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| Started by | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| First post | 2016-03-07 09:40 +0100 |
| Last post | 2016-03-07 09:50 +0100 |
| Articles | 2 — 2 participants |
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Re: [PATCH] thermal: tegra_soctherm: fix sign bit of temperature Thierry Reding <thierry.reding@gmail.com> - 2016-03-07 09:40 +0100
Re: [PATCH] thermal: tegra_soctherm: fix sign bit of temperature Wei Ni <wni@nvidia.com> - 2016-03-07 09:50 +0100
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-03-07 09:40 +0100 |
| Subject | Re: [PATCH] thermal: tegra_soctherm: fix sign bit of temperature |
| Message-ID | <r9YRQ-rn-9@gated-at.bofh.it> |
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On Mon, Feb 29, 2016 at 05:51:20PM +0800, Wei Ni wrote: > The sign bit of temperature readback is bit 0, not bit 1. > Change to BIT(0) to fix it. > > Signed-off-by: Wei Ni <wni@nvidia.com> > --- > drivers/thermal/tegra_soctherm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c > index 74ea5765938b..136975220c92 100644 > --- a/drivers/thermal/tegra_soctherm.c > +++ b/drivers/thermal/tegra_soctherm.c > @@ -57,7 +57,7 @@ > #define READBACK_VALUE_MASK 0xff00 > #define READBACK_VALUE_SHIFT 8 > #define READBACK_ADD_HALF BIT(7) > -#define READBACK_NEGATE BIT(1) > +#define READBACK_NEGATE BIT(0) I haven't found this documented anywhere. The register documentation indicates that the SOC_THERM_TSENSOR_TEMP1 and SOC_THERM_TSENSOR_TEMP2 registers are in some kind of "temp readback format", but I can't find any specification of that format. Can you point me at the source for this information and file an internal bug report so that we can get the documentation updated? Thierry
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| From | Wei Ni <wni@nvidia.com> |
|---|---|
| Date | 2016-03-07 09:50 +0100 |
| Message-ID | <r9Z1w-uU-15@gated-at.bofh.it> |
| In reply to | #1351383 |
On 2016年03月07日 16:38, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Feb 29, 2016 at 05:51:20PM +0800, Wei Ni wrote: >> The sign bit of temperature readback is bit 0, not bit 1. >> Change to BIT(0) to fix it. >> >> Signed-off-by: Wei Ni <wni@nvidia.com> >> --- >> drivers/thermal/tegra_soctherm.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c >> index 74ea5765938b..136975220c92 100644 >> --- a/drivers/thermal/tegra_soctherm.c >> +++ b/drivers/thermal/tegra_soctherm.c >> @@ -57,7 +57,7 @@ >> #define READBACK_VALUE_MASK 0xff00 >> #define READBACK_VALUE_SHIFT 8 >> #define READBACK_ADD_HALF BIT(7) >> -#define READBACK_NEGATE BIT(1) >> +#define READBACK_NEGATE BIT(0) > > I haven't found this documented anywhere. The register documentation > indicates that the SOC_THERM_TSENSOR_TEMP1 and SOC_THERM_TSENSOR_TEMP2 > registers are in some kind of "temp readback format", but I can't find > any specification of that format. Can you point me at the source for > this information and file an internal bug report so that we can get > the documentation updated? Sure, I will do it. Thanks for your comment. > > Thierry > > * Unknown Key > * 0x7F3EB3A1 >
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