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[PATCH 4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type

Started byXing Zheng <zhengxing@rock-chips.com>
First post2016-03-01 11:10 +0100
Last post2016-03-01 11:10 +0100
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  [PATCH 4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type Xing Zheng <zhengxing@rock-chips.com> - 2016-03-01 11:10 +0100

#1346498 — [PATCH 4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type

FromXing Zheng <zhengxing@rock-chips.com>
Date2016-03-01 11:10 +0100
Subject[PATCH 4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Message-ID<r7PpD-7Hb-1@gated-at.bofh.it>
Because there are some frac clock mux nodes don't need gate node on
the RK3399.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk.h |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 36b4938..bfafd67 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -463,6 +463,22 @@ struct rockchip_clk_branch {
 		.child		= ch,				\
 	}
 
+#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
+	{							\
+		.id		= _id,				\
+		.branch_type	= branch_fraction_divider,	\
+		.name		= cname,			\
+		.parent_names	= (const char *[]){ pname },	\
+		.num_parents	= 1,				\
+		.flags		= f,				\
+		.muxdiv_offset	= mo,				\
+		.div_shift	= 16,				\
+		.div_width	= 16,				\
+		.div_flags	= df,				\
+		.gate_offset	= -1,				\
+		.child		= ch,				\
+	}
+
 #define MUX(_id, cname, pnames, f, o, s, w, mf)			\
 	{							\
 		.id		= _id,				\
-- 
1.7.9.5

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