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[PATCH 0/9] ARM: dts: uniphier: UniPhier DT updates for Linux 4.6-rc1 (2nd round)

Started byMasahiro Yamada <yamada.masahiro@socionext.com>
First post2016-02-26 08:20 +0100
Last post2016-02-26 08:30 +0100
Articles 4 — 1 participant

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Contents

  [PATCH 0/9] ARM: dts: uniphier: UniPhier DT updates for Linux 4.6-rc1 (2nd round) Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-02-26 08:20 +0100
    [PATCH 3/9] ARM: dts: uniphier: rework UniPhier System Bus nodes Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-02-26 08:20 +0100
    [PATCH 4/9] ARM: dts: uniphier: add reference clock nodes Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-02-26 08:30 +0100
    [PATCH 5/9] ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-02-26 08:30 +0100

#1343865 — [PATCH 0/9] ARM: dts: uniphier: UniPhier DT updates for Linux 4.6-rc1 (2nd round)

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-02-26 08:20 +0100
Subject[PATCH 0/9] ARM: dts: uniphier: UniPhier DT updates for Linux 4.6-rc1 (2nd round)
Message-ID<r6kQV-86S-3@gated-at.bofh.it>
Hi Olof,

Here is a series for UniPhier DT updates.

It intentionally includes DT updates for ARM 32bit and ARM 64bit
in order to avoid conflicts and build errors.

(Some files in arch/arm64/boot/dts/socionext points to
arch/arm/boot/dts/* by symbolic links, so I needed to
change them atomically.)

Please apply the whole series to one branch.



Masahiro Yamada (9):
  arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20
  ARM: dts: uniphier: factor out ranges property of support card
  ARM: dts: uniphier: rework UniPhier System Bus nodes
  ARM: dts: uniphier: add reference clock nodes
  ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
  ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board
  ARM: dts: uniphier: add PH1-Pro4 Ace board support
  ARM: dts: uniphier: add PH1-Pro4 Sanji board support
  ARM: dts: uniphier: add @{address} to EEPROM node

 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/uniphier-common32.dtsi           |  27 +++--
 arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts         |   8 --
 arch/arm/boot/dts/uniphier-ph1-ld4.dtsi            |   4 +
 arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts        |   8 --
 arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts        | 113 +++++++++++++++++++++
 arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts        |   8 --
 arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts      | 108 ++++++++++++++++++++
 arch/arm/boot/dts/uniphier-ph1-pro4.dtsi           |   4 +
 arch/arm/boot/dts/uniphier-ph1-pro5.dtsi           |   4 +
 arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts        |   8 --
 arch/arm/boot/dts/uniphier-ph1-sld3.dtsi           |  26 +++--
 arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts        |   8 --
 arch/arm/boot/dts/uniphier-ph1-sld8.dtsi           |   4 +
 arch/arm/boot/dts/uniphier-proxstream2-gentil.dts  |  10 ++
 arch/arm/boot/dts/uniphier-proxstream2.dtsi        |   4 +
 arch/arm/boot/dts/uniphier-ref-daughter.dtsi       |   2 +-
 arch/arm/boot/dts/uniphier-support-card.dtsi       |   6 +-
 arch/arm64/boot/dts/socionext/Makefile             |   2 +-
 ...-ph1-ld10-ref.dts => uniphier-ph1-ld20-ref.dts} |  16 +--
 ...iphier-ph1-ld10.dtsi => uniphier-ph1-ld20.dtsi} |  25 +++--
 21 files changed, 315 insertions(+), 82 deletions(-)
 create mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts
 create mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts
 rename arch/arm64/boot/dts/socionext/{uniphier-ph1-ld10-ref.dts => uniphier-ph1-ld20-ref.dts} (88%)
 rename arch/arm64/boot/dts/socionext/{uniphier-ph1-ld10.dtsi => uniphier-ph1-ld20.dtsi} (94%)

-- 
1.9.1

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#1343867 — [PATCH 3/9] ARM: dts: uniphier: rework UniPhier System Bus nodes

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-02-26 08:20 +0100
Subject[PATCH 3/9] ARM: dts: uniphier: rework UniPhier System Bus nodes
Message-ID<r6kQW-86S-23@gated-at.bofh.it>
In reply to#1343865
During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/boot/dts/uniphier-common32.dtsi             | 20 +++++++++++---------
 arch/arm/boot/dts/uniphier-ph1-sld3.dtsi             | 20 +++++++++++---------
 arch/arm/boot/dts/uniphier-support-card.dtsi         |  3 ++-
 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 19 +++++++++++++------
 4 files changed, 37 insertions(+), 25 deletions(-)

diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index ea9301a..f847e68 100644
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -52,12 +52,6 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -98,9 +92,17 @@
 			clocks = <&uart_clk>;
 		};
 
-		system-bus-controller@58c00000 {
-			compatible = "socionext,uniphier-system-bus-controller";
-			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
 		};
 
 		timer@60000200 {
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 691a17d..4c746ea 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -94,12 +94,6 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
 		timer@20000200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x20000200 0x20>;
@@ -216,9 +210,17 @@
 			clock-frequency = <400000>;
 		};
 
-		system-bus-controller@58c00000 {
-			compatible = "socionext,uniphier-system-bus-controller";
-			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
 		};
 
 		usb0: usb@5a800100 {
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index fa807e8..51ecc9b9 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -42,7 +42,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-&extbus {
+&system_bus {
+	status = "okay";
 	ranges = <1 0x00000000 0x42000000 0x02000000>;
 
 	support_card: support_card {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index e6871ea..e682a3f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -133,12 +133,6 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -261,6 +255,19 @@
 			clock-frequency = <400000>;
 		};
 
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
+
 		pinctrl: pinctrl@5f801000 {
 			compatible = "socionext,ph1-ld20-pinctrl", "syscon";
 			reg = <0x5f801000 0xe00>;
-- 
1.9.1

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#1343873 — [PATCH 4/9] ARM: dts: uniphier: add reference clock nodes

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-02-26 08:30 +0100
Subject[PATCH 4/9] ARM: dts: uniphier: add reference clock nodes
Message-ID<r6l0C-8aG-9@gated-at.bofh.it>
In reply to#1343865
Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/boot/dts/uniphier-common32.dtsi    | 7 +++++++
 arch/arm/boot/dts/uniphier-ph1-ld4.dtsi     | 4 ++++
 arch/arm/boot/dts/uniphier-ph1-pro4.dtsi    | 4 ++++
 arch/arm/boot/dts/uniphier-ph1-pro5.dtsi    | 4 ++++
 arch/arm/boot/dts/uniphier-ph1-sld3.dtsi    | 6 ++++++
 arch/arm/boot/dts/uniphier-ph1-sld8.dtsi    | 4 ++++
 arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++++
 7 files changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index f847e68..61a0955 100644
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -45,6 +45,13 @@
 /include/ "skeleton.dtsi"
 
 / {
+	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index 34f0d8d..dadd860 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -173,6 +173,10 @@
 
 };
 
+&refclk {
+	clock-frequency = <24576000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index d78142f..20f3f2a 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -195,6 +195,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 2f389ea..24f6f66 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -189,6 +189,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <20000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 4c746ea..03292f4 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -68,6 +68,12 @@
 	};
 
 	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index 7d06a1c..6bfd29a 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -172,6 +172,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 6bd353f..4ac484c 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -200,6 +200,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };
-- 
1.9.1

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#1343874 — [PATCH 5/9] ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-02-26 08:30 +0100
Subject[PATCH 5/9] ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
Message-ID<r6l0C-8aG-11@gated-at.bofh.it>
In reply to#1343865
This board has an EEPROM (STMicroelectronics M24C64-WMN6TP) connected
to the I2C channel 0 of the SoC.  Its slave address is 0x54.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/boot/dts/uniphier-proxstream2-gentil.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
index 9d7ec5c..0da3018 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
@@ -75,4 +75,9 @@
 
 &i2c0 {
 	status = "okay";
+
+	eeprom@54 {
+		compatible = "st,24c64";
+		reg = <0x54>;
+	};
 };
-- 
1.9.1

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