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| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2016-02-25 20:40 +0100 |
| Last post | 2016-02-25 20:40 +0100 |
| Articles | 1 — 1 participant |
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Re: [PATCH v5 2/4] dts: sun8i-h3: Add APB0 related clocks and resets Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-25 20:40 +0100
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-02-25 20:40 +0100 |
| Subject | Re: [PATCH v5 2/4] dts: sun8i-h3: Add APB0 related clocks and resets |
| Message-ID | <r69Vw-9g-19@gated-at.bofh.it> |
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On Mon, Feb 22, 2016 at 02:03:26PM +0100, Krzysztof Adamski wrote: > APB0 is bearly mentioned in H3 User Manual and it is only setup in the > Allwinners kernel dump for CIR. I have verified experimentally that the > gate for R_PIO exists and works, though. There are probably other gates > there but I don't know their order right now and I don't have access to > their peripherals on my board to test them. > > After some experiments and reviewing how this is organized on other > sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO > and they are working properly without doing anything so I assume they > are connected straight to the 24Mhz oscillator for now. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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