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[PATCH 00/12] ARM: dts: apq8064: spi and i2c dt patches

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  [PATCH 00/12] ARM: dts: apq8064: spi and i2c dt patches Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2016-02-23 15:20 +0100
    [PATCH 03/12] ARM: dts: apq8064: add pci support in CM QS600 Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2016-02-23 15:20 +0100
    [PATCH 06/12] ARM: dts: ifc6410: enable spi device on expansion Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2016-02-23 15:20 +0100
    [PATCH 04/12] ARM: dts: apq8064: add i2c sleep pinctrl states. Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2016-02-23 15:20 +0100

#1340677 — [PATCH 00/12] ARM: dts: apq8064: spi and i2c dt patches

Hi Andy, 

Here are some apq8064 dts patches which are mostly to do with spi and i2c.

Most of the patches are additions of missing nodes required for ifc6410.

thanks,
srini

Srinivas Kandagatla (12):
  ARM: dts: qcom: fix i2c lables to be inline with others
  ARM: dts: apq8064: move pinctrls to dedicated dtsi
  ARM: dts: apq8064: add pci support in CM QS600
  ARM: dts: apq8064: add i2c sleep pinctrl states.
  ARM: dts: apq8064: add spi5 device node.
  ARM: dts: ifc6410: enable spi device on expansion
  ARM: dts: apq8064: add missing i2c2 pinctrl info
  ARM: dts: ifc6410: enable i2c2 on expansion connector
  ARM: dts: apq8064: add gsbi4 with i2c node.
  ARM: dts: ifc6410: enable cam i2c device
  ARM: dts: apq8064: add i2c6 device node.
  ARM: dts: ifc6410: add correct aliases to the i2c and spi bus

 arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts |  27 ++++
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts  |  35 ++++-
 arch/arm/boot/dts/qcom-apq8064-pins.dtsi    | 208 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi         | 126 ++++++++---------
 4 files changed, 329 insertions(+), 67 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-apq8064-pins.dtsi

-- 
1.9.1

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#1340681 — [PATCH 03/12] ARM: dts: apq8064: add pci support in CM QS600

This patch adds PCIE support to APQ8064, tested with Ethernet on
Compulab QS600 board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index 21095da..35f1d46 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -37,6 +37,18 @@
 					bias-disable;
 				};
 			};
+
+			pcie_pins: pcie_pinmux {
+				mux {
+					pins = "gpio27";
+					function = "gpio";
+				};
+				conf {
+					pins = "gpio27";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
 		};
 
 		rpm@108000 {
@@ -103,6 +115,11 @@
 					regulator-max-microvolt = <1900000>;
 					bias-pull-down;
 				};
+
+				pm8921_lvs6: lvs6 {
+					bias-pull-down;
+				};
+
 			};
 		};
 
@@ -195,6 +212,16 @@
 			};
 		};
 
+		pci@1b500000 {
+			status = "ok";
+			vdda-supply = <&pm8921_s3>;
+			vdda_phy-supply = <&pm8921_lvs6>;
+			vdda_refclk-supply = <&v3p3_fixed>;
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+			perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+		};
+
 		amba {
 			/* eMMC */
 			sdcc1: sdcc@12400000 {
-- 
1.9.1

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#1340682 — [PATCH 06/12] ARM: dts: ifc6410: enable spi device on expansion

This patch enables spi device on the 30 pin expansion connector.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 0073294..8de774c 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -178,6 +178,16 @@
 			};
 		};
 
+		gsbi@1a200000 {
+			qcom,mode = <GSBI_PROT_SPI>;
+			status = "okay";
+			spi4: spi@1a280000 {
+				status = "okay";
+				num-cs = <1>;
+				cs-gpios = <&tlmm_pinmux 53 0>;
+			};
+		};
+
 		gsbi@16500000 {
 			status = "ok";
 			qcom,mode = <GSBI_PROT_UART_W_FC>;
-- 
1.9.1

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#1340684 — [PATCH 04/12] ARM: dts: apq8064: add i2c sleep pinctrl states.

This patch adds missing i2c pinctrl sleep states.
Also add 16mA drive strength to the pins so that we can detect wide
range of i2c devices on the other side of level shifters.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 36 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi      |  8 +++----
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index c711aca..ce15c67 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -19,6 +19,24 @@
 			pins = "gpio20", "gpio21";
 			function = "gsbi1";
 		};
+
+		pinconf {
+			pins = "gpio20", "gpio21";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c1_pins_sleep: i2c1_pins_sleep {
+		mux {
+			pins = "gpio20", "gpio21";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio20", "gpio21";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
 	};
 
 	i2c3_pins: i2c3 {
@@ -26,6 +44,24 @@
 			pins = "gpio8", "gpio9";
 			function = "gsbi3";
 		};
+
+		pinconf {
+			pins = "gpio8", "gpio9";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c3_pins_sleep: i2c3_pins_sleep {
+		mux {
+			pins = "gpio8", "gpio9";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio8", "gpio9";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
 	};
 
 	gsbi6_uart_2pins: gsbi6_uart_2pins {
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 3d95534b..3fb66b9 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -227,8 +227,8 @@
 
 			gsbi1_i2c: i2c@12460000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
-				pinctrl-0 = <&i2c1_pins>;
-				pinctrl-names = "default";
+				pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
+				pinctrl-names = "default", "sleep";
 				reg = <0x12460000 0x1000>;
 				interrupts = <0 194 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
@@ -274,8 +274,8 @@
 			ranges;
 			gsbi3_i2c: i2c@16280000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
-				pinctrl-0 = <&i2c3_pins>;
-				pinctrl-names = "default";
+				pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
+				pinctrl-names = "default", "sleep";
 				reg = <0x16280000 0x1000>;
 				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI3_QUP_CLK>,
-- 
1.9.1

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