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[PATCH 00/13] arm-cci: PMU driver updates for 4.6

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  [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 05/13] arm-cci: Delay PMU counter writes to pmu::pmu_enable Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 07/13] arm-cci: Get the status of a counter Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 03/13] arm-cci: Group writes to counter Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 06/13] arm-cci: write_counter: Remove redundant check Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 09/13] arm-cci: Add helper to enable PMU without synchornising counters Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 08/13] arm-cci: Add routines to save/restore all counters Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    [PATCH 11/13] arm-cci: CCI-500: Work around PMU counter writes Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-02-23 12:00 +0100
    Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Will Deacon <will.deacon@arm.com> - 2016-02-23 12:50 +0100
      Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2016-02-23 15:00 +0100
        Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Olof Johansson <olof@lixom.net> - 2016-02-24 18:00 +0100
          Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Will Deacon <will.deacon@arm.com> - 2016-02-24 18:20 +0100
            Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Olof Johansson <olof@lixom.net> - 2016-02-24 19:50 +0100
              Re: [PATCH 00/13] arm-cci: PMU driver updates for 4.6 Will Deacon <will.deacon@arm.com> - 2016-02-26 17:50 +0100

#1340534 — [PATCH 00/13] arm-cci: PMU driver updates for 4.6

Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
applies on top of v4.5-rc5.

Highlights include :
 - Support for CoreLink CCI-550 PMU
 - Reliable writes to PMU Counter registers for CCI-500/550.

All the patches have been Acked. Please let me know how this
can be merged.

Andrzej Hajda (1):
  arm-cci: fix handling cpumask_any_but return value

Mark Rutland (1):
  arm-cci: simplify sysfs attr handling

Suzuki K Poulose (11):
  arm-cci: Group writes to counter
  arm-cci: Refactor CCI PMU enable/disable methods
  arm-cci: Delay PMU counter writes to pmu::pmu_enable
  arm-cci: write_counter: Remove redundant check
  arm-cci: Get the status of a counter
  arm-cci: Add routines to save/restore all counters
  arm-cci: Add helper to enable PMU without synchornising counters
  arm-cci: Provide hook for writing to PMU counters
  arm-cci: CCI-500: Work around PMU counter writes
  arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
  arm-cci: CoreLink CCI-550 PMU driver

 Documentation/devicetree/bindings/arm/cci.txt |    2 +
 drivers/bus/Kconfig                           |   10 +-
 drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
 3 files changed, 427 insertions(+), 197 deletions(-)

-- 
1.7.9.5

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#1340535 — [PATCH 05/13] arm-cci: Delay PMU counter writes to pmu::pmu_enable

CCI PMU driver always reprograms the counters to a safe value (half of the
counter max, = 2^31) before starting the profiling to account for extreme
interrupt latencies. Also, the cost of writing to a PMU counter could be
very costly on some PMUs(e.g, CCI-500). In order to ammortise the cost of
programming the counters, this patch delays the counter writes to pmu::pmu_enable().
We use the PER_HES_ARCH flag to keep track of the counters which need to
be programmed. Before turning on the PMU, we go through the counters that
were marked for write, and perform the operation in a batch.

To unify all the counter writes to pmu_enable(), this patch also makes sure that
we disable-and-enable the PMU in the irq handler to program any counters that
overflowed.

Cc: Punit Agrawal <punit.agrawal@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   57 ++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 52 insertions(+), 5 deletions(-)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index e42842b..629c9e0 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -159,6 +159,8 @@ enum cci_models {
 	CCI_MODEL_MAX
 };
 
+static void pmu_write_counters(struct cci_pmu *cci_pmu,
+				 unsigned long *mask);
 static ssize_t cci_pmu_format_show(struct device *dev,
 			struct device_attribute *attr, char *buf);
 static ssize_t cci_pmu_event_show(struct device *dev,
@@ -606,11 +608,44 @@ static int cci500_validate_hw_event(struct cci_pmu *cci_pmu,
 }
 #endif	/* CONFIG_ARM_CCI500_PMU */
 
+/*
+ * Program the CCI PMU counters which have PERF_HES_ARCH set
+ * with the event period and mark them ready before we enable
+ * PMU.
+ */
+void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
+{
+	int i;
+	struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
+
+	DECLARE_BITMAP(mask, cci_pmu->num_cntrs);
+
+	bitmap_zero(mask, cci_pmu->num_cntrs);
+	for_each_set_bit(i, cci_pmu->hw_events.used_mask, cci_pmu->num_cntrs) {
+		struct perf_event *event = cci_hw->events[i];
+
+		if (WARN_ON(!event))
+			continue;
+
+		/* Leave the events which are not counting */
+		if (event->hw.state & PERF_HES_STOPPED)
+			continue;
+		if (event->hw.state & PERF_HES_ARCH) {
+			set_bit(i, mask);
+			event->hw.state &= ~PERF_HES_ARCH;
+		}
+	}
+
+	pmu_write_counters(cci_pmu, mask);
+}
+
 /* Should be called with cci_pmu->hw_events->pmu_lock held */
-static void __cci_pmu_enable(void)
+static void __cci_pmu_enable(struct cci_pmu *cci_pmu)
 {
 	u32 val;
 
+	cci_pmu_sync_counters(cci_pmu);
+
 	/* Enable all the PMU counters. */
 	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
 	writel(val, cci_ctrl_base + CCI_PMCR);
@@ -791,8 +826,7 @@ static void pmu_write_counter(struct perf_event *event, u32 value)
 		pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
 }
 
-static void __maybe_unused
-pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
 {
 	int i;
 	struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
@@ -840,7 +874,14 @@ void pmu_event_set_period(struct perf_event *event)
 	 */
 	u64 val = 1ULL << 31;
 	local64_set(&hwc->prev_count, val);
-	pmu_write_counter(event, val);
+
+	/*
+	 * CCI PMU uses PERF_HES_ARCH to keep track of the counters, whose
+	 * values needs to be sync-ed with the s/w state before the PMU is
+	 * enabled.
+	 * Mark this counter for sync.
+	 */
+	hwc->state |= PERF_HES_ARCH;
 }
 
 static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
@@ -851,6 +892,9 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
 	int idx, handled = IRQ_NONE;
 
 	raw_spin_lock_irqsave(&events->pmu_lock, flags);
+
+	/* Disable the PMU while we walk through the counters */
+	__cci_pmu_disable();
 	/*
 	 * Iterate over counters and update the corresponding perf events.
 	 * This should work regardless of whether we have per-counter overflow
@@ -877,6 +921,9 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
 		pmu_event_set_period(event);
 		handled = IRQ_HANDLED;
 	}
+
+	/* Enable the PMU and sync possibly overflowed counters */
+	__cci_pmu_enable(cci_pmu);
 	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 
 	return IRQ_RETVAL(handled);
@@ -920,7 +967,7 @@ static void cci_pmu_enable(struct pmu *pmu)
 		return;
 
 	raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
-	__cci_pmu_enable();
+	__cci_pmu_enable(cci_pmu);
 	raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
 
 }
-- 
1.7.9.5

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#1340536 — [PATCH 07/13] arm-cci: Get the status of a counter

Add helper routines to check if the counter is enabled or not.

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 420c30c..d289037 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -707,6 +707,12 @@ static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx)
 	pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL);
 }
 
+static bool __maybe_unused
+pmu_counter_is_enabled(struct cci_pmu *cci_pmu, int idx)
+{
+	return (pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR_CTRL) & 0x1) != 0;
+}
+
 static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
 {
 	pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL);
-- 
1.7.9.5

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#1340537 — [PATCH 03/13] arm-cci: Group writes to counter

Add a helper to group the writes to PMU counter, this will be
used to delay setting the event period to pmu::pmu_enable()

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 5fb1c06..6a76ac7 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -771,6 +771,21 @@ static void pmu_write_counter(struct perf_event *event, u32 value)
 		pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
 }
 
+static void __maybe_unused
+pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+	struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
+
+	for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
+		struct perf_event *event = cci_hw->events[i];
+
+		if (WARN_ON(!event))
+			continue;
+		pmu_write_counter(event, local64_read(&event->hw.prev_count));
+	}
+}
+
 static u64 pmu_event_update(struct perf_event *event)
 {
 	struct hw_perf_event *hwc = &event->hw;
-- 
1.7.9.5

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#1340538 — [PATCH 06/13] arm-cci: write_counter: Remove redundant check

pmu_write_counter() is now only called from pmu_write_counters(),
which does so for each set index in the given mask, bounded by
cci_pmu->num_cntrs. So, there is no need for an extra check to
make sure the given counter is valid inside pmu_write_counter.
This patch gets rid of that.

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 629c9e0..420c30c 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -814,16 +814,9 @@ static u32 pmu_read_counter(struct perf_event *event)
 	return value;
 }
 
-static void pmu_write_counter(struct perf_event *event, u32 value)
+static void pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx)
 {
-	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
-	struct hw_perf_event *hw_counter = &event->hw;
-	int idx = hw_counter->idx;
-
-	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx)))
-		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
-	else
-		pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
+	pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
 }
 
 static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
@@ -836,7 +829,7 @@ static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
 
 		if (WARN_ON(!event))
 			continue;
-		pmu_write_counter(event, local64_read(&event->hw.prev_count));
+		pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
 	}
 }
 
-- 
1.7.9.5

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#1340539 — [PATCH 09/13] arm-cci: Add helper to enable PMU without synchornising counters

On CCI-500 writing to a counter requires turning the PMU on. So,
synchronising the counter state should not be performed for such special cases,
while turning the PMU on. This patch adds a helper, __cci_pmu_enable_nosync(),
without flushing the counter states.

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 7ce7da0..bcc4c59 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -640,18 +640,23 @@ void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
 }
 
 /* Should be called with cci_pmu->hw_events->pmu_lock held */
-static void __cci_pmu_enable(struct cci_pmu *cci_pmu)
+static void __cci_pmu_enable_nosync(struct cci_pmu *cci_pmu)
 {
 	u32 val;
 
-	cci_pmu_sync_counters(cci_pmu);
-
 	/* Enable all the PMU counters. */
 	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
 	writel(val, cci_ctrl_base + CCI_PMCR);
 }
 
 /* Should be called with cci_pmu->hw_events->pmu_lock held */
+static void __cci_pmu_enable_sync(struct cci_pmu *cci_pmu)
+{
+	cci_pmu_sync_counters(cci_pmu);
+	__cci_pmu_enable_nosync(cci_pmu);
+}
+
+/* Should be called with cci_pmu->hw_events->pmu_lock held */
 static void __cci_pmu_disable(void)
 {
 	u32 val;
@@ -960,7 +965,7 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
 	}
 
 	/* Enable the PMU and sync possibly overflowed counters */
-	__cci_pmu_enable(cci_pmu);
+	__cci_pmu_enable_sync(cci_pmu);
 	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 
 	return IRQ_RETVAL(handled);
@@ -1004,7 +1009,7 @@ static void cci_pmu_enable(struct pmu *pmu)
 		return;
 
 	raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
-	__cci_pmu_enable(cci_pmu);
+	__cci_pmu_enable_sync(cci_pmu);
 	raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags);
 
 }
-- 
1.7.9.5

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#1340540 — [PATCH 08/13] arm-cci: Add routines to save/restore all counters

Adds helper routines to disable the counter controls for
all the counters on the CCI PMU and restore it back, by
preserving the original state in caller provided mask.

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index d289037..7ce7da0 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -719,6 +719,44 @@ static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
 }
 
 /*
+ * For all counters on the CCI-PMU, disable any 'enabled' counters,
+ * saving the changed counters in the mask, so that we can restore
+ * it later using pmu_restore_counters. The mask is private to the
+ * caller. We cannot rely on the used_mask maintained by the CCI_PMU
+ * as it only tells us if the counter is assigned to perf_event or not.
+ * The state of the perf_event cannot be locked by the PMU layer, hence
+ * we check the individual counter status (which can be locked by
+ * cci_pm->hw_events->pmu_lock).
+ *
+ * @mask should be initialised to empty by the caller.
+ */
+static void __maybe_unused
+pmu_save_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+
+	for (i = 0; i < cci_pmu->num_cntrs; i++) {
+		if (pmu_counter_is_enabled(cci_pmu, i)) {
+			set_bit(i, mask);
+			pmu_disable_counter(cci_pmu, i);
+		}
+	}
+}
+
+/*
+ * Restore the status of the counters. Reversal of the pmu_save_counters().
+ * For each counter set in the mask, enable the counter back.
+ */
+static void __maybe_unused
+pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+
+	for_each_set_bit(i, mask, cci_pmu->num_cntrs)
+		pmu_enable_counter(cci_pmu, i);
+}
+
+/*
  * Returns the number of programmable counters actually implemented
  * by the cci
  */
-- 
1.7.9.5

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#1340542 — [PATCH 11/13] arm-cci: CCI-500: Work around PMU counter writes

The CCI PMU driver sets the event counter to the half of the maximum
value(2^31) it can count before we start the counters via
pmu_event_set_period(). This is done to give us the best chance to
handle the overflow interrupt, taking care of extreme interrupt latencies.

However, CCI-500 comes with advanced power saving schemes, which
disables the clock to the event counters unless the counters are enabled to
count (PMCR.CEN). This prevents the driver from writing the period to the
counters before starting them.  Also, there is no way we can reset the
individual event counter to 0 (PMCR.RST resets all the counters, losing
their current readings). However the value of the counter is preserved and
could be read back, when the counters are not enabled.

So we cannot reliably use the counters and compute the number of events
generated during the sampling period since we don't have the value of the
counter at start.

This patch works around this issue by changing writes to the counter
with the following steps.

 1) Disable all the counters (remembering any counters which were enabled)
 2) Enable the PMU, now that all the counters are disabled.

 For each counter to be programmed, repeat steps 3-7
 3) Save the current event and program the target counter to count an
    invalid event, which by spec is guaranteed to not-generate any events.
 4) Enable the target counter.
 5) Write to the target counter.
 6) Disable the target counter
 7) Restore the event back on the target counter.

 8) Disable the PMU
 9) Restore the status of the all the counters

Cc: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/bus/arm-cci.c |   66 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index f1d3f47..ebb2f1e 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -891,6 +891,71 @@ static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
 		__pmu_write_counters(cci_pmu, mask);
 }
 
+#ifdef CONFIG_ARM_CCI500_PMU
+
+/*
+ * CCI-500 has advanced power saving policies, which could gate the
+ * clocks to the PMU counters, which makes the writes to them ineffective.
+ * The only way to write to those counters is when the global counters
+ * are enabled and the particular counter is enabled.
+ *
+ * So we do the following :
+ *
+ * 1) Disable all the PMU counters, saving their current state
+ * 2) Enable the global PMU profiling, now that all counters are
+ *    disabled.
+ *
+ * For each counter to be programmed, repeat steps 3-7:
+ *
+ * 3) Write an invalid event code to the event control register for the
+      counter, so that the counters are not modified.
+ * 4) Enable the counter control for the counter.
+ * 5) Set the counter value
+ * 6) Disable the counter
+ * 7) Restore the event in the target counter
+ *
+ * 8) Disable the global PMU.
+ * 9) Restore the status of the rest of the counters.
+ *
+ * We choose an event which for CCI-500 is guaranteed not to count.
+ * We use the highest possible event code (0x1f) for the master interface 0.
+ */
+#define CCI500_INVALID_EVENT	((CCI500_PORT_M0 << CCI500_PMU_EVENT_SOURCE_SHIFT) | \
+				 (CCI500_PMU_EVENT_CODE_MASK << CCI500_PMU_EVENT_CODE_SHIFT))
+static void cci500_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
+{
+	int i;
+	DECLARE_BITMAP(saved_mask, cci_pmu->num_cntrs);
+
+	bitmap_zero(saved_mask, cci_pmu->num_cntrs);
+	pmu_save_counters(cci_pmu, saved_mask);
+
+	/*
+	 * Now that all the counters are disabled, we can safely turn the PMU on,
+	 * without syncing the status of the counters
+	 */
+	__cci_pmu_enable_nosync(cci_pmu);
+
+	for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
+		struct perf_event *event = cci_pmu->hw_events.events[i];
+
+		if (WARN_ON(!event))
+			continue;
+
+		pmu_set_event(cci_pmu, i, CCI500_INVALID_EVENT);
+		pmu_enable_counter(cci_pmu, i);
+		pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
+		pmu_disable_counter(cci_pmu, i);
+		pmu_set_event(cci_pmu, i, event->hw.config_base);
+	}
+
+	__cci_pmu_disable();
+
+	pmu_restore_counters(cci_pmu, saved_mask);
+}
+
+#endif	/* CONFIG_ARM_CCI500_PMU */
+
 static u64 pmu_event_update(struct perf_event *event)
 {
 	struct hw_perf_event *hwc = &event->hw;
@@ -1475,6 +1540,7 @@ static struct cci_pmu_model cci_pmu_models[] = {
 			},
 		},
 		.validate_hw_event = cci500_validate_hw_event,
+		.write_counters	= cci500_pmu_write_counters,
 	},
 #endif
 };
-- 
1.7.9.5

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#1340562

On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
> Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
> applies on top of v4.5-rc5.
> 
> Highlights include :
>  - Support for CoreLink CCI-550 PMU
>  - Reliable writes to PMU Counter registers for CCI-500/550.
> 
> All the patches have been Acked. Please let me know how this
> can be merged.
> 
> Andrzej Hajda (1):
>   arm-cci: fix handling cpumask_any_but return value
> 
> Mark Rutland (1):
>   arm-cci: simplify sysfs attr handling
> 
> Suzuki K Poulose (11):
>   arm-cci: Group writes to counter
>   arm-cci: Refactor CCI PMU enable/disable methods
>   arm-cci: Delay PMU counter writes to pmu::pmu_enable
>   arm-cci: write_counter: Remove redundant check
>   arm-cci: Get the status of a counter
>   arm-cci: Add routines to save/restore all counters
>   arm-cci: Add helper to enable PMU without synchornising counters
>   arm-cci: Provide hook for writing to PMU counters
>   arm-cci: CCI-500: Work around PMU counter writes
>   arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
>   arm-cci: CoreLink CCI-550 PMU driver
> 
>  Documentation/devicetree/bindings/arm/cci.txt |    2 +
>  drivers/bus/Kconfig                           |   10 +-
>  drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
>  3 files changed, 427 insertions(+), 197 deletions(-)

How do you plan to merge this? I can take it all onto a branch for
arm-soc, or I can include it on my perf/updates branch, or ...?

Will

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#1340645

On 23/02/16 11:40, Will Deacon wrote:
> On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
>> Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
>> applies on top of v4.5-rc5.
>>
>> Highlights include :
>>   - Support for CoreLink CCI-550 PMU
>>   - Reliable writes to PMU Counter registers for CCI-500/550.
>>
>> All the patches have been Acked. Please let me know how this
>> can be merged.

>>
>>   Documentation/devicetree/bindings/arm/cci.txt |    2 +
>>   drivers/bus/Kconfig                           |   10 +-
>>   drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
>>   3 files changed, 427 insertions(+), 197 deletions(-)
>
> How do you plan to merge this? I can take it all onto a branch for
> arm-soc, or I can include it on my perf/updates branch, or ...?

Arnd, Olof,

What do you think would be the best route ?

Cheers
Suzuki

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#1342213

On Tue, Feb 23, 2016 at 01:55:51PM +0000, Suzuki K. Poulose wrote:
> On 23/02/16 11:40, Will Deacon wrote:
> >On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
> >>Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
> >>applies on top of v4.5-rc5.
> >>
> >>Highlights include :
> >>  - Support for CoreLink CCI-550 PMU
> >>  - Reliable writes to PMU Counter registers for CCI-500/550.
> >>
> >>All the patches have been Acked. Please let me know how this
> >>can be merged.
> 
> >>
> >>  Documentation/devicetree/bindings/arm/cci.txt |    2 +
> >>  drivers/bus/Kconfig                           |   10 +-
> >>  drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
> >>  3 files changed, 427 insertions(+), 197 deletions(-)
> >
> >How do you plan to merge this? I can take it all onto a branch for
> >arm-soc, or I can include it on my perf/updates branch, or ...?
> 
> Arnd, Olof,
> 
> What do you think would be the best route ?

Traditionally we've been picking these up in arm-soc in our drivers branch.

Will, unless you want them in your tree for some reason that's what I'll do
here as well.


-Olof

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#1342235

On Wed, Feb 24, 2016 at 08:58:14AM -0800, Olof Johansson wrote:
> On Tue, Feb 23, 2016 at 01:55:51PM +0000, Suzuki K. Poulose wrote:
> > On 23/02/16 11:40, Will Deacon wrote:
> > >On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
> > >>Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
> > >>applies on top of v4.5-rc5.
> > >>
> > >>Highlights include :
> > >>  - Support for CoreLink CCI-550 PMU
> > >>  - Reliable writes to PMU Counter registers for CCI-500/550.
> > >>
> > >>All the patches have been Acked. Please let me know how this
> > >>can be merged.
> > 
> > >>
> > >>  Documentation/devicetree/bindings/arm/cci.txt |    2 +
> > >>  drivers/bus/Kconfig                           |   10 +-
> > >>  drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
> > >>  3 files changed, 427 insertions(+), 197 deletions(-)
> > >
> > >How do you plan to merge this? I can take it all onto a branch for
> > >arm-soc, or I can include it on my perf/updates branch, or ...?
> > 
> > Arnd, Olof,
> > 
> > What do you think would be the best route ?
> 
> Traditionally we've been picking these up in arm-soc in our drivers branch.
> 
> Will, unless you want them in your tree for some reason that's what I'll do
> here as well.

Just that I already have some CPU PMU patches that I planned to send, so
I could bundle these in with those if necessary. I have no preference
either way though, as long as they get queued someplace.

At some point, those drivers should be largely moved from drivers/bus/
to drivers/perf/, but that's a separate issue.

Will

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#1342331

On Wed, Feb 24, 2016 at 9:12 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Wed, Feb 24, 2016 at 08:58:14AM -0800, Olof Johansson wrote:
>> On Tue, Feb 23, 2016 at 01:55:51PM +0000, Suzuki K. Poulose wrote:
>> > On 23/02/16 11:40, Will Deacon wrote:
>> > >On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
>> > >>Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
>> > >>applies on top of v4.5-rc5.
>> > >>
>> > >>Highlights include :
>> > >>  - Support for CoreLink CCI-550 PMU
>> > >>  - Reliable writes to PMU Counter registers for CCI-500/550.
>> > >>
>> > >>All the patches have been Acked. Please let me know how this
>> > >>can be merged.
>> >
>> > >>
>> > >>  Documentation/devicetree/bindings/arm/cci.txt |    2 +
>> > >>  drivers/bus/Kconfig                           |   10 +-
>> > >>  drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
>> > >>  3 files changed, 427 insertions(+), 197 deletions(-)
>> > >
>> > >How do you plan to merge this? I can take it all onto a branch for
>> > >arm-soc, or I can include it on my perf/updates branch, or ...?
>> >
>> > Arnd, Olof,
>> >
>> > What do you think would be the best route ?
>>
>> Traditionally we've been picking these up in arm-soc in our drivers branch.
>>
>> Will, unless you want them in your tree for some reason that's what I'll do
>> here as well.
>
> Just that I already have some CPU PMU patches that I planned to send, so
> I could bundle these in with those if necessary. I have no preference
> either way though, as long as they get queued someplace.

Ok, I'm alright with you queueing these if that makes it easier. Feel
free to add:

Acked-by: Olof Johansson <olof@lixom.net>

Only concern is if we cause confusion on where people should send
these patches down the road, but there aren't that many authors of
them so it's not a huge problem.

> At some point, those drivers should be largely moved from drivers/bus/
> to drivers/perf/, but that's a separate issue.

And with a maintainer on that, that'd resolve the "where do I send
this" issue. The maintainer, of course, needs to know where to feed
things next, but that's easier to solve.


-Olof

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#1344446

On Wed, Feb 24, 2016 at 10:46:09AM -0800, Olof Johansson wrote:
> On Wed, Feb 24, 2016 at 9:12 AM, Will Deacon <will.deacon@arm.com> wrote:
> > On Wed, Feb 24, 2016 at 08:58:14AM -0800, Olof Johansson wrote:
> >> On Tue, Feb 23, 2016 at 01:55:51PM +0000, Suzuki K. Poulose wrote:
> >> > On 23/02/16 11:40, Will Deacon wrote:
> >> > >On Tue, Feb 23, 2016 at 10:49:42AM +0000, Suzuki K Poulose wrote:
> >> > >>Here are some fixes and updates for arm-cci pmu driver targeting v4.6,
> >> > >>applies on top of v4.5-rc5.
> >> > >>
> >> > >>Highlights include :
> >> > >>  - Support for CoreLink CCI-550 PMU
> >> > >>  - Reliable writes to PMU Counter registers for CCI-500/550.
> >> > >>
> >> > >>All the patches have been Acked. Please let me know how this
> >> > >>can be merged.
> >> >
> >> > >>
> >> > >>  Documentation/devicetree/bindings/arm/cci.txt |    2 +
> >> > >>  drivers/bus/Kconfig                           |   10 +-
> >> > >>  drivers/bus/arm-cci.c                         |  612 +++++++++++++++++--------
> >> > >>  3 files changed, 427 insertions(+), 197 deletions(-)
> >> > >
> >> > >How do you plan to merge this? I can take it all onto a branch for
> >> > >arm-soc, or I can include it on my perf/updates branch, or ...?
> >> >
> >> > Arnd, Olof,
> >> >
> >> > What do you think would be the best route ?
> >>
> >> Traditionally we've been picking these up in arm-soc in our drivers branch.
> >>
> >> Will, unless you want them in your tree for some reason that's what I'll do
> >> here as well.
> >
> > Just that I already have some CPU PMU patches that I planned to send, so
> > I could bundle these in with those if necessary. I have no preference
> > either way though, as long as they get queued someplace.
> 
> Ok, I'm alright with you queueing these if that makes it easier. Feel
> free to add:
> 
> Acked-by: Olof Johansson <olof@lixom.net>

Thanks, Olof. I'll queue them shortly.

> Only concern is if we cause confusion on where people should send
> these patches down the road, but there aren't that many authors of
> them so it's not a huge problem.

Yup. It's pretty much a handful of @arm.com people.

> > At some point, those drivers should be largely moved from drivers/bus/
> > to drivers/perf/, but that's a separate issue.
> 
> And with a maintainer on that, that'd resolve the "where do I send
> this" issue. The maintainer, of course, needs to know where to feed
> things next, but that's easier to solve.

I'm down for the arm-pmu.c, so I'm happy to own the interconnect PMUs
too, but I'll need to sit down and extract the drivers first.

Will

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