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Groups > linux.kernel > #1339456 > unrolled thread
| Started by | Krzysztof Adamski <k@japko.eu> |
|---|---|
| First post | 2016-02-22 14:10 +0100 |
| Last post | 2016-02-22 14:10 +0100 |
| Articles | 5 — 1 participant |
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[PATCH v5 0/4] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-22 14:10 +0100
[PATCH v5 1/4] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-22 14:10 +0100
[PATCH v5 2/4] dts: sun8i-h3: Add APB0 related clocks and resets Krzysztof Adamski <k@japko.eu> - 2016-02-22 14:10 +0100
[PATCH v5 3/4] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi Krzysztof Adamski <k@japko.eu> - 2016-02-22 14:10 +0100
[PATCH v5 4/4] ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards Krzysztof Adamski <k@japko.eu> - 2016-02-22 14:10 +0100
| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-22 14:10 +0100 |
| Subject | [PATCH v5 0/4] pinctrl: sunxi: Add H3 R_PIO controller support |
| Message-ID | <r4Yps-6jn-9@gated-at.bofh.it> |
This patch series is extension of my original single patch with the same subject. It adds support for R_PIO so that GPIO port L can be used in H3 based devices. It was tested on OrangePi PC and OrangePi Plus where PL is connected amount others to an onboard led, a switch, an IR receiver and some VCC controllers. Patchset is based on next-20160222. --- Changes since v4: - remove patches that are alredy merged - add patch describing leds and switch in DT Changes since v3: - collect some acked-bys - fix r_pios #interrupt-cells Changes since v2: - fixed apb0 parrent clocks list - moved binding documentation change to the proper patch - simplified sunxi_pinctrl_gpio_get according to ChenYu suggestions - fixed ordering in sunxi binding documentation Changes since v1: - splited patch to two separate - dtsi and c files - added APB0 clocks a parent for R_PIO - added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq mode and on 2nd pinctrl - fixed a "pwn" > "pwm" typo - fixed order in allwinner,sunxi-pinctrl.txt Krzysztof Adamski (4): clk: sunxi: Add apb0 gates for H3 dts: sun8i-h3: Add APB0 related clocks and resets ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards Krzysztof Adamski (4): clk: sunxi: Add apb0 gates for H3 dts: sun8i-h3: Add APB0 related clocks and resets ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards Documentation/devicetree/bindings/clock/sunxi.txt | 2 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63 +++++++++++++++++++++++ arch/arm/boot/dts/sun8i-h3.dtsi | 37 +++++++++++++ drivers/clk/sunxi/clk-simple-gates.c | 4 ++ 4 files changed, 106 insertions(+) -- 2.1.4
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| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-22 14:10 +0100 |
| Subject | [PATCH v5 1/4] clk: sunxi: Add apb0 gates for H3 |
| Message-ID | <r4Yps-6jn-15@gated-at.bofh.it> |
| In reply to | #1339456 |
This patch adds support for APB0 in H3. It seems to be compatible with earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, etc). Signed-off-by: Krzysztof Adamski <k@japko.eu> --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++ drivers/clk/sunxi/clk-simple-gates.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index c09f59b..834436f 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -18,6 +18,7 @@ Required properties: "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-a10-axi-clk" - for the AXI clock "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 + "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates "allwinner,sun4i-a10-ahb-clk" - for the AHB clock "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 @@ -46,6 +47,7 @@ Required properties: "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 + "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c index 2cfc5a8..d7ec2dc 100644 --- a/drivers/clk/sunxi/clk-simple-gates.c +++ b/drivers/clk/sunxi/clk-simple-gates.c @@ -98,6 +98,8 @@ static void __init sunxi_simple_gates_init(struct device_node *node) sunxi_simple_gates_setup(node, NULL, 0); } +CLK_OF_DECLARE(sun4i_a10_gates, "allwinner,sun4i-a10-gates-clk", + sunxi_simple_gates_init); CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk", sunxi_simple_gates_init); CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk", @@ -132,6 +134,8 @@ CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk", sunxi_simple_gates_init); CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk", sunxi_simple_gates_init); +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk", + sunxi_simple_gates_init); CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk", sunxi_simple_gates_init); CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk", -- 2.1.4
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| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-22 14:10 +0100 |
| Subject | [PATCH v5 2/4] dts: sun8i-h3: Add APB0 related clocks and resets |
| Message-ID | <r4Ypt-6jn-31@gated-at.bofh.it> |
| In reply to | #1339456 |
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.
After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3ba65c2..1348b69 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -276,6 +276,25 @@
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+ "allwinner,sun4i-a10-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
};
soc {
@@ -493,5 +512,11 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
};
};
--
2.1.4
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| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-22 14:10 +0100 |
| Subject | [PATCH v5 3/4] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi |
| Message-ID | <r4Ypt-6jn-41@gated-at.bofh.it> |
| In reply to | #1339456 |
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1348b69..c3b73d7 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -518,5 +518,17 @@
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-h3-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_reset 0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.1.4
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| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-22 14:10 +0100 |
| Subject | [PATCH v5 4/4] ARM: dts: sun8i: Add leds and switch on Orangepi Plus boards |
| Message-ID | <r4Ypt-6jn-49@gated-at.bofh.it> |
| In reply to | #1339456 |
OrangePi Plus board has two leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63 ++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index e67df59..5f159d0 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -45,6 +45,7 @@
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
@@ -58,6 +59,68 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_opc>;
+
+ status_led {
+ label = "status:red:user";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_r_opc>;
+
+ tx {
+ label = "pwr:green:user";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "sw4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw4@0 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&pio {
+ leds_opc: led_pins@0 {
+ allwinner,pins = "PA15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL03";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
&mmc0 {
--
2.1.4
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