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[PATCH 0/4] Updates to EDAC and AMD MCE driver

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  [PATCH 0/4] Updates to EDAC and AMD MCE driver Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-16 22:40 +0100
    [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-02-16 22:40 +0100

#1335867 — [PATCH 0/4] Updates to EDAC and AMD MCE driver

This patchset mainly provides necessary EDAC bits to decode errors
occuring on Scalable MCA enabled processors and also updates AMD MCE
driver to get correct MCx_MISC register address for upcoming processors.
Patches 1 ans 2 are meant for the upcoming processors.

Patches 3 and 4 are either fixing or adding comments to help in
understanding the code and do not introduce any functional changes.

Patch 1: Updates to EDAC driver to decode the new error signatures
Patch 2: Fix logic to get correct block address
Patch 3: Fix deferred error comment
Patch 4: Add comments to mce_amd.c to describe functionality

Tested the patches for regressions on Fam15h, Fam10h systems
and found none.

Aravind Gopalakrishnan (4):
  EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
  x86/mce/AMD: Fix logic to obtain block address
  x86/mce: Clarify comments regarding deferred error
  x86/mce/AMD: Add comments for easier understanding

 arch/x86/include/asm/mce.h           |  52 +++++-
 arch/x86/include/asm/msr-index.h     |   6 +
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 126 ++++++++++----
 drivers/edac/mce_amd.c               | 327 ++++++++++++++++++++++++++++++++++-
 4 files changed, 480 insertions(+), 31 deletions(-)

-- 
2.7.0

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#1335872 — [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding

In an attempt to help folks not very familiar with the code to
understand what the code is doing, adding a bit of helper
comments around some more important functions in the driver
to describe them.

No functional change is introduced.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 4bdc836..d2b6001 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -184,6 +184,11 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 };
 
 /*
+ * Set the error_count and interrupt_enable sysfs attributes here.
+ * This function gets called during the init phase and when someone
+ * makes changes to either of the sysfs attributes.
+ * During init phase, we also program Interrupt type as 'APIC' and
+ * verify if LVT offset obtained from MCx_MISC is valid.
  * Called via smp_call_function_single(), must be called with correct
  * cpu affinity.
  */
@@ -262,6 +267,11 @@ static int setup_APIC_deferred_error(int reserved, int new)
 	return reserved;
 }
 
+/*
+ * Obtain LVT offset from MSR_CU_DEF_ERR and call
+ * setup_APIC_deferred_error() to program relevant APIC register.
+ * Also, register a deferred error interrupt handler
+ */
 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 {
 	u32 low = 0, high = 0;
@@ -338,6 +348,14 @@ nextaddr_out:
 		return addr;
 }
 
+/*
+ * struct threshold_block descriptor tracks useful info regarding the
+ * banks' MISC register. Among other things, it tracks whether interrupt
+ * is possible for the given bank, the threshold limit and the sysfs object
+ * that outputs these info. Initializing the struct here, programming
+ * LVT offset for threshold interrupts and registering a interrupt handler
+ * if we haven't already done so
+ */
 static int
 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 			int offset, u32 misc_high)
@@ -673,6 +691,9 @@ static struct kobj_type threshold_ktype = {
 	.default_attrs		= default_attrs,
 };
 
+/*
+ * Initializing sysfs entries for each block within the MCA bank
+ */
 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
 				     unsigned int block, u32 address)
 {
-- 
2.7.0

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