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| Started by | Christophe Leroy <christophe.leroy@c-s.fr> |
|---|---|
| First post | 2016-02-09 11:30 +0100 |
| Last post | 2016-02-09 11:30 +0100 |
| Articles | 1 — 1 participant |
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[PATCH v7 22/23] powerpc32: small optimisation in flush_icache_range() Christophe Leroy <christophe.leroy@c-s.fr> - 2016-02-09 11:30 +0100
| From | Christophe Leroy <christophe.leroy@c-s.fr> |
|---|---|
| Date | 2016-02-09 11:30 +0100 |
| Subject | [PATCH v7 22/23] powerpc32: small optimisation in flush_icache_range() |
| Message-ID | <r0dIu-2Hb-17@gated-at.bofh.it> |
Inlining of _dcache_range() functions has shown that the compiler does the same thing a bit better with one insn less Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- v2: new v3: no change v4: no change v5: no change v6: no change v7: no change arch/powerpc/kernel/misc_32.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 09e1e5d..3ec5a22 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -348,10 +348,9 @@ BEGIN_FTR_SECTION PURGE_PREFETCHED_INS blr /* for 601, do nothing */ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) - li r5,L1_CACHE_BYTES-1 - andc r3,r3,r5 + rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT subf r4,r3,r4 - add r4,r4,r5 + addi r4,r4,L1_CACHE_BYTES - 1 srwi. r4,r4,L1_CACHE_SHIFT beqlr mtctr r4 -- 2.1.0
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