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Groups > linux.kernel > #1331933 > unrolled thread
| Started by | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| First post | 2016-02-11 14:20 +0100 |
| Last post | 2016-02-11 14:30 +0100 |
| Articles | 4 — 3 participants |
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Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Linus Walleij <linus.walleij@linaro.org> - 2016-02-11 14:20 +0100
Re: [linux-sunxi] Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Krzysztof Adamski <k@japko.eu> - 2016-02-11 14:30 +0100
Re: [linux-sunxi] Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Linus Walleij <linus.walleij@linaro.org> - 2016-02-11 15:00 +0100
Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Chen-Yu Tsai <wens@csie.org> - 2016-02-11 14:30 +0100
| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-02-11 14:20 +0100 |
| Subject | Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set |
| Message-ID | <r0Zk5-QV-3@gated-at.bofh.it> |
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > sunxi_pmx_set accepts pin number and then calculates offset by > subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, > gets offset so we have to convert it to pin number so we won't get > negative value in sunxi_pmx_set. > > This was only used on A10 so far, where there is only one GPIO chip with > pin_base set to 0 so it didn't matter. However H3 also requires this > workaround but have two pinmux sections, triggering problem for PL port. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> Waiting for Maxime to review this. I guess this patch can be merged independently of the other patches? Yours, Linus Walleij
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| From | Krzysztof Adamski <k@japko.eu> |
|---|---|
| Date | 2016-02-11 14:30 +0100 |
| Subject | Re: [linux-sunxi] Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set |
| Message-ID | <r0ZtM-VJ-3@gated-at.bofh.it> |
| In reply to | #1331933 |
On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote: >On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > >> sunxi_pmx_set accepts pin number and then calculates offset by >> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >> gets offset so we have to convert it to pin number so we won't get >> negative value in sunxi_pmx_set. >> >> This was only used on A10 so far, where there is only one GPIO chip with >> pin_base set to 0 so it didn't matter. However H3 also requires this >> workaround but have two pinmux sections, triggering problem for PL port. >> >> Signed-off-by: Krzysztof Adamski <k@japko.eu> > >Waiting for Maxime to review this. I guess this patch can be merged >independently of the other patches? Yes it can but it won't have any effect, as stated in the commit message, since other SoCs either don't use this flag or have only one port so theri pin_base=0. Best regards, Krzysztof Adamski
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-02-11 15:00 +0100 |
| Subject | Re: [linux-sunxi] Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set |
| Message-ID | <r0ZWO-17m-13@gated-at.bofh.it> |
| In reply to | #1331935 |
On Thu, Feb 11, 2016 at 2:20 PM, Krzysztof Adamski <k@japko.eu> wrote: > On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote: >> >> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: >> >>> sunxi_pmx_set accepts pin number and then calculates offset by >>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >>> gets offset so we have to convert it to pin number so we won't get >>> negative value in sunxi_pmx_set. >>> >>> This was only used on A10 so far, where there is only one GPIO chip with >>> pin_base set to 0 so it didn't matter. However H3 also requires this >>> workaround but have two pinmux sections, triggering problem for PL port. >>> >>> Signed-off-by: Krzysztof Adamski <k@japko.eu> >> >> >> Waiting for Maxime to review this. I guess this patch can be merged >> independently of the other patches? > > Yes it can but it won't have any effect, as stated in the commit message, > since other SoCs either don't use this flag or have only one port so theri > pin_base=0. Who cares as long as it will be used eventually. Merged v4 as stated earlier. Yours, Linus Walleij
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-02-11 14:30 +0100 |
| Message-ID | <r0ZtM-VJ-9@gated-at.bofh.it> |
| In reply to | #1331933 |
Hi, On Thu, Feb 11, 2016 at 9:17 PM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote: > >> sunxi_pmx_set accepts pin number and then calculates offset by >> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, >> gets offset so we have to convert it to pin number so we won't get >> negative value in sunxi_pmx_set. >> >> This was only used on A10 so far, where there is only one GPIO chip with >> pin_base set to 0 so it didn't matter. However H3 also requires this >> workaround but have two pinmux sections, triggering problem for PL port. >> >> Signed-off-by: Krzysztof Adamski <k@japko.eu> > > Waiting for Maxime to review this. I guess this patch can be merged > independently of the other patches? FYI there's a v4 of this patch that both Maxime and I acked. ChenYu
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