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| Started by | Shengjiu Wang <shengjiu.wang@freescale.com> |
|---|---|
| First post | 2015-11-24 08:10 +0100 |
| Last post | 2015-11-25 00:30 +0100 |
| Articles | 5 — 3 participants |
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[PATCH V3 0/3] add spba clock for fsl audio IP Shengjiu Wang <shengjiu.wang@freescale.com> - 2015-11-24 08:10 +0100
Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device Nicolin Chen <nicoleotsuka@gmail.com> - 2015-11-24 09:40 +0100
Re: [PATCH V3 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device Rob Herring <robh@kernel.org> - 2015-11-25 00:30 +0100
Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device Rob Herring <robh@kernel.org> - 2015-11-25 00:30 +0100
Re: [PATCH V3 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device Rob Herring <robh@kernel.org> - 2015-11-25 00:30 +0100
| From | Shengjiu Wang <shengjiu.wang@freescale.com> |
|---|---|
| Date | 2015-11-24 08:10 +0100 |
| Subject | [PATCH V3 0/3] add spba clock for fsl audio IP |
| Message-ID | <qyfTH-4UT-3@gated-at.bofh.it> |
add spba clock for fsl audio IP Changes in V3 - update the comments for clock description. Shengjiu Wang (3): ASoC: fsl_esai: spba clock is needed by esai device ASoC: fsl_spdif: spba clk is needed by spdif device ASoC: fsl_asrc: spba clock is needed by asrc device Documentation/devicetree/bindings/sound/fsl,asrc.txt | 5 +++++ Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +++++ Documentation/devicetree/bindings/sound/fsl,spdif.txt | 5 +++++ sound/soc/fsl/fsl_asrc.c | 10 ++++++++++ sound/soc/fsl/fsl_asrc.h | 2 ++ sound/soc/fsl/fsl_esai.c | 13 +++++++++++++ sound/soc/fsl/fsl_spdif.c | 15 +++++++++++++++ 7 files changed, 55 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Nicolin Chen <nicoleotsuka@gmail.com> |
|---|---|
| Date | 2015-11-24 09:40 +0100 |
| Subject | Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device |
| Message-ID | <qyhiO-5GD-15@gated-at.bofh.it> |
| In reply to | #1276093 |
On Tue, Nov 24, 2015 at 03:03:28PM +0800, Shengjiu Wang wrote:
> @@ -469,6 +471,9 @@ static int fsl_esai_startup(struct snd_pcm_substream *substream,
> ret = clk_prepare_enable(esai_priv->coreclk);
> if (ret)
> return ret;
> + ret = clk_prepare_enable(esai_priv->spbaclk);
> + if (ret)
> + goto err_spbaclk;
> if (!IS_ERR(esai_priv->extalclk)) {
> ret = clk_prepare_enable(esai_priv->extalclk);
> if (ret)
Just like for extalclk there is a IS_ERR check out there, there
should be one for spbaclk as well. Otherwise....
root@imx6qdlsolo:~# aplay /unit_tests/audio8k16S.wav
[ 29.956250] Unable to handle kernel paging request at virtual address fffffffe
[ 29.963491] pgd = edd98000
[ 29.966278] [fffffffe] *pgd=afffd861, *pte=00000000, *ppte=00000000
[ 29.972615] Internal error: Oops: 37 [#1] SMP ARM
[ 29.977327] Modules linked in:
[ 29.980410] CPU: 0 PID: 755 Comm: aplay Not tainted 4.4.0-rc1-12414-gcc8db17 #250
[ 29.987899] Hardware name: Freescale i.MX6 SoloX (Device Tree)
[ 29.993738] task: edece780 ti: ed26a000 task.ti: ed26a000
[ 29.999156] PC is at clk_prepare+0x18/0x38
[ 30.003268] LR is at mark_held_locks+0x70/0x98
[ 30.007720] pc : [<c0568714>] lr : [<c006f42c>] psr: 600f0013
[ 30.007720] sp : ed26bc60 ip : 00000003 fp : ed26bc74
[ 30.019204] r10: eebe4d9c r9 : eeb2e00c r8 : eeb2e00c
[ 30.024435] r7 : fffffffe r6 : eeb2c500 r5 : eeb2d0c0 r4 : fffffffe
[ 30.030966] r3 : edece780 r2 : 00000001 r1 : 00000001 r0 : 00000001
[ 30.037502] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 30.044643] Control: 10c5387d Table: add9804a DAC: 00000051
[ 30.050395] Process aplay (pid: 755, stack limit = 0xed26a210)
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-11-25 00:30 +0100 |
| Subject | Re: [PATCH V3 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device |
| Message-ID | <qyvc5-6mi-5@gated-at.bofh.it> |
| In reply to | #1276093 |
On Tue, Nov 24, 2015 at 03:03:29PM +0800, Shengjiu Wang wrote:
> SPDIF need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to SPDIF registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.txt | 5 +++++
For the binding:
Acked-by: Rob Herring <robh@kernel.org>
> sound/soc/fsl/fsl_spdif.c | 15 +++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> index b5ee32e..4ca39dd 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -27,6 +27,11 @@ Required properties:
> Transceiver Clock Diagram" of SoC reference manual.
> It can also be referred to TxClk_Source bit of
> register SPDIF_STC.
> + "spba" The spba clock is required when SPDIF is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
> - big-endian : If this property is absent, the native endian mode
> will be in use as default, or the big endian mode
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> index 28a8823..64e2a1f 100644
> --- a/sound/soc/fsl/fsl_spdif.c
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -88,6 +88,7 @@ struct spdif_mixer_control {
> * @rxclk: rx clock sources for capture
> * @coreclk: core clock for register access via DMA
> * @sysclk: system clock for rx clock rate measurement
> + * @spbaclk: SPBA clock (optional, depending on SoC design)
> * @dma_params_tx: DMA parameters for transmit channel
> * @dma_params_rx: DMA parameters for receive channel
> */
> @@ -106,6 +107,7 @@ struct fsl_spdif_priv {
> struct clk *rxclk;
> struct clk *coreclk;
> struct clk *sysclk;
> + struct clk *spbaclk;
> struct snd_dmaengine_dai_dma_data dma_params_tx;
> struct snd_dmaengine_dai_dma_data dma_params_rx;
> /* regcache for SRPC */
> @@ -474,6 +476,12 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
> return ret;
> }
>
> + ret = clk_prepare_enable(spdif_priv->spbaclk);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to enable spba clock\n");
> + goto err_spbaclk;
> + }
> +
> ret = spdif_softreset(spdif_priv);
> if (ret) {
> dev_err(&pdev->dev, "failed to soft reset\n");
> @@ -515,6 +523,8 @@ disable_txclk:
> for (i--; i >= 0; i--)
> clk_disable_unprepare(spdif_priv->txclk[i]);
> err:
> + clk_disable_unprepare(spdif_priv->spbaclk);
> +err_spbaclk:
> clk_disable_unprepare(spdif_priv->coreclk);
>
> return ret;
> @@ -548,6 +558,7 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
> spdif_intr_status_clear(spdif_priv);
> regmap_update_bits(regmap, REG_SPDIF_SCR,
> SCR_LOW_POWER, SCR_LOW_POWER);
> + clk_disable_unprepare(spdif_priv->spbaclk);
> clk_disable_unprepare(spdif_priv->coreclk);
> }
> }
> @@ -1261,6 +1272,10 @@ static int fsl_spdif_probe(struct platform_device *pdev)
> return PTR_ERR(spdif_priv->coreclk);
> }
>
> + spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(spdif_priv->spbaclk))
> + dev_warn(&pdev->dev, "no spba clock in devicetree\n");
> +
> /* Select clock source for rx/tx clock */
> spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
> if (IS_ERR(spdif_priv->rxclk)) {
> --
> 1.9.1
>
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-11-25 00:30 +0100 |
| Subject | Re: [PATCH V3 1/3] ASoC: fsl_esai: spba clock is needed by esai device |
| Message-ID | <qyvc6-6mi-23@gated-at.bofh.it> |
| In reply to | #1276093 |
On Tue, Nov 24, 2015 at 03:03:28PM +0800, Shengjiu Wang wrote:
> ESAI need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to ESAI registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +++++
Acked-by: Rob Herring <robh@kernel.org>
> sound/soc/fsl/fsl_esai.c | 13 +++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> index d3b6b5f..cd3ee5d 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> @@ -27,6 +27,11 @@ Required properties:
> derive HCK, SCK and FS.
> "fsys" The system clock derived from ahb clock used to
> derive HCK, SCK and FS.
> + "spba" The spba clock is required when ESAI is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
> - fsl,fifo-depth : The number of elements in the transmit and receive
> FIFOs. This number is the maximum allowed value for
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 504e731..4d7589c 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -35,6 +35,7 @@
> * @coreclk: clock source to access register
> * @extalclk: esai clock source to derive HCK, SCK and FS
> * @fsysclk: system clock source to derive HCK, SCK and FS
> + * @spbaclk: SPBA clock (optional, depending on SoC design)
> * @fifo_depth: depth of tx/rx FIFO
> * @slot_width: width of each DAI slot
> * @slots: number of slots
> @@ -54,6 +55,7 @@ struct fsl_esai {
> struct clk *coreclk;
> struct clk *extalclk;
> struct clk *fsysclk;
> + struct clk *spbaclk;
> u32 fifo_depth;
> u32 slot_width;
> u32 slots;
> @@ -469,6 +471,9 @@ static int fsl_esai_startup(struct snd_pcm_substream *substream,
> ret = clk_prepare_enable(esai_priv->coreclk);
> if (ret)
> return ret;
> + ret = clk_prepare_enable(esai_priv->spbaclk);
> + if (ret)
> + goto err_spbaclk;
> if (!IS_ERR(esai_priv->extalclk)) {
> ret = clk_prepare_enable(esai_priv->extalclk);
> if (ret)
> @@ -499,6 +504,8 @@ err_fsysclk:
> if (!IS_ERR(esai_priv->extalclk))
> clk_disable_unprepare(esai_priv->extalclk);
> err_extalck:
> + clk_disable_unprepare(esai_priv->spbaclk);
> +err_spbaclk:
> clk_disable_unprepare(esai_priv->coreclk);
>
> return ret;
> @@ -564,6 +571,7 @@ static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
> clk_disable_unprepare(esai_priv->fsysclk);
> if (!IS_ERR(esai_priv->extalclk))
> clk_disable_unprepare(esai_priv->extalclk);
> + clk_disable_unprepare(esai_priv->spbaclk);
> clk_disable_unprepare(esai_priv->coreclk);
> }
>
> @@ -819,6 +827,11 @@ static int fsl_esai_probe(struct platform_device *pdev)
> dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
> PTR_ERR(esai_priv->fsysclk));
>
> + esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(esai_priv->spbaclk))
> + dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
> + PTR_ERR(esai_priv->spbaclk));
> +
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
> dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
> --
> 1.9.1
>
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-11-25 00:30 +0100 |
| Subject | Re: [PATCH V3 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device |
| Message-ID | <qyvc6-6mi-31@gated-at.bofh.it> |
| In reply to | #1276093 |
On Tue, Nov 24, 2015 at 03:03:30PM +0800, Shengjiu Wang wrote:
> ASRC need to enable the spba clock, when sdma is using share peripheral
> script. In this case, there is two spba master port is used, if don't
> enable the clock, the spba bus will have arbitration issue, which may
> cause read/write wrong data from/to ASRC registers
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,asrc.txt | 5 +++++
For the binding:
Acked-by: Rob Herring <robh@kernel.org>
> sound/soc/fsl/fsl_asrc.c | 10 ++++++++++
> sound/soc/fsl/fsl_asrc.h | 2 ++
> 3 files changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> index b93362a..3e26a94 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
> @@ -25,6 +25,11 @@ Required properties:
> "mem" Peripheral access clock to access registers.
> "ipg" Peripheral clock to driver module.
> "asrck_<0-f>" Clock sources for input and output clock.
> + "spba" The spba clock is required when ASRC is placed as a
> + bus slave of the Shared Peripheral Bus and when two
> + or more bus masters (CPU, DMA or DSP) try to access
> + it. This property is optional depending on the SoC
> + design.
>
> - big-endian : If this property is absent, the little endian mode
> will be in use as default. Otherwise, the big endian
> diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
> index 9f087d4..800828e 100644
> --- a/sound/soc/fsl/fsl_asrc.c
> +++ b/sound/soc/fsl/fsl_asrc.c
> @@ -859,6 +859,10 @@ static int fsl_asrc_probe(struct platform_device *pdev)
> return PTR_ERR(asrc_priv->ipg_clk);
> }
>
> + asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
> + if (IS_ERR(asrc_priv->spba_clk))
> + dev_warn(&pdev->dev, "failed to get spba clock\n");
> +
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
> sprintf(tmp, "asrck_%x", i);
> asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
> @@ -939,6 +943,9 @@ static int fsl_asrc_runtime_resume(struct device *dev)
> ret = clk_prepare_enable(asrc_priv->ipg_clk);
> if (ret)
> goto disable_mem_clk;
> + ret = clk_prepare_enable(asrc_priv->spba_clk);
> + if (ret)
> + goto disable_ipg_clk;
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
> ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
> if (ret)
> @@ -950,6 +957,8 @@ static int fsl_asrc_runtime_resume(struct device *dev)
> disable_asrck_clk:
> for (i--; i >= 0; i--)
> clk_disable_unprepare(asrc_priv->asrck_clk[i]);
> + clk_disable_unprepare(asrc_priv->spba_clk);
> +disable_ipg_clk:
> clk_disable_unprepare(asrc_priv->ipg_clk);
> disable_mem_clk:
> clk_disable_unprepare(asrc_priv->mem_clk);
> @@ -963,6 +972,7 @@ static int fsl_asrc_runtime_suspend(struct device *dev)
>
> for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
> clk_disable_unprepare(asrc_priv->asrck_clk[i]);
> + clk_disable_unprepare(asrc_priv->spba_clk);
> clk_disable_unprepare(asrc_priv->ipg_clk);
> clk_disable_unprepare(asrc_priv->mem_clk);
>
> diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h
> index 4aed63c..68802cd 100644
> --- a/sound/soc/fsl/fsl_asrc.h
> +++ b/sound/soc/fsl/fsl_asrc.h
> @@ -426,6 +426,7 @@ struct fsl_asrc_pair {
> * @paddr: physical address to the base address of registers
> * @mem_clk: clock source to access register
> * @ipg_clk: clock source to drive peripheral
> + * @spba_clk: SPBA clock (optional, depending on SoC design)
> * @asrck_clk: clock sources to driver ASRC internal logic
> * @lock: spin lock for resource protection
> * @pair: pair pointers
> @@ -442,6 +443,7 @@ struct fsl_asrc {
> unsigned long paddr;
> struct clk *mem_clk;
> struct clk *ipg_clk;
> + struct clk *spba_clk;
> struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
> spinlock_t lock;
>
> --
> 1.9.1
>
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