Groups > linux.kernel > #1273368 > unrolled thread

[PATCH 00/25] serial: sh-sci: Add external clock and BRG Support

Started by	Geert Uytterhoeven <geert+renesas@glider.be>
First post	2015-11-19 19:50 +0100
Last post	2015-11-24 03:50 +0100
Articles	20 on this page of 54 — 4 participants

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  [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 22/25] ARM: shmobile: koelsch dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 16/25] serial: sh-sci: Correct SCIF type on RZ/A1H Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 20/25] serial: sh-sci: Add support for optional BRG on (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
        Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and  baud rate generators Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:00 +0100
          Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 15:50 +0100
            Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and  baud rate generators Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:20 +0100
              Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:40 +0100
    [PATCH 05/25] serial: sh-sci: Drop unused frame_len parameter for sci_baud_calc_hscif() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
        Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:20 +0100
    [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:30 +0100
        Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for  BRG support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:50 +0100
          Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:20 +0100
            Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for  BRG support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:00 +0100
    [PATCH 04/25] serial: sh-sci: Grammar s/Get ... for/Get ... from/ Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:00 +0100
        Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 08:50 +0100
          Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:00 +0100
            Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:40 +0100
            Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:40 +0100
    [PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 14/25] serial: sh-sci: Add BRG register definitions Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:50 +0100
    [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get() Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:40 +0100
    [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
      Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:20 +0100
        Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:30 +0100
          Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for  external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:50 +0100
            Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:20 +0100
              Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for  external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:10 +0100
        Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for  external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:40 +0100
    [PATCH 03/25] serial: sh-sci: Drop useless check for zero sampling_rate Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 24/25] arm64: renesas: salvator-x dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 19/25] serial: sh-sci: Add support for optional external (H)SCK input Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
    [PATCH 11/25] serial: sh-sci: Avoid calculating the receive margin for HSCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
    [PATCH 12/25] serial: sh-sci: Merge sci_scbrr_calc() and sci_baud_calc_hscif() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
    [PATCH 10/25] serial: sh-sci: Improve bit rate error calculation for HSCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
    Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
      Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:30 +0100
        Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 10:00 +0100
          Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 10:10 +0100
            Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:00 +0100
              Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:40 +0100
    Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 10:10 +0100
    Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Simon Horman <horms@verge.net.au> - 2015-11-24 03:50 +0100

Page 2 of 3 — ← Prev page 1 [2] 3 Next page →

#1273380 — [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwCrp-4G9-35@gated-at.bofh.it>
In reply to	#1273368

The "renesas,scif" compatible value is currently used for the SCIF
variant in all Renesas SoCs of the R-Car family.  However, the variant
used in the R-Car family is not the common "SH-4(A)" variant, but a
derivative with added "Baud Rate Generator for External Clock" (BRG),
which is also present in sh7734.

Use the (already documented) SoC-specific SCIF compatible values for all
supported R-Car Gen1, Gen2, and Gen3 SoCs to differentiate.  The
"renesas,scif" compatible value can still be used as a common
denominator for SCIF variants with the "SH-4(A)" register layout (i.e.
ignoring the "Serial Extension Mode Register" (SCEMR) and the new
BRG-specific registers).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/sh-sci.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index b0127f38af744fcf..726c96d5a511c222 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2605,6 +2605,30 @@ static const struct of_device_id of_sci_match[] = {
 	{
 		.compatible = "renesas,scif-r7s72100",
 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7778",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7779",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7790",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7791",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7792",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7793",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7794",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
+	}, {
+		.compatible = "renesas,scif-r8a7795",
+		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
 	},
 	/* Generic types */
 	{
-- 
1.9.1

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#1273497 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 22:00 +0100
Subject	Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwEtb-5WV-7@gated-at.bofh.it>
In reply to	#1273380

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:56 Geert Uytterhoeven wrote:
> The "renesas,scif" compatible value is currently used for the SCIF
> variant in all Renesas SoCs of the R-Car family.  However, the variant
> used in the R-Car family is not the common "SH-4(A)" variant, but a
> derivative with added "Baud Rate Generator for External Clock" (BRG),
> which is also present in sh7734.

Time to introduce a "renesas,scif-rcar" compatible string ? ;-)

As the only DT-enabled platform to have a different SCIF type is r7s72100 we 
could also consider just switching the regtype to SCIx_SH4_SCIF_BRG_REGTYPE 
for the generic "renesas,scif" entry as it's listed after the "renesas,scif-
r7s72100" entry. That might cause an issue if we want to enable DT on arch/sh 
though, but even if that happens due to the J-Core processors I'd be surprised 
to see the old Renesas SH platforms being moved to DT.

> Use the (already documented) SoC-specific SCIF compatible values for all
> supported R-Car Gen1, Gen2, and Gen3 SoCs to differentiate.  The
> "renesas,scif" compatible value can still be used as a common
> denominator for SCIF variants with the "SH-4(A)" register layout (i.e.
> ignoring the "Serial Extension Mode Register" (SCEMR) and the new
> BRG-specific registers).
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/sh-sci.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index b0127f38af744fcf..726c96d5a511c222 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2605,6 +2605,30 @@ static const struct of_device_id of_sci_match[] = {
>  	{
>  		.compatible = "renesas,scif-r7s72100",
>  		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7778",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7779",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7790",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7791",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7792",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7793",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7794",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
> +	}, {
> +		.compatible = "renesas,scif-r8a7795",
> +		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
>  	},
>  	/* Generic types */
>  	{

-- 
Regards,

Laurent Pinchart

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#1273766 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Geert Uytterhoeven <geert@linux-m68k.org>
Date	2015-11-20 08:50 +0100
Subject	Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwOCd-4dZ-15@gated-at.bofh.it>
In reply to	#1273497

Hi Laurent,

On Thu, Nov 19, 2015 at 9:55 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:56 Geert Uytterhoeven wrote:
>> The "renesas,scif" compatible value is currently used for the SCIF
>> variant in all Renesas SoCs of the R-Car family.  However, the variant
>> used in the R-Car family is not the common "SH-4(A)" variant, but a
>> derivative with added "Baud Rate Generator for External Clock" (BRG),
>> which is also present in sh7734.
>
> Time to introduce a "renesas,scif-rcar" compatible string ? ;-)
>
> As the only DT-enabled platform to have a different SCIF type is r7s72100 we
> could also consider just switching the regtype to SCIx_SH4_SCIF_BRG_REGTYPE
> for the generic "renesas,scif" entry as it's listed after the "renesas,scif-
> r7s72100" entry. That might cause an issue if we want to enable DT on arch/sh
> though, but even if that happens due to the J-Core processors I'd be surprised
> to see the old Renesas SH platforms being moved to DT.

I thought about that, but you never know in which out-of-tree BSP it ended up
being used, too. So better safe than sorry.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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#1274135 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-20 16:00 +0100
Subject	Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwVkm-6h-29@gated-at.bofh.it>
In reply to	#1273766

Hi Geert,

On Friday 20 November 2015 08:46:56 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 9:55 PM, Laurent Pinchart wrote:
> > On Thursday 19 November 2015 19:38:56 Geert Uytterhoeven wrote:
> >> The "renesas,scif" compatible value is currently used for the SCIF
> >> variant in all Renesas SoCs of the R-Car family.  However, the variant
> >> used in the R-Car family is not the common "SH-4(A)" variant, but a
> >> derivative with added "Baud Rate Generator for External Clock" (BRG),
> >> which is also present in sh7734.
> > 
> > Time to introduce a "renesas,scif-rcar" compatible string ? ;-)
> > 
> > As the only DT-enabled platform to have a different SCIF type is r7s72100
> > we could also consider just switching the regtype to
> > SCIx_SH4_SCIF_BRG_REGTYPE for the generic "renesas,scif" entry as it's
> > listed after the "renesas,scif- r7s72100" entry. That might cause an
> > issue if we want to enable DT on arch/sh though, but even if that happens
> > due to the J-Core processors I'd be surprised to see the old Renesas SH
> > platforms being moved to DT.
> 
> I thought about that, but you never know in which out-of-tree BSP it ended
> up being used, too. So better safe than sorry.

Out-of-tree should be banned :-)

More seriously, I suppose you wouldn't be thrilled by the idea of a 
"renesas,scif-rcar-gen2" ?

-- 
Regards,

Laurent Pinchart

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#1274182 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-20 16:40 +0100
Subject	Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwVX3-Bk-5@gated-at.bofh.it>
In reply to	#1274135

Hi Geert,

On Friday 20 November 2015 16:30:22 Geert Uytterhoeven wrote:
> On Fri, Nov 20, 2015 at 3:52 PM, Laurent Pinchart wrote:
> > On Friday 20 November 2015 08:46:56 Geert Uytterhoeven wrote:
> >> On Thu, Nov 19, 2015 at 9:55 PM, Laurent Pinchart wrote:
> >>> On Thursday 19 November 2015 19:38:56 Geert Uytterhoeven wrote:
> >>>> The "renesas,scif" compatible value is currently used for the SCIF
> >>>> variant in all Renesas SoCs of the R-Car family.  However, the variant
> >>>> used in the R-Car family is not the common "SH-4(A)" variant, but a
> >>>> derivative with added "Baud Rate Generator for External Clock" (BRG),
> >>>> which is also present in sh7734.
> >>> 
> >>> Time to introduce a "renesas,scif-rcar" compatible string ? ;-)
> >>> 
> >>> As the only DT-enabled platform to have a different SCIF type is
> >>> r7s72100 we could also consider just switching the regtype to
> >>> SCIx_SH4_SCIF_BRG_REGTYPE for the generic "renesas,scif" entry as it's
> >>> listed after the "renesas,scif- r7s72100" entry. That might cause an
> >>> issue if we want to enable DT on arch/sh though, but even if that
> >>> happens due to the J-Core processors I'd be surprised to see the old
> >>> Renesas SH platforms being moved to DT.
> >> 
> >> I thought about that, but you never know in which out-of-tree BSP it
> >> ended up being used, too. So better safe than sorry.
> > 
> > Out-of-tree should be banned :-)
> > 
> > More seriously, I suppose you wouldn't be thrilled by the idea of a
> > "renesas,scif-rcar-gen2" ?
> 
> Nope. Note that it's also used in R-Car Gen 1 and Gen 3, and sh7734.

Yes, but it would at least cover the whole Gen2 family that behaves the same 
way. And wouldn't preclude adding "renesas,scif-rcar-gen1". That's two compat 
strings only.

-- 
Regards,

Laurent Pinchart

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#1274183 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

From	Geert Uytterhoeven <geert@linux-m68k.org>
Date	2015-11-20 16:40 +0100
Subject	Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG
Message-ID	<qwVX3-Bk-7@gated-at.bofh.it>
In reply to	#1274135

Hi Laurent,

On Fri, Nov 20, 2015 at 3:52 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Friday 20 November 2015 08:46:56 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 9:55 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 19:38:56 Geert Uytterhoeven wrote:
>> >> The "renesas,scif" compatible value is currently used for the SCIF
>> >> variant in all Renesas SoCs of the R-Car family.  However, the variant
>> >> used in the R-Car family is not the common "SH-4(A)" variant, but a
>> >> derivative with added "Baud Rate Generator for External Clock" (BRG),
>> >> which is also present in sh7734.
>> >
>> > Time to introduce a "renesas,scif-rcar" compatible string ? ;-)
>> >
>> > As the only DT-enabled platform to have a different SCIF type is r7s72100
>> > we could also consider just switching the regtype to
>> > SCIx_SH4_SCIF_BRG_REGTYPE for the generic "renesas,scif" entry as it's
>> > listed after the "renesas,scif- r7s72100" entry. That might cause an
>> > issue if we want to enable DT on arch/sh though, but even if that happens
>> > due to the J-Core processors I'd be surprised to see the old Renesas SH
>> > platforms being moved to DT.
>>
>> I thought about that, but you never know in which out-of-tree BSP it ended
>> up being used, too. So better safe than sorry.
>
> Out-of-tree should be banned :-)
>
> More seriously, I suppose you wouldn't be thrilled by the idea of a
> "renesas,scif-rcar-gen2" ?

Nope. Note that it's also used in R-Car Gen 1 and Gen 3, and sh7734.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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#1273382 — [PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write()

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write()
Message-ID	<qwCrp-4G9-45@gated-at.bofh.it>
In reply to	#1273368

Blindly writing the default configuration value into the SCSCR register
may change the clock selection bits, breaking the serial console if the
current driver settings differ from the default settings.

Keep the current clock selection bits to prevent this from happening
on e.g. r8a7791/koelsch when support for the BRG will be added.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/sh-sci.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 7c7dfbce54ed9c19..cba51da604253db6 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2415,7 +2415,7 @@ static void serial_console_write(struct console *co, const char *s,
 {
 	struct sci_port *sci_port = &sci_ports[co->index];
 	struct uart_port *port = &sci_port->port;
-	unsigned short bits, ctrl;
+	unsigned short bits, ctrl, ctrl_temp;
 	unsigned long flags;
 	int locked = 1;
 
@@ -2427,9 +2427,11 @@ static void serial_console_write(struct console *co, const char *s,
 	else
 		spin_lock(&port->lock);
 
-	/* first save the SCSCR then disable the interrupts */
+	/* first save SCSCR then disable interrupts, keep clock source */
 	ctrl = serial_port_in(port, SCSCR);
-	serial_port_out(port, SCSCR, sci_port->cfg->scscr);
+	ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
+		    (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
+	serial_port_out(port, SCSCR, ctrl_temp);
 
 	uart_console_write(port, s, count, serial_console_putchar);
 
-- 
1.9.1

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#1273383 — [PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate
Message-ID	<qwCrp-4G9-41@gated-at.bofh.it>
In reply to	#1273368

The maximum baud rate depends on the sampling rate.
HSCIF has a variable sampling rate and sets s->sampling_rate to zero,
hence use the minimum sampling rate of 8.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/sh-sci.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index dccea5df5355076a..d82735dd62ae38d8 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1961,7 +1961,10 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 	 * that the previous boot loader has enabled required clocks and
 	 * setup the baud rate generator hardware for us already.
 	 */
-	max_baud = port->uartclk ? port->uartclk / 16 : 115200;
+	if (port->uartclk)
+		max_baud = port->uartclk / max(s->sampling_rate, 8U);
+	else
+		max_baud = 115200;
 
 	baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
 	if (likely(baud && port->uartclk))
-- 
1.9.1

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#1273384 — [PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF
Message-ID	<qwCrp-4G9-43@gated-at.bofh.it>
In reply to	#1273368

Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depends on
the actual board.

Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.

This increases the range and accuracy of supported baud rates on
(H)SCIF.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r8a7791.dtsi | 54 ++++++++++++++++++++++++++++--------------
 1 file changed, 36 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 684120a0a479a8d0..20f0cacd3a79095b 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -670,8 +670,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;
 		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -682,8 +683,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6e68000 0 64>;
 		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -694,8 +696,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6e58000 0 64>;
 		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -706,8 +709,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6ea8000 0 64>;
 		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -718,8 +722,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6ee0000 0 64>;
 		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -730,8 +735,9 @@
 		compatible = "renesas,scif-r8a7791", "renesas,scif";
 		reg = <0 0xe6ee8000 0 64>;
 		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -742,8 +748,9 @@
 		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 		reg = <0 0xe62c0000 0 96>;
 		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -754,8 +761,9 @@
 		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 		reg = <0 0xe62c8000 0 96>;
 		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -766,8 +774,9 @@
 		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 		reg = <0 0xe62d0000 0 96>;
 		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
-		clock-names = "fck";
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "int_clk", "scif_clk";
 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg_clocks>;
@@ -1014,6 +1023,15 @@
 			status = "disabled";
 		};
 
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+			status = "disabled";
+		};
+
 		/* External USB clock - can be overridden by the board */
 		usb_extal_clk: usb_extal_clk {
 			compatible = "fixed-clock";
-- 
1.9.1

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#1273385 — [PATCH 14/25] serial: sh-sci: Add BRG register definitions

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 14/25] serial: sh-sci: Add BRG register definitions
Message-ID	<qwCrp-4G9-47@gated-at.bofh.it>
In reply to	#1273368

Add register definitions for the Baud Rate Generator for External Clock
(BRG), as found in some SCIF and in HSCIF, including a new regtype for
the "SH-4(A)"-derived SCIF variant with BRG.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/sh-sci.c | 46 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/tty/serial/sh-sci.h |  5 +++++
 include/linux/serial_sci.h  |  1 +
 3 files changed, 52 insertions(+)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d82735dd62ae38d8..76738c9918885764 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -161,6 +161,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -183,6 +185,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -204,6 +208,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= { 0x30, 16 },
 		[SCPDR]		= { 0x34, 16 },
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -225,6 +231,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= { 0x30, 16 },
 		[SCPDR]		= { 0x34, 16 },
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -247,6 +255,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -268,6 +278,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -289,6 +301,32 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
+	},
+
+	/*
+	 * Common SCIF definitions for ports with a Baud Rate Generator for
+	 * External Clock (BRG).
+	 */
+	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
+		[SCSMR]		= { 0x00, 16 },
+		[SCBRR]		= { 0x04,  8 },
+		[SCSCR]		= { 0x08, 16 },
+		[SCxTDR]	= { 0x0c,  8 },
+		[SCxSR]		= { 0x10, 16 },
+		[SCxRDR]	= { 0x14,  8 },
+		[SCFCR]		= { 0x18, 16 },
+		[SCFDR]		= { 0x1c, 16 },
+		[SCTFDR]	= sci_reg_invalid,
+		[SCRFDR]	= sci_reg_invalid,
+		[SCSPTR]	= { 0x20, 16 },
+		[SCLSR]		= { 0x24, 16 },
+		[HSSRR]		= sci_reg_invalid,
+		[SCPCR]		= sci_reg_invalid,
+		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= { 0x30, 16 },
+		[SCCKS]		= { 0x34, 16 },
 	},
 
 	/*
@@ -310,6 +348,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= { 0x40, 16 },
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= { 0x30, 16 },
+		[SCCKS]		= { 0x34, 16 },
 	},
 
 	/*
@@ -332,6 +372,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -354,6 +396,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 
 	/*
@@ -376,6 +420,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
 		[HSSRR]		= sci_reg_invalid,
 		[SCPCR]		= sci_reg_invalid,
 		[SCPDR]		= sci_reg_invalid,
+		[SCDL]		= sci_reg_invalid,
+		[SCCKS]		= sci_reg_invalid,
 	},
 };
 
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index bf69bbdcc1f9aa39..54994f0bfafdbe12 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -27,6 +27,8 @@ enum {
 	HSSRR,				/* Sampling Rate Register */
 	SCPCR,				/* Serial Port Control Register */
 	SCPDR,				/* Serial Port Data Register */
+	SCDL,				/* BRG Frequency Division Register */
+	SCCKS,				/* BRG Clock Select Register */
 
 	SCIx_NR_REGS,
 };
@@ -109,6 +111,9 @@ enum {
 #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
 #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */
 
+/* BRG Clock Select Register (Some SCIF and HSCIF) */
+#define SCCKS_CKS	BIT(15)	/* Select SCK (1) or SC_CLK (0) */
+#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
 
 #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 #define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 7c536ac5be05d3aa..9f2bfd0557429ac3 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -32,6 +32,7 @@ enum {
 	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 	SCIx_SH3_SCIF_REGTYPE,
 	SCIx_SH4_SCIF_REGTYPE,
+	SCIx_SH4_SCIF_BRG_REGTYPE,
 	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 	SCIx_SH7705_SCIF_REGTYPE,
-- 
1.9.1

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#1273483 — Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 21:50 +0100
Subject	Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions
Message-ID	<qwEjv-5Tc-3@gated-at.bofh.it>
In reply to	#1273385

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:53 Geert Uytterhoeven wrote:
> Add register definitions for the Baud Rate Generator for External Clock
> (BRG), as found in some SCIF and in HSCIF, including a new regtype for
> the "SH-4(A)"-derived SCIF variant with BRG.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/sh-sci.c | 46 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/tty/serial/sh-sci.h |  5 +++++
>  include/linux/serial_sci.h  |  1 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index d82735dd62ae38d8..76738c9918885764 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -161,6 +161,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -183,6 +185,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -204,6 +208,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -225,6 +231,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -247,6 +255,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -268,6 +278,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -289,6 +301,32 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
> +	},
> +
> +	/*
> +	 * Common SCIF definitions for ports with a Baud Rate Generator for
> +	 * External Clock (BRG).
> +	 */
> +	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
> +		[SCSMR]		= { 0x00, 16 },
> +		[SCBRR]		= { 0x04,  8 },
> +		[SCSCR]		= { 0x08, 16 },
> +		[SCxTDR]	= { 0x0c,  8 },
> +		[SCxSR]		= { 0x10, 16 },
> +		[SCxRDR]	= { 0x14,  8 },
> +		[SCFCR]		= { 0x18, 16 },
> +		[SCFDR]		= { 0x1c, 16 },
> +		[SCTFDR]	= sci_reg_invalid,
> +		[SCRFDR]	= sci_reg_invalid,
> +		[SCSPTR]	= { 0x20, 16 },
> +		[SCLSR]		= { 0x24, 16 },
> +		[HSSRR]		= sci_reg_invalid,
> +		[SCPCR]		= sci_reg_invalid,
> +		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -310,6 +348,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= { 0x40, 16 },
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -332,6 +372,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -354,6 +396,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -376,6 +420,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
>  };
> 
> diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
> index bf69bbdcc1f9aa39..54994f0bfafdbe12 100644
> --- a/drivers/tty/serial/sh-sci.h
> +++ b/drivers/tty/serial/sh-sci.h
> @@ -27,6 +27,8 @@ enum {
>  	HSSRR,				/* Sampling Rate Register */
>  	SCPCR,				/* Serial Port Control Register */
>  	SCPDR,				/* Serial Port Data Register */
> +	SCDL,				/* BRG Frequency Division Register */
> +	SCCKS,				/* BRG Clock Select Register */
> 
>  	SCIx_NR_REGS,
>  };
> @@ -109,6 +111,9 @@ enum {
>  #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
>  #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */
> 
> +/* BRG Clock Select Register (Some SCIF and HSCIF) */
> +#define SCCKS_CKS	BIT(15)	/* Select SCK (1) or SC_CLK (0) */

This is slightly confusing. SC_CLK is defined as the external clock selectable 
between the bus clock and SCIF_CLK. The CKS bit selects the output of the baud 
rate generator for external clock as being the divided SC_CLK or the undivided 
(H)SCK. The comment, and I know it comes from the datasheet, seems to imply 
that the bit selects the input of the BRG-EC. Speaking of which it would be 
good to have a comment somewhere in the code to explain that we have two 
chained BRGs.

> +#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) 
*/
> 
>  #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   :
> SCIF_TEND) #define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? 
SCI_RDRF 
>  : SCIF_RDF) diff --git a/include/linux/serial_sci.h
> b/include/linux/serial_sci.h index 7c536ac5be05d3aa..9f2bfd0557429ac3
> 100644
> --- a/include/linux/serial_sci.h
> +++ b/include/linux/serial_sci.h
> @@ -32,6 +32,7 @@ enum {
>  	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH3_SCIF_REGTYPE,
>  	SCIx_SH4_SCIF_REGTYPE,
> +	SCIx_SH4_SCIF_BRG_REGTYPE,
>  	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
>  	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH7705_SCIF_REGTYPE,

-- 
Regards,

Laurent Pinchart

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#1273386 — [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()
Message-ID	<qwCrp-4G9-49@gated-at.bofh.it>
In reply to	#1273368

Transfer clock cleanup handling to the core device management code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/sh-sci.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index cba51da604253db6..9442961a198378c7 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2216,7 +2216,7 @@ static struct uart_ops sci_uart_ops = {
 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 {
 	/* Get the SCI functional clock. It's called "fck" on ARM. */
-	sci_port->fclk = clk_get(dev, "fck");
+	sci_port->fclk = devm_clk_get(dev, "fck");
 	if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
 		return -EPROBE_DEFER;
 	if (!IS_ERR(sci_port->fclk))
@@ -2226,7 +2226,7 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 	 * But it used to be called "sci_ick", and we need to maintain DT
 	 * backward compatibility.
 	 */
-	sci_port->fclk = clk_get(dev, "sci_ick");
+	sci_port->fclk = devm_clk_get(dev, "sci_ick");
 	if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
 		return -EPROBE_DEFER;
 	if (!IS_ERR(sci_port->fclk))
@@ -2236,7 +2236,7 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 	 * Not all SH platforms declare a clock lookup entry for SCI devices,
 	 * in which case we need to get the global "peripheral_clk" clock.
 	 */
-	sci_port->fclk = clk_get(dev, "peripheral_clk");
+	sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
 	if (!IS_ERR(sci_port->fclk))
 		return 0;
 
@@ -2395,8 +2395,6 @@ static int sci_init_single(struct platform_device *dev,
 
 static void sci_cleanup_single(struct sci_port *port)
 {
-	clk_put(port->fclk);
-
 	pm_runtime_disable(port->port.dev);
 }
 
-- 
1.9.1

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#1273475 — Re: [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 21:40 +0100
Subject	Re: [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()
Message-ID	<qwE9P-5PC-3@gated-at.bofh.it>
In reply to	#1273386

Hi Geert,

Thank for the patch.

On Thursday 19 November 2015 19:38:46 Geert Uytterhoeven wrote:
> Transfer clock cleanup handling to the core device management code.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/sh-sci.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index cba51da604253db6..9442961a198378c7 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2216,7 +2216,7 @@ static struct uart_ops sci_uart_ops = {
>  static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  {
>  	/* Get the SCI functional clock. It's called "fck" on ARM. */
> -	sci_port->fclk = clk_get(dev, "fck");
> +	sci_port->fclk = devm_clk_get(dev, "fck");

Have you tested what happens if you unbind the device from the driver while 
userspace has the serial port open ?

>  	if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>  		return -EPROBE_DEFER;
>  	if (!IS_ERR(sci_port->fclk))
> @@ -2226,7 +2226,7 @@ static int sci_init_clocks(struct sci_port *sci_port,
> struct device *dev) * But it used to be called "sci_ick", and we need to
> maintain DT * backward compatibility.
>  	 */
> -	sci_port->fclk = clk_get(dev, "sci_ick");
> +	sci_port->fclk = devm_clk_get(dev, "sci_ick");
>  	if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>  		return -EPROBE_DEFER;
>  	if (!IS_ERR(sci_port->fclk))
> @@ -2236,7 +2236,7 @@ static int sci_init_clocks(struct sci_port *sci_port,
> struct device *dev) * Not all SH platforms declare a clock lookup entry for
> SCI devices, * in which case we need to get the global "peripheral_clk"
> clock. */
> -	sci_port->fclk = clk_get(dev, "peripheral_clk");
> +	sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
>  	if (!IS_ERR(sci_port->fclk))
>  		return 0;
> 
> @@ -2395,8 +2395,6 @@ static int sci_init_single(struct platform_device
> *dev,
> 
>  static void sci_cleanup_single(struct sci_port *port)
>  {
> -	clk_put(port->fclk);
> -
>  	pm_runtime_disable(port->port.dev);
>  }

-- 
Regards,

Laurent Pinchart

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#1273387 — [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Geert Uytterhoeven <geert+renesas@glider.be>
Date	2015-11-19 19:50 +0100
Subject	[PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwCrp-4G9-51@gated-at.bofh.it>
In reply to	#1273368

Amend the DT bindings to include the optional external clock on
(H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
depending on board wiring.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: devicetree@vger.kernel.org
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 2c9e6b8477e92792..8efc9b6f35637fbb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -43,6 +43,9 @@ Required properties:
   - clocks: Must contain a phandle and clock-specifier pair for each entry
     in clock-names.
   - clock-names: Must contain "fck" for the SCIx UART functional clock.
+    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
+      - "hsck" for the optional external clock input (on HSCIF),
+      - "sck" for the optional external clock input (on other variants).
 
 Note: Each enabled SCIx UART should have an alias correctly numbered in the
 "aliases" node.
-- 
1.9.1

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#1273450 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 21:20 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwDQt-5IW-1@gated-at.bofh.it>
In reply to	#1273387

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> Amend the DT bindings to include the optional external clock on
> (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> depending on board wiring.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: devicetree@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> 2c9e6b8477e92792..8efc9b6f35637fbb 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -43,6 +43,9 @@ Required properties:
>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>      in clock-names.
>    - clock-names: Must contain "fck" for the SCIx UART functional clock.
> +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:

Could you list the SCIFA variants that support external clocks ?

> +      - "hsck" for the optional external clock input (on HSCIF),
> +      - "sck" for the optional external clock input (on other variants).
> 
>  Note: Each enabled SCIx UART should have an alias correctly numbered in the
> "aliases" node.

-- 
Regards,

Laurent Pinchart

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#1273470 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 21:30 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwE0a-5Mi-3@gated-at.bofh.it>
In reply to	#1273450

Hi Geert,

On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> > Amend the DT bindings to include the optional external clock on
> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> > depending on board wiring.
> > 
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Cc: devicetree@vger.kernel.org
> > ---
> > 
> >  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> > 2c9e6b8477e92792..8efc9b6f35637fbb 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > 
> > @@ -43,6 +43,9 @@ Required properties:
> >    - clocks: Must contain a phandle and clock-specifier pair for each
> >    entry
> >    
> >      in clock-names.
> >    
> >    - clock-names: Must contain "fck" for the SCIx UART functional clock.
> > 
> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
> Could you list the SCIFA variants that support external clocks ?
> 
> > +      - "hsck" for the optional external clock input (on HSCIF),
> > +      - "sck" for the optional external clock input (on other variants).

Additionally, those clocks are used as inputs to the baud rate generator for 
external clocks, as the ones listed in patch 02/25 in this series. I'd merge 
the two patches and clarify the wording.

> >  Note: Each enabled SCIx UART should have an alias correctly numbered in
> >  the "aliases" node.

-- 
Regards,

Laurent Pinchart

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#1273485 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Geert Uytterhoeven <geert@linux-m68k.org>
Date	2015-11-19 21:50 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwEjv-5Tc-11@gated-at.bofh.it>
In reply to	#1273470

On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
>> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> > Amend the DT bindings to include the optional external clock on
>> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
>> > depending on board wiring.

>> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >
>> > @@ -43,6 +43,9 @@ Required properties:
>> >    - clocks: Must contain a phandle and clock-specifier pair for each
>> >    entry
>> >
>> >      in clock-names.
>> >
>> >    - clock-names: Must contain "fck" for the SCIx UART functional clock.
>> >
>> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> Could you list the SCIFA variants that support external clocks ?
>>
>> > +      - "hsck" for the optional external clock input (on HSCIF),
>> > +      - "sck" for the optional external clock input (on other variants).
>
> Additionally, those clocks are used as inputs to the baud rate generator for
> external clocks, as the ones listed in patch 02/25 in this series. I'd merge
> the two patches and clarify the wording.

"SCK" predates the BRG, it even exists on SCI in H8/300.

That SCK is used as input to the BRG is just an artefact of how the BRG was
added to the SCIF. The BRG is just muxed with the existing SCK to form a clock
input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
And the BRG itself can choose between SCIF_CLK and INT_CLK.

Hence that's why I split it in two parts.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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#1273507 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date	2015-11-19 22:20 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwEMx-6ku-9@gated-at.bofh.it>
In reply to	#1273485

Hi Geert,

On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote:
> > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
> >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> >> > Amend the DT bindings to include the optional external clock on
> >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> >> > depending on board wiring.
> >> > 
> >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> > 
> >> > @@ -43,6 +43,9 @@ Required properties:
> >> >    - clocks: Must contain a phandle and clock-specifier pair for each
> >> >      entry in clock-names.
> >> >    - clock-names: Must contain "fck" for the SCIx UART functional
> >> >    clock.
> >> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
> >>
> >> Could you list the SCIFA variants that support external clocks ?
> >> 
> >> > +      - "hsck" for the optional external clock input (on HSCIF),
> >> > +      - "sck" for the optional external clock input (on other
> >> > variants).
> > 
> > Additionally, those clocks are used as inputs to the baud rate generator
> > for external clocks, as the ones listed in patch 02/25 in this series.
> > I'd merge the two patches and clarify the wording.
> 
> "SCK" predates the BRG, it even exists on SCI in H8/300.
> 
> That SCK is used as input to the BRG is just an artefact of how the BRG was
> added to the SCIF. The BRG is just muxed with the existing SCK to form a
> clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
> And the BRG itself can choose between SCIF_CLK and INT_CLK.
> 
> Hence that's why I split it in two parts.

It makes sense with the explanation.

I think some of the patches should be clarified to mention BRG-EC (or whatever 
you want to call it) instead of just BRG, as otherwise it's very easy to 
confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while 
the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the 
DT bindings and the code can be hard to understand.

-- 
Regards,

Laurent Pinchart

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#1273789 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Geert Uytterhoeven <geert@linux-m68k.org>
Date	2015-11-20 09:10 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwOVB-4AF-39@gated-at.bofh.it>
In reply to	#1273507

Hi Laurent,

On Thu, Nov 19, 2015 at 10:17 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
>> >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> >> > Amend the DT bindings to include the optional external clock on
>> >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
>> >> > depending on board wiring.
>> >> >
>> >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> >
>> >> > @@ -43,6 +43,9 @@ Required properties:
>> >> >    - clocks: Must contain a phandle and clock-specifier pair for each
>> >> >      entry in clock-names.
>> >> >    - clock-names: Must contain "fck" for the SCIx UART functional
>> >> >    clock.
>> >> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> >>
>> >> Could you list the SCIFA variants that support external clocks ?
>> >>
>> >> > +      - "hsck" for the optional external clock input (on HSCIF),
>> >> > +      - "sck" for the optional external clock input (on other
>> >> > variants).
>> >
>> > Additionally, those clocks are used as inputs to the baud rate generator
>> > for external clocks, as the ones listed in patch 02/25 in this series.
>> > I'd merge the two patches and clarify the wording.
>>
>> "SCK" predates the BRG, it even exists on SCI in H8/300.
>>
>> That SCK is used as input to the BRG is just an artefact of how the BRG was
>> added to the SCIF. The BRG is just muxed with the existing SCK to form a
>> clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
>> And the BRG itself can choose between SCIF_CLK and INT_CLK.
>>
>> Hence that's why I split it in two parts.
>
> It makes sense with the explanation.
>
> I think some of the patches should be clarified to mention BRG-EC (or whatever
> you want to call it) instead of just BRG, as otherwise it's very easy to
> confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while
> the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the
> DT bindings and the code can be hard to understand.

The (H)SCK clock is not an input to the internal BRG: it's used directly as the
sampling clock.

I'll add more clarification...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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#1273476 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

From	Geert Uytterhoeven <geert@linux-m68k.org>
Date	2015-11-19 21:40 +0100
Subject	Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input
Message-ID	<qwE9P-5PC-19@gated-at.bofh.it>
In reply to	#1273450

Hi Laurent,

On Thu, Nov 19, 2015 at 9:19 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
>> 2c9e6b8477e92792..8efc9b6f35637fbb 100644
>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> @@ -43,6 +43,9 @@ Required properties:
>>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>>      in clock-names.
>>    - clock-names: Must contain "fck" for the SCIx UART functional clock.
>> +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>
> Could you list the SCIFA variants that support external clocks ?

The list is in the commit description of "[PATCH 19/25] serial: sh-sci: Add
support for optional external (H)SCK input": sh7723, sh7724, and r8a7740.

Note that the list is probably incomplete, so I don't know if it's that useful
to have it in the binding docs. Especially as I haven't verified yet that it
actually works ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Page 2 of 3 — ← Prev page 1 [2] 3 Next page →

csiph-web

[PATCH 00/25] serial: sh-sci: Add external clock and BRG Support

Contents

#1273380 — [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1273497 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1273766 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1274135 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1274182 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1274183 — Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG

#1273382 — [PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write()

#1273383 — [PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate

#1273384 — [PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF

#1273385 — [PATCH 14/25] serial: sh-sci: Add BRG register definitions

#1273483 — Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions

#1273386 — [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()

#1273475 — Re: [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get()

#1273387 — [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273450 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273470 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273485 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273507 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273789 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

#1273476 — Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input