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[PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs

Started byMatthew McClintock <mmcclint@qca.qualcomm.com>
First post2015-11-20 00:20 +0100
Last post2015-11-20 00:30 +0100
Articles 3 — 1 participant

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  [PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs Matthew McClintock <mmcclint@qca.qualcomm.com> - 2015-11-20 00:20 +0100
    [PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board Matthew McClintock <mmcclint@qca.qualcomm.com> - 2015-11-20 00:30 +0100
    [PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC Matthew McClintock <mmcclint@qca.qualcomm.com> - 2015-11-20 00:30 +0100

#1273582 — [PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs

FromMatthew McClintock <mmcclint@qca.qualcomm.com>
Date2015-11-20 00:20 +0100
Subject[PATCH v3 0/6] arm: qcom: Add support for IPQ8014 family of SoCs
Message-ID<qwGEF-7yE-5@gated-at.bofh.it>
This patch series adds basic support for IPQ8019 series of SoCs,
presently it just boots to prompt via serial but more functionality
will follow.

This is partially based off a previously submitted patch series from
Varada which can be found here:

https://patchwork.ozlabs.org/patch/509954/

The IPQ8019 has a Quad-Core ARM Cortex A7 with integrated Wifi, GMAC,
Swtich, USB, PCIe, and more..

v3 of this series adds one patch to bring up secondary cores

Changes:

pinctrl changes:
v3
- update example with actual values from dts
- add missing pins 71-99
- drop many functions and stick to basic functionality

v2
- add a note in the device tree binding about the TLMM block

gcc changes:
v3:
- fix unused variable from refactored code

v2:
- drop calls qcom_cc_remove, gcc_ipq4019_remove
- move defines into clk structs
- remove src,cfg in struct initializations
- make hex values lowercase
- clean up MODULE_ALIAS and MODULE_DESCRIPTION
- change tabs after define to spacein dt include files
- remove extra AUDIO_BLK_ARES define
- remove unneeded of_match_device from gcc_ipq4019_probe
- move sleep_clk and xo to soc and board level dts
- drop all the (not required) fixed-clocks for now
- combine reset dts include files into one overall dts include

SoC dts file:
v2
- add sleep_clk

Board dts file:
- add xo clock

Matthew McClintock (4):
  ARM: qcom: add IPQ4019 compatible match
  qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
  dts: ipq4019: Add support for IPQ4019 DK01 board
  qcom: ipq4019: add acc and saw nodes to bring up secondary cores

Varadarajan Narayanan (2):
  pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support
  clk: qcom: Add IPQ4019 Global Clock Controller support

 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt      |   74 ++
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts    |   22 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi      |   59 +
 arch/arm/boot/dts/qcom-ipq4019.dtsi                |  175 +++
 arch/arm/mach-qcom/board.c                         |    1 +
 drivers/clk/qcom/Kconfig                           |    9 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/gcc-ipq4019.c                     | 1355 ++++++++++++++++++++
 drivers/pinctrl/qcom/Kconfig                       |    8 +
 drivers/pinctrl/qcom/Makefile                      |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq4019.c             |  454 +++++++
 include/dt-bindings/clock/qcom,gcc-ipq4019.h       |  158 +++
 14 files changed, 2319 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq4019.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq4019.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq4019.h

-- 
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a Linux Foundation Collaborative Project

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#1273583 — [PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board

FromMatthew McClintock <mmcclint@qca.qualcomm.com>
Date2015-11-20 00:30 +0100
Subject[PATCH v3 5/6] dts: ipq4019: Add support for IPQ4019 DK01 board
Message-ID<qwGOm-7Dg-7@gated-at.bofh.it>
In reply to#1273582
From: Matthew McClintock <mmcclint@codeaurora.org>

Initial board support dts files for DK01 board.

Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---

v2
- add xo clock

 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +++++++++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   | 59 +++++++++++++++++++++++++
 3 files changed, 82 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..11b151e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 	qcom-apq8074-dragonboard.dtb \
 	qcom-apq8084-ifc6540.dtb \
 	qcom-apq8084-mtp.dtb \
+	qcom-ipq4019-ap.dk01.1-c1.dtb \
 	qcom-ipq8064-ap148.dtb \
 	qcom-msm8660-surf.dtb \
 	qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 0000000..0d92f1b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 0000000..fe78f3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,59 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+	compatible = "qcom,ipq4019";
+
+	clocks {
+                xo: xo {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+	};
+
+	soc {
+
+
+		timer {
+			compatible = "arm,armv7-timer";
+			interrupts = <1 2 0xf08>,
+				     <1 3 0xf08>,
+				     <1 4 0xf08>,
+				     <1 1 0xf08>;
+			clock-frequency = <48000000>;
+		};
+
+		pinctrl@0x01000000 {
+			serial_pins: serial_pinmux {
+				mux {
+					pins = "gpio60", "gpio61";
+					function = "blsp_uart0";
+					bias-disable;
+				};
+			};
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+		};
+	};
+};
-- 
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a Linux Foundation Collaborative Project

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#1273584 — [PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

FromMatthew McClintock <mmcclint@qca.qualcomm.com>
Date2015-11-20 00:30 +0100
Subject[PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
Message-ID<qwGOm-7Dg-11@gated-at.bofh.it>
In reply to#1273582
From: Matthew McClintock <mmcclint@codeaurora.org>

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---

v2
- add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 ++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 0000000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ4019";
+	compatible = "qcom,ipq4019";
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x3>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+		};
+	};
+
+	clocks {
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "simple-bus";
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>,
+			<0x0b002000 0x1000>;
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq4019";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			reg = <0x1800000 0x60000>;
+		};
+
+		tlmm: pinctrl@0x01000000 {
+			compatible = "qcom,ipq4019-pinctrl";
+			reg = <0x01000000 0x300000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 208 0>;
+		};
+
+		serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78af000 0x200>;
+			interrupts = <0 107 0>;
+			status = "disabled";
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				<&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+		};
+
+		serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78b0000 0x200>;
+			interrupts = <0 108 0>;
+			status = "disabled";
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				<&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+		};
+	};
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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