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Groups > linux.kernel > #1273368 > unrolled thread
| Started by | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| First post | 2015-11-19 19:50 +0100 |
| Last post | 2015-11-24 03:50 +0100 |
| Articles | 20 on this page of 54 — 4 participants |
Back to article view | Back to linux.kernel
[PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 22/25] ARM: shmobile: koelsch dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 16/25] serial: sh-sci: Correct SCIF type on RZ/A1H Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 20/25] serial: sh-sci: Add support for optional BRG on (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:00 +0100
Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 15:50 +0100
Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:20 +0100
Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:40 +0100
[PATCH 05/25] serial: sh-sci: Drop unused frame_len parameter for sci_baud_calc_hscif() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:20 +0100
[PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:30 +0100
Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:50 +0100
Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:20 +0100
Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:00 +0100
[PATCH 04/25] serial: sh-sci: Grammar s/Get ... for/Get ... from/ Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:00 +0100
Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 08:50 +0100
Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:00 +0100
Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:40 +0100
Re: [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:40 +0100
[PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 14/25] serial: sh-sci: Add BRG register definitions Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:50 +0100
[PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get() Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:40 +0100
[PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:20 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 21:30 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:50 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:20 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:10 +0100
Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-19 21:40 +0100
[PATCH 03/25] serial: sh-sci: Drop useless check for zero sampling_rate Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 24/25] arm64: renesas: salvator-x dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 19/25] serial: sh-sci: Add support for optional external (H)SCK input Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 19:50 +0100
[PATCH 11/25] serial: sh-sci: Avoid calculating the receive margin for HSCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
[PATCH 12/25] serial: sh-sci: Merge sci_scbrr_calc() and sci_baud_calc_hscif() Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
[PATCH 10/25] serial: sh-sci: Improve bit rate error calculation for HSCIF Geert Uytterhoeven <geert+renesas@glider.be> - 2015-11-19 20:00 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-19 22:10 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 09:30 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 10:00 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 10:10 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2015-11-20 16:00 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 16:40 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven <geert@linux-m68k.org> - 2015-11-20 10:10 +0100
Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Simon Horman <horms@verge.net.au> - 2015-11-24 03:50 +0100
Page 1 of 3 [1] 2 3 Next page →
| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support |
| Message-ID | <qwChI-4Cb-7@gated-at.bofh.it> |
Hi,
This patch series adds support to the Renesas SCI serial driver for
- the optional external clock on (H)SCI(F) and some SCIFA, where this
pin can serve as a clock input,
- the optional clock sources for the Baud Rate Generator for External
Clock (BRG), as found on some SCIF variants and on HSCIF.
Using external clocks increases the range and accuracy of supported baud
rates. Please see the descriptions of the DTS patches for more detailed
information regarding the impact on the supported platforms.
For now this supports r8a7791/koelsch and r8a7795/salvator-x only, which
have an external SCIF_CLK running at 14.7456 MHz.
Support for other R-Car platforms will be added later.
Testing:
- The Baud Rate Generator for External Clock (BRG) was tested with
SCIF and HSCIF on r8a7791/koelsch and r8a7795/salvator-x,
- The external clock input on (H)SCK was tested on r8a7795/salvator-x
by feeding an external clock signal to (H)SCIF1,
- Various bit rates were monitored using a SmartScope,
- Regression testing was done on Renesas ARM platforms that use SCIFA
as the console (r8a73a4/ape6evm, r8a7740/armadillo, and
sh73a0/kzm9g).
Dependencies:
- This series depends on the series "[PATCH v2 00/16] serial: sh-sci:
Clock Cleanups",
- The SH patch 25 depends on the "serial: sh-sci" patches in this
series,
- The DTS patches 21-24 can be applied independently, once the DT
binding patches 1-2 are accepted,
- r8a7791/r8a7795 has a runtime dependency on series "[PATCH 0/2]
pinctrl: sh-pfc: r8a7791/r8a7795: Add SCIF_CLK support",
- r8a7795 also depends on
- platform support in e.g. renesas-drivers-2015-11-17-v4.4-rc1,
- "[PATCH] pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and
functions",
- "[PATCH] arm64: renesas: r8a7795 dtsi: Add all HSCIF nodes".
- Legacy SH has a runtime dependency on:
- series "[PATCH 0/2] drivers: sh: clk: Cleanup clock API",
Thanks for your comments!
Geert Uytterhoeven (25):
serial: sh-sci: Update DT binding documentation for external clock
input
serial: sh-sci: Update DT binding documentation for BRG support
serial: sh-sci: Drop useless check for zero sampling_rate
serial: sh-sci: Grammar s/Get ... for/Get ... from/
serial: sh-sci: Drop unused frame_len parameter for
sci_baud_calc_hscif()
serial: sh-sci: Don't overwrite clock selection in
serial_console_write()
serial: sh-sci: Convert from clk_get() to devm_clk_get()
serial: sh-sci: Make unsigned values in sci_baud_calc_hscif() unsigned
serial: sh-sci: Avoid overflow in sci_baud_calc_hscif()
serial: sh-sci: Improve bit rate error calculation for HSCIF
serial: sh-sci: Avoid calculating the receive margin for HSCIF
serial: sh-sci: Merge sci_scbrr_calc() and sci_baud_calc_hscif()
serial: sh-sci: Take into account sampling rate for max baud rate
serial: sh-sci: Add BRG register definitions
serial: sh-sci: Replace struct sci_port_info by type/regtype encoding
serial: sh-sci: Correct SCIF type on RZ/A1H
serial: sh-sci: Correct SCIF type on R-Car for BRG
serial: sh-sci: Prepare for multiple clocks and baud rate generators
serial: sh-sci: Add support for optional external (H)SCK input
serial: sh-sci: Add support for optional BRG on (H)SCIF
ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF
ARM: shmobile: koelsch dts: Enable SCIF_CLK frequency and pins
arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF
arm64: renesas: salvator-x dts: Enable SCIF_CLK frequency and pins
sh: sh7734: Correct SCIF type for BRG
.../bindings/serial/renesas,sci-serial.txt | 9 +
arch/arm/boot/dts/r8a7791-koelsch.dts | 13 +
arch/arm/boot/dts/r8a7791.dtsi | 54 ++-
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 74 ++-
arch/sh/kernel/cpu/sh4a/setup-sh7734.c | 12 +-
drivers/tty/serial/sh-sci.c | 530 +++++++++++++++------
drivers/tty/serial/sh-sci.h | 5 +
include/linux/serial_sci.h | 1 +
9 files changed, 508 insertions(+), 202 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 22/25] ARM: shmobile: koelsch dts: Enable SCIF_CLK frequency and pins |
| Message-ID | <qwCro-4G9-15@gated-at.bofh.it> |
| In reply to | #1273368 |
Add and enable the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
This increases the range and accuracy of supported baud rates:
- SCIF:
- Supports now 50, 75, 110, 1152000, 1500000, 2000000, and
4000000 bps,
- Perfect match for standard 50-460800, and 9216000 bps.
- More accurate 576000 bps.
- HSCIF:
- Supports now 50, 75, 110, 134, 150, and 200 bps,
- Perfect match for standard 50-460800, and 9216000 bps.
- More accurate 576000, 1152000, 3000000, 3500000, and 4000000
bps.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index da263dbb126db78c..9c3bc94791fc932a 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -320,6 +320,9 @@
};
&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
@@ -340,6 +343,11 @@
renesas,function = "scif1";
};
+ scif_clk_pins: scif_clk {
+ renesas,groups = "scif_clk";
+ renesas,function = "scif_clk";
+ };
+
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
@@ -440,6 +448,11 @@
status = "okay";
};
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
--
1.9.1
--
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 16/25] serial: sh-sci: Correct SCIF type on RZ/A1H |
| Message-ID | <qwCro-4G9-17@gated-at.bofh.it> |
| In reply to | #1273368 |
The "renesas,scif" compatible value is currently used for the SCIF
variant in all Renesas SoCs of the R-Car and RZ families. However, the
variant used in the RZ family is not the common "SH-4(A)" variant, but
the "SH-2(A) with FIFO data count register" variant, as it has the
"Serial Extension Mode Register" (SCEMR), just like on sh7203, sh7263,
sh7264, and sh7269.
Use the (already documented) SoC-specific "renesas,scif-r7s72100"
compatible value to differentiate. The "renesas,scif" compatible value
can still be used as a common denominator for SCIF variants with the
"SH-4(A)" register layout (i.e. ignoring the SCEMR register).
Note that currently both variants are treated the same, but this may
change if support for the SCEMR register is ever added.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/tty/serial/sh-sci.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 41351ae055de661f..b0127f38af744fcf 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2601,6 +2601,12 @@ static int sci_remove(struct platform_device *dev)
#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
static const struct of_device_id of_sci_match[] = {
+ /* SoC-specific types */
+ {
+ .compatible = "renesas,scif-r7s72100",
+ .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
+ },
+ /* Generic types */
{
.compatible = "renesas,scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
--
1.9.1
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 20/25] serial: sh-sci: Add support for optional BRG on (H)SCIF |
| Message-ID | <qwCro-4G9-23@gated-at.bofh.it> |
| In reply to | #1273368 |
Add support for the Baud Rate Generator for External Clock (BRG), as
found on some SCIF and HSCIF variants, which can improve baud rate range
and accuracy.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/tty/serial/sh-sci.c | 82 ++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 77 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f88aac684ed1e3b6..6b8f1675b9f6fadb 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -80,6 +80,8 @@ enum {
enum SCI_CLKS {
SCI_FCK, /* Functional Clock */
SCI_SCK, /* Optional External Clock */
+ SCI_INT_CLK, /* Optional BRG Internal Clock Source */
+ SCI_SCIF_CLK, /* Optional BRG External Clock Source */
SCI_NUM_CLKS
};
@@ -1955,6 +1957,40 @@ static int sci_sck_calc(struct sci_port *s, unsigned int bps,
return min_err;
}
+static int sci_brg_calc(struct sci_port *s, unsigned int bps,
+ unsigned long freq, unsigned int *dlr,
+ unsigned int *srr)
+{
+ unsigned int min_sr, max_sr, sr, dl;
+ int err, min_err = INT_MAX;
+
+ if (s->sampling_rate) {
+ /* SCIF has a fixed sampling rate */
+ min_sr = max_sr = s->sampling_rate / 2;
+ } else {
+ /* HSCIF has a variable 1/(8..32) sampling rate */
+ min_sr = 8;
+ max_sr = 32;
+ }
+
+ for (sr = max_sr; sr >= min_sr; sr--) {
+ dl = DIV_ROUND_CLOSEST(freq, sr * bps);
+ dl = clamp(dl, 1U, 65535U);
+
+ err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
+ if (abs(err) >= abs(min_err))
+ continue;
+
+ min_err = err;
+ *dlr = dl;
+ *srr = sr - 1;
+ }
+
+ dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
+ min_err, *dlr, *srr + 1);
+ return min_err;
+}
+
/* calculate sample rate, BRR, and clock select */
static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
unsigned int *brr, unsigned int *srr,
@@ -2036,8 +2072,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
unsigned int baud, smr_val = 0, scr_val = 0, i;
- unsigned int brr = 255, cks = 0, srr = 15, sccks = 0;
- unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
+ unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
+ unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
struct sci_port *s = to_sci_port(port);
const struct plat_sci_reg *reg;
int min_err = INT_MAX, err;
@@ -2089,6 +2125,38 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
}
}
+ /* Optional BRG External Clock Source */
+ if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
+ err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
+ &srr1);
+ if (abs(err) < abs(min_err)) {
+ best_clk = SCI_SCIF_CLK;
+ scr_val = SCSCR_CKE1;
+ sccks = 0;
+ min_err = err;
+ dl = dl1;
+ srr = srr1;
+ if (!err)
+ goto done;
+ }
+ }
+
+ /* Optional BRG Internal Clock Source */
+ if (s->clk_rates[SCI_INT_CLK] && sci_getreg(port, SCDL)->size) {
+ err = sci_brg_calc(s, baud, s->clk_rates[SCI_INT_CLK], &dl1,
+ &srr1);
+ if (abs(err) < abs(min_err)) {
+ best_clk = SCI_INT_CLK;
+ scr_val = SCSCR_CKE1;
+ sccks = SCCKS_XIN;
+ min_err = err;
+ dl = dl1;
+ srr = srr1;
+ if (!min_err)
+ goto done;
+ }
+ }
+
/* Functional Clock and standard Bit Rate Register */
err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
if (abs(err) < abs(min_err)) {
@@ -2108,8 +2176,10 @@ done:
sci_port_enable(s);
/* Program the optional External Baud Rate Generator (BRG) first */
- if (best_clk >= 0 && sci_getreg(port, SCCKS)->size)
+ if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
+ serial_port_out(port, SCDL, dl);
serial_port_out(port, SCCKS, sccks);
+ }
sci_reset(port);
@@ -2118,8 +2188,8 @@ done:
if (best_clk >= 0) {
smr_val |= cks;
dev_dbg(port->dev,
- "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x SRR %u\n",
- scr_val, smr_val, brr, sccks, srr);
+ "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
+ scr_val, smr_val, brr, sccks, dl, srr);
serial_port_out(port, SCSCR, scr_val);
serial_port_out(port, SCSMR, smr_val);
serial_port_out(port, SCBRR, brr);
@@ -2357,6 +2427,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
const char *clk_names[] = {
[SCI_FCK] = "fck",
[SCI_SCK] = "sck",
+ [SCI_INT_CLK] = "int_clk",
+ [SCI_SCIF_CLK] = "scif_clk",
};
struct clk *clk;
unsigned int i;
--
1.9.1
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwCro-4G9-25@gated-at.bofh.it> |
| In reply to | #1273368 |
Refactor the clock and baud rate parameter code to ease adding support
for multiple clocks and baud rate generators later.
sci_scbrr_calc() now returns the bit rate error, so it can be compared
to the bit rate error for other baud rate generators.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/tty/serial/sh-sci.c | 176 ++++++++++++++++++++++++++++++--------------
1 file changed, 120 insertions(+), 56 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 726c96d5a511c222..12800e52f41953dc 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2,6 +2,7 @@
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002 - 2011 Paul Mundt
+ * Copyright (C) 2015 Glider bvba
* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*
* based off of the old drivers/char/sh-sci.c by:
@@ -76,6 +77,11 @@ enum {
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
+enum SCI_CLKS {
+ SCI_FCK, /* Functional Clock */
+ SCI_NUM_CLKS
+};
+
struct sci_port {
struct uart_port port;
@@ -92,8 +98,9 @@ struct sci_port {
struct timer_list break_timer;
int break_flag;
- /* Function clock */
- struct clk *fclk;
+ /* Clocks */
+ struct clk *clks[SCI_NUM_CLKS];
+ unsigned long clk_rates[SCI_NUM_CLKS];
int irqs[SCIx_NR_IRQS];
char *irqstr[SCIx_NR_IRQS];
@@ -496,17 +503,24 @@ static int sci_probe_regmap(struct plat_sci_port *cfg)
static void sci_port_enable(struct sci_port *sci_port)
{
+ unsigned int i;
+
if (!sci_port->port.dev)
return;
pm_runtime_get_sync(sci_port->port.dev);
- clk_prepare_enable(sci_port->fclk);
- sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
+ for (i = 0; i < SCI_NUM_CLKS; i++) {
+ clk_prepare_enable(sci_port->clks[i]);
+ sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
+ }
+ sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
}
static void sci_port_disable(struct sci_port *sci_port)
{
+ unsigned int i;
+
if (!sci_port->port.dev)
return;
@@ -518,7 +532,8 @@ static void sci_port_disable(struct sci_port *sci_port)
del_timer_sync(&sci_port->break_timer);
sci_port->break_flag = 0;
- clk_disable_unprepare(sci_port->fclk);
+ for (i = SCI_NUM_CLKS; i-- > 0; )
+ clk_disable_unprepare(sci_port->clks[i]);
pm_runtime_put_sync(sci_port->port.dev);
}
@@ -1657,6 +1672,7 @@ static int sci_notifier(struct notifier_block *self,
{
struct sci_port *sci_port;
unsigned long flags;
+ unsigned int i;
sci_port = container_of(self, struct sci_port, freq_transition);
@@ -1664,7 +1680,9 @@ static int sci_notifier(struct notifier_block *self,
struct uart_port *port = &sci_port->port;
spin_lock_irqsave(&port->lock, flags);
- port->uartclk = clk_get_rate(sci_port->fclk);
+ for (i = 0; i < SCI_NUM_CLKS; i++)
+ sci_port->clk_rates[i] =
+ clk_get_rate(sci_port->clks[i]);
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -1907,11 +1925,12 @@ static void sci_shutdown(struct uart_port *port)
}
/* calculate sample rate, BRR, and clock select */
-static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
- unsigned long freq, int *brr, unsigned int *srr,
- unsigned int *cks)
+static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
+ unsigned int *brr, unsigned int *srr,
+ unsigned int *cks)
{
unsigned int min_sr, max_sr, shift, sr, br, a, b, c;
+ unsigned long freq = s->clk_rates[SCI_FCK];
int err, min_err = INT_MAX;
if (s->sampling_rate) {
@@ -1963,6 +1982,7 @@ static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
min_err, *brr, *srr + 1, *cks);
+ return min_err;
}
static void sci_reset(struct uart_port *port)
@@ -1984,11 +2004,14 @@ static void sci_reset(struct uart_port *port)
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
+ unsigned int baud, smr_val = 0, scr_val = 0, i;
+ unsigned int brr = 255, cks = 0, srr = 15;
+ unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
struct sci_port *s = to_sci_port(port);
const struct plat_sci_reg *reg;
- unsigned int baud, smr_val = 0, max_baud, cks = 0;
- int t = -1;
- unsigned int srr = 15;
+ int min_err = INT_MAX, err;
+ unsigned long max_freq = 0;
+ int best_clk = -1;
if ((termios->c_cflag & CSIZE) == CS7)
smr_val |= SCSMR_CHR;
@@ -2007,35 +2030,59 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
* that the previous boot loader has enabled required clocks and
* setup the baud rate generator hardware for us already.
*/
- if (port->uartclk)
- max_baud = port->uartclk / max(s->sampling_rate, 8U);
- else
- max_baud = 115200;
+ if (!port->uartclk) {
+ baud = uart_get_baud_rate(port, termios, old, 0, 115200);
+ goto done;
+ }
- baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
- if (likely(baud && port->uartclk))
- sci_scbrr_calc(s, baud, port->uartclk, &t, &srr, &cks);
+ for (i = 0; i < SCI_NUM_CLKS; i++)
+ max_freq = max(max_freq, s->clk_rates[i]);
+
+ baud = uart_get_baud_rate(port, termios, old, 0,
+ max_freq / max(s->sampling_rate, 8U));
+ if (!baud)
+ goto done;
+
+ /* Functional Clock and standard Bit Rate Register */
+ err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
+ if (abs(err) < abs(min_err)) {
+ best_clk = SCI_FCK;
+ min_err = err;
+ brr = brr1;
+ srr = srr1;
+ cks = cks1;
+ }
+
+done:
+ if (best_clk >= 0)
+ dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
+ s->clks[best_clk], baud, min_err);
sci_port_enable(s);
sci_reset(port);
- smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
-
uart_update_timeout(port, termios->c_cflag, baud);
- dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
- __func__, smr_val, cks, t, s->cfg->scscr);
-
- if (t >= 0) {
- serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
- serial_port_out(port, SCBRR, t);
- reg = sci_getreg(port, HSSRR);
- if (reg->size)
+ if (best_clk >= 0) {
+ smr_val |= cks;
+ dev_dbg(port->dev, "SMR 0x%x BRR %u SRR %u\n", smr_val, brr,
+ srr);
+ serial_port_out(port, SCSMR, smr_val);
+ serial_port_out(port, SCBRR, brr);
+ if (sci_getreg(port, HSSRR)->size)
serial_port_out(port, HSSRR, srr | HSCIF_SRE);
- udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
- } else
+
+ /* Wait one bit interval */
+ udelay((1000000 + (baud - 1)) / baud);
+ } else {
+ /* Don't touch the bit rate configuration */
+ scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
+ smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
+ dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
+ serial_port_out(port, SCSCR, scr_val);
serial_port_out(port, SCSMR, smr_val);
+ }
sci_init_pins(port, termios->c_cflag);
@@ -2060,7 +2107,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
serial_port_out(port, SCFCR, ctrl);
}
- serial_port_out(port, SCSCR, s->cfg->scscr);
+ scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
+ dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
+ serial_port_out(port, SCSCR, scr_val);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
/*
@@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
{
- /* Get the SCI functional clock. It's called "fck" on ARM. */
- sci_port->fclk = devm_clk_get(dev, "fck");
- if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
- if (!IS_ERR(sci_port->fclk))
- return 0;
+ const char *clk_names[] = {
+ [SCI_FCK] = "fck",
+ };
+ struct clk *clk;
+ unsigned int i;
- /*
- * But it used to be called "sci_ick", and we need to maintain DT
- * backward compatibility.
- */
- sci_port->fclk = devm_clk_get(dev, "sci_ick");
- if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
- if (!IS_ERR(sci_port->fclk))
- return 0;
+ for (i = 0; i < SCI_NUM_CLKS; i++) {
+ clk = devm_clk_get(dev, clk_names[i]);
+ if (PTR_ERR(clk) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
- /*
- * Not all SH platforms declare a clock lookup entry for SCI devices,
- * in which case we need to get the global "peripheral_clk" clock.
- */
- sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
- if (!IS_ERR(sci_port->fclk))
- return 0;
+ if (IS_ERR(clk) && i == SCI_FCK) {
+ /*
+ * "fck" used to be called "sci_ick", and we need to
+ * maintain DT backward compatibility.
+ */
+ clk = devm_clk_get(dev, "sci_ick");
+ if (PTR_ERR(clk) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ if (!IS_ERR(clk))
+ goto found;
+
+ /*
+ * Not all SH platforms declare a clock lookup entry
+ * for SCI devices, in which case we need to get the
+ * global "peripheral_clk" clock.
+ */
+ clk = devm_clk_get(dev, "peripheral_clk");
+ if (!IS_ERR(clk))
+ goto found;
+
+ dev_err(dev, "failed to get functional clock\n");
+ return PTR_ERR(clk);
+ }
- dev_err(dev, "failed to get functional clock\n");
- return PTR_ERR(sci_port->fclk);
+found:
+ if (!IS_ERR(clk))
+ dev_dbg(dev, "clk %u is %pC rate %pCr\n", i, clk, clk);
+ sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
+ }
+ return 0;
}
static int sci_init_single(struct platform_device *dev,
--
1.9.1
--
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-19 22:10 +0100 |
| Subject | Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwECS-6fX-19@gated-at.bofh.it> |
| In reply to | #1273374 |
Hi Geert,
Thank you for the patch.
On Thursday 19 November 2015 19:38:57 Geert Uytterhoeven wrote:
> Refactor the clock and baud rate parameter code to ease adding support
> for multiple clocks and baud rate generators later.
> sci_scbrr_calc() now returns the bit rate error, so it can be compared
> to the bit rate error for other baud rate generators.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> drivers/tty/serial/sh-sci.c | 176 +++++++++++++++++++++++++++--------------
> 1 file changed, 120 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 726c96d5a511c222..12800e52f41953dc 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2,6 +2,7 @@
> * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
> *
> * Copyright (C) 2002 - 2011 Paul Mundt
> + * Copyright (C) 2015 Glider bvba
> * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
> *
> * based off of the old drivers/char/sh-sci.c by:
> @@ -76,6 +77,11 @@ enum {
> ((port)->irqs[SCIx_ERI_IRQ] && \
> ((port)->irqs[SCIx_RXI_IRQ] < 0))
>
> +enum SCI_CLKS {
> + SCI_FCK, /* Functional Clock */
> + SCI_NUM_CLKS
> +};
> +
> struct sci_port {
> struct uart_port port;
>
> @@ -92,8 +98,9 @@ struct sci_port {
> struct timer_list break_timer;
> int break_flag;
>
> - /* Function clock */
> - struct clk *fclk;
> + /* Clocks */
> + struct clk *clks[SCI_NUM_CLKS];
> + unsigned long clk_rates[SCI_NUM_CLKS];
>
> int irqs[SCIx_NR_IRQS];
> char *irqstr[SCIx_NR_IRQS];
> @@ -496,17 +503,24 @@ static int sci_probe_regmap(struct plat_sci_port *cfg)
>
> static void sci_port_enable(struct sci_port *sci_port)
> {
> + unsigned int i;
> +
> if (!sci_port->port.dev)
> return;
>
> pm_runtime_get_sync(sci_port->port.dev);
>
> - clk_prepare_enable(sci_port->fclk);
> - sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
> + for (i = 0; i < SCI_NUM_CLKS; i++) {
> + clk_prepare_enable(sci_port->clks[i]);
> + sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
> + }
> + sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
> }
>
> static void sci_port_disable(struct sci_port *sci_port)
> {
> + unsigned int i;
> +
> if (!sci_port->port.dev)
> return;
>
> @@ -518,7 +532,8 @@ static void sci_port_disable(struct sci_port *sci_port)
> del_timer_sync(&sci_port->break_timer);
> sci_port->break_flag = 0;
>
> - clk_disable_unprepare(sci_port->fclk);
> + for (i = SCI_NUM_CLKS; i-- > 0; )
> + clk_disable_unprepare(sci_port->clks[i]);
>
> pm_runtime_put_sync(sci_port->port.dev);
> }
> @@ -1657,6 +1672,7 @@ static int sci_notifier(struct notifier_block *self,
> {
> struct sci_port *sci_port;
> unsigned long flags;
> + unsigned int i;
>
> sci_port = container_of(self, struct sci_port, freq_transition);
>
> @@ -1664,7 +1680,9 @@ static int sci_notifier(struct notifier_block *self,
> struct uart_port *port = &sci_port->port;
>
> spin_lock_irqsave(&port->lock, flags);
> - port->uartclk = clk_get_rate(sci_port->fclk);
> + for (i = 0; i < SCI_NUM_CLKS; i++)
> + sci_port->clk_rates[i] =
> + clk_get_rate(sci_port->clks[i]);
> spin_unlock_irqrestore(&port->lock, flags);
> }
>
> @@ -1907,11 +1925,12 @@ static void sci_shutdown(struct uart_port *port)
> }
>
> /* calculate sample rate, BRR, and clock select */
> -static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
> - unsigned long freq, int *brr, unsigned int *srr,
> - unsigned int *cks)
> +static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
> + unsigned int *brr, unsigned int *srr,
> + unsigned int *cks)
> {
> unsigned int min_sr, max_sr, shift, sr, br, a, b, c;
> + unsigned long freq = s->clk_rates[SCI_FCK];
> int err, min_err = INT_MAX;
>
> if (s->sampling_rate) {
> @@ -1963,6 +1982,7 @@ static void sci_scbrr_calc(struct sci_port *s,
> unsigned int bps,
>
> dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
> min_err, *brr, *srr + 1, *cks);
> + return min_err;
> }
>
> static void sci_reset(struct uart_port *port)
> @@ -1984,11 +2004,14 @@ static void sci_reset(struct uart_port *port)
> static void sci_set_termios(struct uart_port *port, struct ktermios
> *termios, struct ktermios *old)
> {
> + unsigned int baud, smr_val = 0, scr_val = 0, i;
> + unsigned int brr = 255, cks = 0, srr = 15;
> + unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
> struct sci_port *s = to_sci_port(port);
> const struct plat_sci_reg *reg;
> - unsigned int baud, smr_val = 0, max_baud, cks = 0;
> - int t = -1;
> - unsigned int srr = 15;
> + int min_err = INT_MAX, err;
> + unsigned long max_freq = 0;
> + int best_clk = -1;
>
> if ((termios->c_cflag & CSIZE) == CS7)
> smr_val |= SCSMR_CHR;
> @@ -2007,35 +2030,59 @@ static void sci_set_termios(struct uart_port *port,
> struct ktermios *termios, * that the previous boot loader has enabled
> required clocks and * setup the baud rate generator hardware for us
> already.
> */
> - if (port->uartclk)
> - max_baud = port->uartclk / max(s->sampling_rate, 8U);
> - else
> - max_baud = 115200;
> + if (!port->uartclk) {
> + baud = uart_get_baud_rate(port, termios, old, 0, 115200);
> + goto done;
> + }
>
> - baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
> - if (likely(baud && port->uartclk))
> - sci_scbrr_calc(s, baud, port->uartclk, &t, &srr, &cks);
> + for (i = 0; i < SCI_NUM_CLKS; i++)
> + max_freq = max(max_freq, s->clk_rates[i]);
> +
> + baud = uart_get_baud_rate(port, termios, old, 0,
> + max_freq / max(s->sampling_rate, 8U));
> + if (!baud)
> + goto done;
> +
> + /* Functional Clock and standard Bit Rate Register */
> + err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
> + if (abs(err) < abs(min_err)) {
> + best_clk = SCI_FCK;
> + min_err = err;
> + brr = brr1;
> + srr = srr1;
> + cks = cks1;
> + }
> +
> +done:
> + if (best_clk >= 0)
> + dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
> + s->clks[best_clk], baud, min_err);
>
> sci_port_enable(s);
>
> sci_reset(port);
>
> - smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
> -
> uart_update_timeout(port, termios->c_cflag, baud);
>
> - dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
> - __func__, smr_val, cks, t, s->cfg->scscr);
> -
> - if (t >= 0) {
> - serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
> - serial_port_out(port, SCBRR, t);
> - reg = sci_getreg(port, HSSRR);
> - if (reg->size)
> + if (best_clk >= 0) {
> + smr_val |= cks;
> + dev_dbg(port->dev, "SMR 0x%x BRR %u SRR %u\n", smr_val, brr,
> + srr);
> + serial_port_out(port, SCSMR, smr_val);
> + serial_port_out(port, SCBRR, brr);
> + if (sci_getreg(port, HSSRR)->size)
> serial_port_out(port, HSSRR, srr | HSCIF_SRE);
> - udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
> - } else
> +
> + /* Wait one bit interval */
> + udelay((1000000 + (baud - 1)) / baud);
> + } else {
> + /* Don't touch the bit rate configuration */
> + scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
> + smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
> + dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
> + serial_port_out(port, SCSCR, scr_val);
> serial_port_out(port, SCSMR, smr_val);
> + }
>
> sci_init_pins(port, termios->c_cflag);
>
> @@ -2060,7 +2107,9 @@ static void sci_set_termios(struct uart_port *port,
> struct ktermios *termios, serial_port_out(port, SCFCR, ctrl);
> }
>
> - serial_port_out(port, SCSCR, s->cfg->scscr);
> + scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
> + dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
> + serial_port_out(port, SCSCR, scr_val);
>
> #ifdef CONFIG_SERIAL_SH_SCI_DMA
> /*
> @@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
>
> static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
> {
> - /* Get the SCI functional clock. It's called "fck" on ARM. */
> - sci_port->fclk = devm_clk_get(dev, "fck");
> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> - return -EPROBE_DEFER;
> - if (!IS_ERR(sci_port->fclk))
> - return 0;
> + const char *clk_names[] = {
> + [SCI_FCK] = "fck",
> + };
> + struct clk *clk;
> + unsigned int i;
>
> - /*
> - * But it used to be called "sci_ick", and we need to maintain DT
> - * backward compatibility.
> - */
> - sci_port->fclk = devm_clk_get(dev, "sci_ick");
> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> - return -EPROBE_DEFER;
> - if (!IS_ERR(sci_port->fclk))
> - return 0;
> + for (i = 0; i < SCI_NUM_CLKS; i++) {
> + clk = devm_clk_get(dev, clk_names[i]);
> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
>
> - /*
> - * Not all SH platforms declare a clock lookup entry for SCI devices,
> - * in which case we need to get the global "peripheral_clk" clock.
> - */
> - sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
> - if (!IS_ERR(sci_port->fclk))
> - return 0;
> + if (IS_ERR(clk) && i == SCI_FCK) {
> + /*
> + * "fck" used to be called "sci_ick", and we need to
> + * maintain DT backward compatibility.
> + */
> + clk = devm_clk_get(dev, "sci_ick");
> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> +
> + if (!IS_ERR(clk))
> + goto found;
> +
> + /*
> + * Not all SH platforms declare a clock lookup entry
> + * for SCI devices, in which case we need to get the
> + * global "peripheral_clk" clock.
> + */
> + clk = devm_clk_get(dev, "peripheral_clk");
> + if (!IS_ERR(clk))
> + goto found;
> +
> + dev_err(dev, "failed to get functional clock\n");
> + return PTR_ERR(clk);
> + }
>
> - dev_err(dev, "failed to get functional clock\n");
> - return PTR_ERR(sci_port->fclk);
> +found:
> + if (!IS_ERR(clk))
> + dev_dbg(dev, "clk %u is %pC rate %pCr\n", i, clk, clk);
> + sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
Isn't it an issue that we can't tell apart the case where there is no clock
specified in DT and the case where we can't get the clock due to another error
?
> + }
> + return 0;
> }
>
> static int sci_init_single(struct platform_device *dev,
--
Regards,
Laurent Pinchart
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| From | Geert Uytterhoeven <geert@linux-m68k.org> |
|---|---|
| Date | 2015-11-20 09:00 +0100 |
| Subject | Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwOLU-4hH-11@gated-at.bofh.it> |
| In reply to | #1273505 |
Hi Laurent,
On Thu, Nov 19, 2015 at 10:04 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:57 Geert Uytterhoeven wrote:
>> Refactor the clock and baud rate parameter code to ease adding support
>> for multiple clocks and baud rate generators later.
>> sci_scbrr_calc() now returns the bit rate error, so it can be compared
>> to the bit rate error for other baud rate generators.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> drivers/tty/serial/sh-sci.c | 176 +++++++++++++++++++++++++++--------------
>> 1 file changed, 120 insertions(+), 56 deletions(-)
>>
>> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
>> index 726c96d5a511c222..12800e52f41953dc 100644
>> --- a/drivers/tty/serial/sh-sci.c
>> +++ b/drivers/tty/serial/sh-sci.c
>> @@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
>>
>> static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>> {
>> - /* Get the SCI functional clock. It's called "fck" on ARM. */
>> - sci_port->fclk = devm_clk_get(dev, "fck");
>> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>> - return -EPROBE_DEFER;
>> - if (!IS_ERR(sci_port->fclk))
>> - return 0;
>> + const char *clk_names[] = {
>> + [SCI_FCK] = "fck",
>> + };
>> + struct clk *clk;
>> + unsigned int i;
>>
>> - /*
>> - * But it used to be called "sci_ick", and we need to maintain DT
>> - * backward compatibility.
>> - */
>> - sci_port->fclk = devm_clk_get(dev, "sci_ick");
>> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>> - return -EPROBE_DEFER;
>> - if (!IS_ERR(sci_port->fclk))
>> - return 0;
>> + for (i = 0; i < SCI_NUM_CLKS; i++) {
>> + clk = devm_clk_get(dev, clk_names[i]);
>> + if (PTR_ERR(clk) == -EPROBE_DEFER)
>> + return -EPROBE_DEFER;
>>
>> - /*
>> - * Not all SH platforms declare a clock lookup entry for SCI devices,
>> - * in which case we need to get the global "peripheral_clk" clock.
>> - */
>> - sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
>> - if (!IS_ERR(sci_port->fclk))
>> - return 0;
>> + if (IS_ERR(clk) && i == SCI_FCK) {
>> + /*
>> + * "fck" used to be called "sci_ick", and we need to
>> + * maintain DT backward compatibility.
>> + */
>> + clk = devm_clk_get(dev, "sci_ick");
>> + if (PTR_ERR(clk) == -EPROBE_DEFER)
>> + return -EPROBE_DEFER;
>> +
>> + if (!IS_ERR(clk))
>> + goto found;
>> +
>> + /*
>> + * Not all SH platforms declare a clock lookup entry
>> + * for SCI devices, in which case we need to get the
>> + * global "peripheral_clk" clock.
>> + */
>> + clk = devm_clk_get(dev, "peripheral_clk");
>> + if (!IS_ERR(clk))
>> + goto found;
>> +
>> + dev_err(dev, "failed to get functional clock\n");
>> + return PTR_ERR(clk);
>> + }
>>
>> - dev_err(dev, "failed to get functional clock\n");
>> - return PTR_ERR(sci_port->fclk);
>> +found:
>> + if (!IS_ERR(clk))
>> + dev_dbg(dev, "clk %u is %pC rate %pCr\n", i, clk, clk);
>> + sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
>
> Isn't it an issue that we can't tell apart the case where there is no clock
> specified in DT and the case where we can't get the clock due to another error
> ?
All failures here are for optional clocks.
If the real failure is that the clock wasn't specified (or misspelled) in DT,
it should have been detected during the integration phase.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-20 15:50 +0100 |
| Subject | Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwVaG-8uf-5@gated-at.bofh.it> |
| In reply to | #1273772 |
Hi Geert,
On Friday 20 November 2015 08:52:19 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 10:04 PM, Laurent Pinchart wrote:
> > On Thursday 19 November 2015 19:38:57 Geert Uytterhoeven wrote:
> >> Refactor the clock and baud rate parameter code to ease adding support
> >> for multiple clocks and baud rate generators later.
> >> sci_scbrr_calc() now returns the bit rate error, so it can be compared
> >> to the bit rate error for other baud rate generators.
> >>
> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >> ---
> >>
> >> drivers/tty/serial/sh-sci.c | 176 +++++++++++++++++++++++++-------------
> >> 1 file changed, 120 insertions(+), 56 deletions(-)
> >>
> >> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> >> index 726c96d5a511c222..12800e52f41953dc 100644
> >> --- a/drivers/tty/serial/sh-sci.c
> >> +++ b/drivers/tty/serial/sh-sci.c
> >> @@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
> >> static int sci_init_clocks(struct sci_port *sci_port, struct device
> >> *dev)
> >> {
> >> - /* Get the SCI functional clock. It's called "fck" on ARM. */
> >> - sci_port->fclk = devm_clk_get(dev, "fck");
> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> >> - return -EPROBE_DEFER;
> >> - if (!IS_ERR(sci_port->fclk))
> >> - return 0;
> >> + const char *clk_names[] = {
> >> + [SCI_FCK] = "fck",
> >> + };
> >> + struct clk *clk;
> >> + unsigned int i;
> >>
> >> - /*
> >> - * But it used to be called "sci_ick", and we need to maintain DT
> >> - * backward compatibility.
> >> - */
> >> - sci_port->fclk = devm_clk_get(dev, "sci_ick");
> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> >> - return -EPROBE_DEFER;
> >> - if (!IS_ERR(sci_port->fclk))
> >> - return 0;
> >> + for (i = 0; i < SCI_NUM_CLKS; i++) {
> >> + clk = devm_clk_get(dev, clk_names[i]);
> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> >> + return -EPROBE_DEFER;
> >>
> >> - /*
> >> - * Not all SH platforms declare a clock lookup entry for SCI
> >> devices,
> >> - * in which case we need to get the global "peripheral_clk" clock.
> >> - */
> >> - sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
> >> - if (!IS_ERR(sci_port->fclk))
> >> - return 0;
> >> + if (IS_ERR(clk) && i == SCI_FCK) {
> >> + /*
> >> + * "fck" used to be called "sci_ick", and we need
> >> to
> >> + * maintain DT backward compatibility.
> >> + */
> >> + clk = devm_clk_get(dev, "sci_ick");
> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> >> + return -EPROBE_DEFER;
> >> +
> >> + if (!IS_ERR(clk))
> >> + goto found;
> >> +
> >> + /*
> >> + * Not all SH platforms declare a clock lookup
> >> entry
> >> + * for SCI devices, in which case we need to get
> >> the
> >> + * global "peripheral_clk" clock.
> >> + */
> >> + clk = devm_clk_get(dev, "peripheral_clk");
> >> + if (!IS_ERR(clk))
> >> + goto found;
> >> +
> >> + dev_err(dev, "failed to get functional clock\n");
> >> + return PTR_ERR(clk);
> >> + }
> >>
> >> - dev_err(dev, "failed to get functional clock\n");
> >> - return PTR_ERR(sci_port->fclk);
> >> +found:
> >> + if (!IS_ERR(clk))
> >> + dev_dbg(dev, "clk %u is %pC rate %pCr\n", i, clk,
> >> clk);
> >> + sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
> >
> > Isn't it an issue that we can't tell apart the case where there is no
> > clock specified in DT and the case where we can't get the clock due to
> > another error ?
>
> All failures here are for optional clocks.
> If the real failure is that the clock wasn't specified (or misspelled) in
> DT, it should have been detected during the integration phase.
There could be cases where the clock is correctly specified in DT but can't be
retrieved due to a runtime error. I suppose that's mostly theoretical in our
case though. Maybe a dev_dbg for the error case could be useful too ? Can we
tell the case where the clock is not specified in DT apart from other errors
(-EPROBE_DEFER aside as that case is already handled) ?
--
Regards,
Laurent Pinchart
--
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| From | Geert Uytterhoeven <geert@linux-m68k.org> |
|---|---|
| Date | 2015-11-20 16:20 +0100 |
| Subject | Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwVDI-uA-33@gated-at.bofh.it> |
| In reply to | #1274124 |
Hi Laurent,
On Fri, Nov 20, 2015 at 3:47 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Friday 20 November 2015 08:52:19 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 10:04 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 19:38:57 Geert Uytterhoeven wrote:
>> >> Refactor the clock and baud rate parameter code to ease adding support
>> >> for multiple clocks and baud rate generators later.
>> >> sci_scbrr_calc() now returns the bit rate error, so it can be compared
>> >> to the bit rate error for other baud rate generators.
>> >>
>> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> >> ---
>> >>
>> >> drivers/tty/serial/sh-sci.c | 176 +++++++++++++++++++++++++-------------
>> >> 1 file changed, 120 insertions(+), 56 deletions(-)
>> >>
>> >> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
>> >> index 726c96d5a511c222..12800e52f41953dc 100644
>> >> --- a/drivers/tty/serial/sh-sci.c
>> >> +++ b/drivers/tty/serial/sh-sci.c
>> >> @@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
>> >> static int sci_init_clocks(struct sci_port *sci_port, struct device
>> >> *dev)
>> >> {
>> >> - /* Get the SCI functional clock. It's called "fck" on ARM. */
>> >> - sci_port->fclk = devm_clk_get(dev, "fck");
>> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>> >> - return -EPROBE_DEFER;
>> >> - if (!IS_ERR(sci_port->fclk))
>> >> - return 0;
>> >> + const char *clk_names[] = {
>> >> + [SCI_FCK] = "fck",
>> >> + };
>> >> + struct clk *clk;
>> >> + unsigned int i;
>> >>
>> >> - /*
>> >> - * But it used to be called "sci_ick", and we need to maintain DT
>> >> - * backward compatibility.
>> >> - */
>> >> - sci_port->fclk = devm_clk_get(dev, "sci_ick");
>> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
>> >> - return -EPROBE_DEFER;
>> >> - if (!IS_ERR(sci_port->fclk))
>> >> - return 0;
>> >> + for (i = 0; i < SCI_NUM_CLKS; i++) {
>> >> + clk = devm_clk_get(dev, clk_names[i]);
>> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
>> >> + return -EPROBE_DEFER;
>> >>
>> >> - /*
>> >> - * Not all SH platforms declare a clock lookup entry for SCI
>> >> devices,
>> >> - * in which case we need to get the global "peripheral_clk" clock.
>> >> - */
>> >> - sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
>> >> - if (!IS_ERR(sci_port->fclk))
>> >> - return 0;
>> >> + if (IS_ERR(clk) && i == SCI_FCK) {
>> >> + /*
>> >> + * "fck" used to be called "sci_ick", and we need
>> >> to
>> >> + * maintain DT backward compatibility.
>> >> + */
>> >> + clk = devm_clk_get(dev, "sci_ick");
>> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
>> >> + return -EPROBE_DEFER;
>> >> +
>> >> + if (!IS_ERR(clk))
>> >> + goto found;
>> >> +
>> >> + /*
>> >> + * Not all SH platforms declare a clock lookup
>> >> entry
>> >> + * for SCI devices, in which case we need to get
>> >> the
>> >> + * global "peripheral_clk" clock.
>> >> + */
>> >> + clk = devm_clk_get(dev, "peripheral_clk");
>> >> + if (!IS_ERR(clk))
>> >> + goto found;
>> >> +
>> >> + dev_err(dev, "failed to get functional clock\n");
>> >> + return PTR_ERR(clk);
>> >> + }
>> >>
>> >> - dev_err(dev, "failed to get functional clock\n");
>> >> - return PTR_ERR(sci_port->fclk);
>> >> +found:
>> >> + if (!IS_ERR(clk))
>> >> + dev_dbg(dev, "clk %u is %pC rate %pCr\n", i, clk,
>> >> clk);
>> >> + sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
>> >
>> > Isn't it an issue that we can't tell apart the case where there is no
>> > clock specified in DT and the case where we can't get the clock due to
>> > another error ?
>>
>> All failures here are for optional clocks.
>> If the real failure is that the clock wasn't specified (or misspelled) in
>> DT, it should have been detected during the integration phase.
>
> There could be cases where the clock is correctly specified in DT but can't be
> retrieved due to a runtime error. I suppose that's mostly theoretical in our
> case though. Maybe a dev_dbg for the error case could be useful too ? Can we
> tell the case where the clock is not specified in DT apart from other errors
> (-EPROBE_DEFER aside as that case is already handled) ?
If the clock is not in clock/clock-names in DT, the error is definitely -ENOENT.
If the clock is specified in DT, it has a phandle to a clock node. If that
clock hasn't been instantiated yet, the error is EPROBE_DEFER.
Which means there are no other possible error values, right?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-20 16:40 +0100 |
| Subject | Re: [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators |
| Message-ID | <qwVX4-Bk-13@gated-at.bofh.it> |
| In reply to | #1274173 |
On Friday 20 November 2015 16:17:13 Geert Uytterhoeven wrote:
> On Fri, Nov 20, 2015 at 3:47 PM, Laurent Pinchart wrote:
> > On Friday 20 November 2015 08:52:19 Geert Uytterhoeven wrote:
> >> On Thu, Nov 19, 2015 at 10:04 PM, Laurent Pinchart wrote:
> >> > On Thursday 19 November 2015 19:38:57 Geert Uytterhoeven wrote:
> >> >> Refactor the clock and baud rate parameter code to ease adding support
> >> >> for multiple clocks and baud rate generators later.
> >> >> sci_scbrr_calc() now returns the bit rate error, so it can be compared
> >> >> to the bit rate error for other baud rate generators.
> >> >>
> >> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >> >> ---
> >> >>
> >> >> drivers/tty/serial/sh-sci.c | 176
> >> >> +++++++++++++++++++++++++-------------
> >> >> 1 file changed, 120 insertions(+), 56 deletions(-)
> >> >>
> >> >> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> >> >> index 726c96d5a511c222..12800e52f41953dc 100644
> >> >> --- a/drivers/tty/serial/sh-sci.c
> >> >> +++ b/drivers/tty/serial/sh-sci.c
> >> >> @@ -2252,33 +2301,48 @@ static struct uart_ops sci_uart_ops = {
> >> >>
> >> >> static int sci_init_clocks(struct sci_port *sci_port, struct device
> >> >> *dev)
> >> >> {
> >> >>
> >> >> - /* Get the SCI functional clock. It's called "fck" on ARM. */
> >> >> - sci_port->fclk = devm_clk_get(dev, "fck");
> >> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> >> >> - return -EPROBE_DEFER;
> >> >> - if (!IS_ERR(sci_port->fclk))
> >> >> - return 0;
> >> >> + const char *clk_names[] = {
> >> >> + [SCI_FCK] = "fck",
> >> >> + };
> >> >> + struct clk *clk;
> >> >> + unsigned int i;
> >> >>
> >> >> - /*
> >> >> - * But it used to be called "sci_ick", and we need to maintain
> >> >> DT
> >> >> - * backward compatibility.
> >> >> - */
> >> >> - sci_port->fclk = devm_clk_get(dev, "sci_ick");
> >> >> - if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
> >> >> - return -EPROBE_DEFER;
> >> >> - if (!IS_ERR(sci_port->fclk))
> >> >> - return 0;
> >> >> + for (i = 0; i < SCI_NUM_CLKS; i++) {
> >> >> + clk = devm_clk_get(dev, clk_names[i]);
> >> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> >> >> + return -EPROBE_DEFER;
> >> >>
> >> >> - /*
> >> >> - * Not all SH platforms declare a clock lookup entry for SCI
> >> >> devices,
> >> >> - * in which case we need to get the global "peripheral_clk"
> >> >> clock.
> >> >> - */
> >> >> - sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
> >> >> - if (!IS_ERR(sci_port->fclk))
> >> >> - return 0;
> >> >> + if (IS_ERR(clk) && i == SCI_FCK) {
> >> >> + /*
> >> >> + * "fck" used to be called "sci_ick", and we
> >> >> need
> >> >> to
> >> >> + * maintain DT backward compatibility.
> >> >> + */
> >> >> + clk = devm_clk_get(dev, "sci_ick");
> >> >> + if (PTR_ERR(clk) == -EPROBE_DEFER)
> >> >> + return -EPROBE_DEFER;
> >> >> +
> >> >> + if (!IS_ERR(clk))
> >> >> + goto found;
> >> >> +
> >> >> + /*
> >> >> + * Not all SH platforms declare a clock lookup
> >> >> entry
> >> >> + * for SCI devices, in which case we need to get
> >> >> the
> >> >> + * global "peripheral_clk" clock.
> >> >> + */
> >> >> + clk = devm_clk_get(dev, "peripheral_clk");
> >> >> + if (!IS_ERR(clk))
> >> >> + goto found;
> >> >> +
> >> >> + dev_err(dev, "failed to get functional
> >> >> clock\n");
> >> >> + return PTR_ERR(clk);
> >> >> + }
> >> >>
> >> >> - dev_err(dev, "failed to get functional clock\n");
> >> >> - return PTR_ERR(sci_port->fclk);
> >> >> +found:
> >> >> + if (!IS_ERR(clk))
> >> >> + dev_dbg(dev, "clk %u is %pC rate %pCr\n", i,
> >> >> clk,
> >> >> clk);
> >> >> + sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
> >> >
> >> > Isn't it an issue that we can't tell apart the case where there is no
> >> > clock specified in DT and the case where we can't get the clock due to
> >> > another error ?
> >>
> >> All failures here are for optional clocks.
> >> If the real failure is that the clock wasn't specified (or misspelled) in
> >> DT, it should have been detected during the integration phase.
> >
> > There could be cases where the clock is correctly specified in DT but
> > can't be retrieved due to a runtime error. I suppose that's mostly
> > theoretical in our case though. Maybe a dev_dbg for the error case could
> > be useful too ? Can we tell the case where the clock is not specified in
> > DT apart from other errors (-EPROBE_DEFER aside as that case is already
> > handled) ?
>
> If the clock is not in clock/clock-names in DT, the error is definitely
> -ENOENT.
>
> If the clock is specified in DT, it has a phandle to a clock node. If that
> clock hasn't been instantiated yet, the error is EPROBE_DEFER.
> Which means there are no other possible error values, right?
There could be other errors returned from __of_clk_get_from_provider if the
clock provider get method returns an error or if __clk_create_clk() fails. The
latter only returns -ENOMEM so we'd have worse issues anyway. I agree that a
clock provider get failure shouldn't be a common case.
--
Regards,
Laurent Pinchart
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 05/25] serial: sh-sci: Drop unused frame_len parameter for sci_baud_calc_hscif() |
| Message-ID | <qwCrp-4G9-29@gated-at.bofh.it> |
| In reply to | #1273368 |
As F is assumed to be zero in the receive margin formula, frame_len is
not used. Remove it, together with the sci_baud_calc_frame_len() helper
function.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/tty/serial/sh-sci.c | 24 +++---------------------
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 676f9d1354943a1b..7c7dfbce54ed9c19 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1866,26 +1866,9 @@ static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
}
-/* calculate frame length from SMR */
-static int sci_baud_calc_frame_len(unsigned int smr_val)
-{
- int len = 10;
-
- if (smr_val & SCSMR_CHR)
- len--;
- if (smr_val & SCSMR_PE)
- len++;
- if (smr_val & SCSMR_STOP)
- len++;
-
- return len;
-}
-
-
/* calculate sample rate, BRR, and clock select for HSCIF */
-static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
- int *brr, unsigned int *srr,
- unsigned int *cks, int frame_len)
+static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, int *brr,
+ unsigned int *srr, unsigned int *cks)
{
int sr, c, br, err, recv_margin;
int min_err = 1000; /* 100% */
@@ -1987,9 +1970,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
if (likely(baud && port->uartclk)) {
if (s->cfg->type == PORT_HSCIF) {
- int frame_len = sci_baud_calc_frame_len(smr_val);
sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
- &cks, frame_len);
+ &cks);
} else {
t = sci_scbrr_calc(s, baud, port->uartclk);
for (cks = 0; t >= 256 && cks <= 3; cks++)
--
1.9.1
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF |
| Message-ID | <qwCrp-4G9-31@gated-at.bofh.it> |
| In reply to | #1273368 |
Add the device node for the external SCIF_CLK.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
resp. external clock) for the Baud Rate Generator for External Clock
(BRG) to all SCIF and HSCIF device nodes.
This increases the range and accuracy of supported baud rates on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 74 ++++++++++++++++++++++----------
1 file changed, 52 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 53a2a8fb42b7480c..25900761cfde201e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -84,6 +84,14 @@
status = "disabled";
};
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -362,8 +370,10 @@
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
reg = <0 0xe6540000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 520>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -374,8 +384,10 @@
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
reg = <0 0xe6550000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 519>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -386,8 +398,10 @@
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
reg = <0 0xe6560000 0 96>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 518>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -398,8 +412,10 @@
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
reg = <0 0xe66a0000 0 96>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 517>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -410,8 +426,10 @@
compatible = "renesas,hscif-r8a7795", "renesas,hscif";
reg = <0 0xe66b0000 0 96>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 516>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -422,8 +440,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 207>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -434,8 +454,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 206>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -446,8 +468,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -458,8 +482,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 204>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -470,8 +496,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 203>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
@@ -482,8 +510,10 @@
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6f30000 0 64>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 202>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "int_clk", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
--
1.9.1
--
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-19 22:10 +0100 |
| Subject | Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF |
| Message-ID | <qwECR-6fX-1@gated-at.bofh.it> |
| In reply to | #1273377 |
Hi Geert,
Thank you for the patch.
On Thursday 19 November 2015 19:39:02 Geert Uytterhoeven wrote:
> Add the device node for the external SCIF_CLK.
> The presence of the SCIF_CLK crystal and its clock frequency depend on
> the actual board.
>
> Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
> resp. external clock) for the Baud Rate Generator for External Clock
> (BRG) to all SCIF and HSCIF device nodes.
>
> This increases the range and accuracy of supported baud rates on
> (H)SCIF.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 74 +++++++++++++++++++----------
> 1 file changed, 52 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index
> 53a2a8fb42b7480c..25900761cfde201e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -84,6 +84,14 @@
> status = "disabled";
> };
>
> + /* External SCIF clock - to be overridden by boards that provide it */
> + scif_clk: scif {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + status = "disabled";
> + };
I have mixed feelings about this. Defining an external clock that isn't
present on the board isn't very clean, even more so when the clock has such a
generic name. Wouldn't it be better to let board files define the clock when
they need it ? I know it would require board files to override the clocks and
clock-names property too. Maybe we need to extend the DTS syntax to allow
extending list properties instead of overriding them completely ?
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&gic>;
> @@ -362,8 +370,10 @@
> compatible = "renesas,hscif-r8a7795", "renesas,hscif";
> reg = <0 0xe6540000 0 96>;
> interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 520>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 520>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x31>, <&dmac1 0x30>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -374,8 +384,10 @@
> compatible = "renesas,hscif-r8a7795", "renesas,hscif";
> reg = <0 0xe6550000 0 96>;
> interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 519>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 519>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x33>, <&dmac1 0x32>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -386,8 +398,10 @@
> compatible = "renesas,hscif-r8a7795", "renesas,hscif";
> reg = <0 0xe6560000 0 96>;
> interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 518>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 518>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x35>, <&dmac1 0x34>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -398,8 +412,10 @@
> compatible = "renesas,hscif-r8a7795", "renesas,hscif";
> reg = <0 0xe66a0000 0 96>;
> interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 517>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 517>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac0 0x37>, <&dmac0 0x36>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -410,8 +426,10 @@
> compatible = "renesas,hscif-r8a7795", "renesas,hscif";
> reg = <0 0xe66b0000 0 96>;
> interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 516>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 516>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac0 0x39>, <&dmac0 0x38>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -422,8 +440,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6e60000 0 64>;
> interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 207>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 207>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x51>, <&dmac1 0x50>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -434,8 +454,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6e68000 0 64>;
> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 206>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 206>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x53>, <&dmac1 0x52>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -446,8 +468,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6e88000 0 64>;
> interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 310>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 310>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x13>, <&dmac1 0x12>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -458,8 +482,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6c50000 0 64>;
> interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 204>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 204>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac0 0x57>, <&dmac0 0x56>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -470,8 +496,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6c40000 0 64>;
> interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 203>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 203>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac0 0x59>, <&dmac0 0x58>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
> @@ -482,8 +510,10 @@
> compatible = "renesas,scif-r8a7795", "renesas,scif";
> reg = <0 0xe6f30000 0 64>;
> interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 202>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 202>,
> + <&cpg CPG_CORE R8A7795_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "int_clk", "scif_clk";
> dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
> dma-names = "tx", "rx";
> power-domains = <&cpg>;
--
Regards,
Laurent Pinchart
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| From | Geert Uytterhoeven <geert@linux-m68k.org> |
|---|---|
| Date | 2015-11-20 09:20 +0100 |
| Subject | Re: [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF |
| Message-ID | <qwP5f-4EO-13@gated-at.bofh.it> |
| In reply to | #1273500 |
Hi Laurent,
On Thu, Nov 19, 2015 at 10:07 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:39:02 Geert Uytterhoeven wrote:
>> Add the device node for the external SCIF_CLK.
>> The presence of the SCIF_CLK crystal and its clock frequency depend on
>> the actual board.
>>
>> Add the two optional clock sources (ZS_CLK and SCIF_CLK for the internal
>> resp. external clock) for the Baud Rate Generator for External Clock
>> (BRG) to all SCIF and HSCIF device nodes.
>>
>> This increases the range and accuracy of supported baud rates on
>> (H)SCIF.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 74 +++++++++++++++++++----------
>> 1 file changed, 52 insertions(+), 22 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index
>> 53a2a8fb42b7480c..25900761cfde201e 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -84,6 +84,14 @@
>> status = "disabled";
>> };
>>
>> + /* External SCIF clock - to be overridden by boards that provide it */
>> + scif_clk: scif {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <0>;
>> + status = "disabled";
>> + };
>
> I have mixed feelings about this. Defining an external clock that isn't
> present on the board isn't very clean, even more so when the clock has such a
We have precedence of optional external clocks (can_clk, audio_clk_*).
The SoC datasheet clearly calls it "scif_clk", so that makes it an ABI, IMHO.
> generic name. Wouldn't it be better to let board files define the clock when
> they need it ? I know it would require board files to override the clocks and
> clock-names property too. Maybe we need to extend the DTS syntax to allow
> extending list properties instead of overriding them completely ?
As scif_clk is shared between all (H)SCIF instances, that would mean overriding
the clock and clock-names for all of them, which is quite a tedious task.
Most boards seem to provide a SCIF_CLK, to allow having "perfect" standard
baud rates.
Combined all of the above, I think it's sufficiently generic to keep
it that way.
Note that it's different for (H)SCK: these are per-(H)SCIF inputs, and depend
even more on board layout. Adding individual zero-frequency clock nodes for
them would preclude e.g. connecting all (H)SCK inputs to the same crystal.
Hence I didn't add them, and you do have to override all clocks and
clock-names of a node if you want to add an (H)SCK clock input (been there,
done that for testing; long live DT overlays).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support |
| Message-ID | <qwCrp-4G9-33@gated-at.bofh.it> |
| In reply to | #1273368 |
Amend the DT bindings to include the optional clock sources for the Baud
Rate Generator for External Clock (BRG), as found on some SCIF variants
and on HSCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 8efc9b6f35637fbb..ae907e39b11c2a5a 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -46,6 +46,12 @@ Required properties:
On (H)SCI(F) and some SCIFA, an additional clock may be specified:
- "hsck" for the optional external clock input (on HSCIF),
- "sck" for the optional external clock input (on other variants).
+ On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
+ (some SCIF and HSCIF), additional clocks may be specified:
+ - "int_clk" for the optional internal clock source for the frequency
+ divider (typically the (AXI or SHwy) bus clock),
+ - "scif_clk" for the optional external clock source for the frequency
+ divider (SCIF_CLK).
Note: Each enabled SCIx UART should have an alias correctly numbered in the
"aliases" node.
--
1.9.1
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-19 21:30 +0100 |
| Subject | Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support |
| Message-ID | <qwE0a-5Mi-11@gated-at.bofh.it> |
| In reply to | #1273378 |
Hi Geert, Thank you for the patch. On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: > Amend the DT bindings to include the optional clock sources for the Baud > Rate Generator for External Clock (BRG), as found on some SCIF variants > and on HSCIF. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: devicetree@vger.kernel.org > --- > Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index > 8efc9b6f35637fbb..ae907e39b11c2a5a 100644 > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > @@ -46,6 +46,12 @@ Required properties: > On (H)SCI(F) and some SCIFA, an additional clock may be specified: > - "hsck" for the optional external clock input (on HSCIF), > - "sck" for the optional external clock input (on other variants). > + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) > + (some SCIF and HSCIF), additional clocks may be specified: > + - "int_clk" for the optional internal clock source for the frequency > + divider (typically the (AXI or SHwy) bus clock), Isn't this always the same clock as the SCIF functional clock ? > + - "scif_clk" for the optional external clock source for the frequency > + divider (SCIF_CLK). > > Note: Each enabled SCIx UART should have an alias correctly numbered in the > "aliases" node. -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Geert Uytterhoeven <geert@linux-m68k.org> |
|---|---|
| Date | 2015-11-19 21:50 +0100 |
| Subject | Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support |
| Message-ID | <qwEjw-5Tc-19@gated-at.bofh.it> |
| In reply to | #1273471 |
Hi Laurent,
On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
>> Amend the DT bindings to include the optional clock sources for the Baud
>> Rate Generator for External Clock (BRG), as found on some SCIF variants
>> and on HSCIF.
>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> @@ -46,6 +46,12 @@ Required properties:
>> On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> - "hsck" for the optional external clock input (on HSCIF),
>> - "sck" for the optional external clock input (on other variants).
>> + On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
>> + (some SCIF and HSCIF), additional clocks may be specified:
>> + - "int_clk" for the optional internal clock source for the frequency
>> + divider (typically the (AXI or SHwy) bus clock),
>
> Isn't this always the same clock as the SCIF functional clock ?
(On R-Car Gen2/3)
No, SCIF uses different parents for fck (p) and int_clk (zs).
HSCIF uses the same parents though (zs).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2015-11-19 22:20 +0100 |
| Subject | Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support |
| Message-ID | <qwEMx-6ku-19@gated-at.bofh.it> |
| In reply to | #1273488 |
Hi Geert, On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote: > On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: > > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: > >> Amend the DT bindings to include the optional clock sources for the Baud > >> Rate Generator for External Clock (BRG), as found on some SCIF variants > >> and on HSCIF. > >> > >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> > >> @@ -46,6 +46,12 @@ Required properties: > >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: > >> - "hsck" for the optional external clock input (on HSCIF), > >> - "sck" for the optional external clock input (on other variants). > >> > >> + On UARTs equipped with a Baud Rate Generator for External Clock > >> (BRG) > >> + (some SCIF and HSCIF), additional clocks may be specified: > >> + - "int_clk" for the optional internal clock source for the > >> frequency > >> + divider (typically the (AXI or SHwy) bus clock), > > > > Isn't this always the same clock as the SCIF functional clock ? > > (On R-Car Gen2/3) > > No, SCIF uses different parents for fck (p) and int_clk (zs). Right, my bad. Should we rename "int_clk" to something that makes it explicit that the clock is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We probably don't need to keep the _clk suffix as it's quite evident that a clock name refers to a clock. > HSCIF uses the same parents though (zs). -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Geert Uytterhoeven <geert@linux-m68k.org> |
|---|---|
| Date | 2015-11-20 09:00 +0100 |
| Subject | Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support |
| Message-ID | <qwOLU-4hH-13@gated-at.bofh.it> |
| In reply to | #1273508 |
Hi Laurent,
On Thu, Nov 19, 2015 at 10:13 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
>> >> Amend the DT bindings to include the optional clock sources for the Baud
>> >> Rate Generator for External Clock (BRG), as found on some SCIF variants
>> >> and on HSCIF.
>> >>
>> >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >>
>> >> @@ -46,6 +46,12 @@ Required properties:
>> >> On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> >> - "hsck" for the optional external clock input (on HSCIF),
>> >> - "sck" for the optional external clock input (on other variants).
>> >>
>> >> + On UARTs equipped with a Baud Rate Generator for External Clock
>> >> (BRG)
>> >> + (some SCIF and HSCIF), additional clocks may be specified:
>> >> + - "int_clk" for the optional internal clock source for the
>> >> frequency
>> >> + divider (typically the (AXI or SHwy) bus clock),
>> >
>> > Isn't this always the same clock as the SCIF functional clock ?
>>
>> (On R-Car Gen2/3)
>>
>> No, SCIF uses different parents for fck (p) and int_clk (zs).
>
> Right, my bad.
>
> Should we rename "int_clk" to something that makes it explicit that the clock
> is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We
> probably don't need to keep the _clk suffix as it's quite evident that a clock
> name refers to a clock.
The documentation always uses the SoC-specific explicit clock name (e.g. zs
s3d1, or clks), or just "internal clock", so I used "int_clk".
But I agree "int_brg" sounds better.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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| From | Geert Uytterhoeven <geert+renesas@glider.be> |
|---|---|
| Date | 2015-11-19 19:50 +0100 |
| Subject | [PATCH 04/25] serial: sh-sci: Grammar s/Get ... for/Get ... from/ |
| Message-ID | <qwCrp-4G9-37@gated-at.bofh.it> |
| In reply to | #1273368 |
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ae136a1632e6298d..676f9d1354943a1b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2640,7 +2640,7 @@ sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
if (!p)
return NULL;
- /* Get the line number for the aliases node. */
+ /* Get the line number from the aliases node. */
id = of_alias_get_id(np, "serial");
if (id < 0) {
dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
--
1.9.1
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