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[PATCH v12 0/3] Mediatek xHCI support

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  [PATCH v12 0/3] Mediatek xHCI support Chunfeng Yun <chunfeng.yun@mediatek.com> - 2015-11-17 10:20 +0100
    [PATCH v12 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun <chunfeng.yun@mediatek.com> - 2015-11-17 10:30 +0100
    Re: [PATCH v12 0/3] Mediatek xHCI support Mathias Nyman <mathias.nyman@intel.com> - 2015-11-20 12:20 +0100
      Re: [PATCH v12 0/3] Mediatek xHCI support chunfeng yun <chunfeng.yun@mediatek.com> - 2015-11-21 03:50 +0100

#1270995 — [PATCH v12 0/3] Mediatek xHCI support

From 577f68d9c0ca1531d5f9cae0dcbea2ba116c8551 Mon Sep 17 00:00:00 2001
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
Date: Tue, 17 Nov 2015 17:09:05 +0800
Subject: [PATCH v12 0/3] Mediatek xHCI support

The patch supports MediaTek's xHCI controller.

There are some differences from xHCI spec:
1. The interval is specified in 250 * 8ns increments for Interrupt Moderation
Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times as
much as that defined in xHCI spec.

2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
number of packets that remain to be transferred for a TD after processing all
Max packets in all previous TRBs,that means don't include the current TRB's,
but in xHCI spec it includes the current ones.

3. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK
architecture defines some extra SW scheduling parameters for HW. According to
these parameters provided by SW, the xHC can easily decide whether a
synchronous endpoint should be scheduled in a specific uFrame. The extra SW
scheduling parameters are put into reserved DWs in Slot and Endpoint Context.
And a bandwidth scheduler algorithm is added to support such feature.

A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
supports two usb2.0 ports and one usb3.0 port.

Change in v12:
1. change LPM as optional feature

Change in v11:
1. remove some dummy header files
2. call xhci_mtk_sch_exit() when primary hcd register fail
3. use false instead of 0 for the second parameter of device_init_wakeup();

Change in v10:
1. simplify clock stability checks
2. put MTK xHCI configuration from xhci_mtk_probe() to xhci_mtk_setup()

Change in v9:
1. fix up issue of FS out-iso when use single-TT hub
2. improve RX sensitivity
3. remove udelay(800) called by phy_instance_power_on/off

Change in v8:
1. use struct overlay for ippc register
2. change usb wakeup as optional feature
3. add TDS quirk into unified TDS calculation function

Change in v7:
1. remove xHCI timing setting which only for FPGA
2. revise xHCI scheduler algorithms
3. replace "usb" by "USB" in xHCI binding file

Change in v6:
1. get register base address of port in probe instead of of_xlate
2. enable clock in phy_init instead of probe

Change in v5:
1. descripte more exactly for each specifiers in xHCI binding
2. make use of new multi-phy feature for phy driver

Change in v4:
1. descripte more exactly for each specifiers in binding file
2. use BIT() to define a bit mask macro

Change in v3:
1. implement generic phy
2. move opperations of IPPC and wakeup from phy driver to xHCI driver
3. seperate quirk functions into a single C file to fix up dependence issue

Change in v2:
1. Rebase to 4.2-rc1
2. Remove probe phy before add usb_hcd patch from this series due to 4.2-rc1
   already fix this issue
3. add xhci mac clocks
4. add suspend/resume
5. support remote wakeup


Chunfeng Yun (3):
  dt-bindings: Add a binding for Mediatek xHCI host controller
  xhci: mediatek: support MTK xHCI host controller
  arm64: dts: mediatek: add xHCI & usb phy for mt8173

Chunfeng Yun (3):
  dt-bindings: Add a binding for Mediatek xHCI host controller
  xhci: mediatek: support MTK xHCI host controller
  arm64: dts: mediatek: add xHCI & usb phy for mt8173

 .../devicetree/bindings/usb/mt8173-xhci.txt        |  51 ++
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts        |  16 +
 arch/arm64/boot/dts/mediatek/mt8173.dtsi           |  42 ++
 drivers/usb/host/Kconfig                           |   9 +
 drivers/usb/host/Makefile                          |   4 +
 drivers/usb/host/xhci-mtk-sch.c                    | 415 +++++++++++
 drivers/usb/host/xhci-mtk.c                        | 763 +++++++++++++++++++++
 drivers/usb/host/xhci-mtk.h                        | 162 +++++
 drivers/usb/host/xhci-ring.c                       |  16 +-
 drivers/usb/host/xhci.c                            |  19 +-
 drivers/usb/host/xhci.h                            |   1 +
 11 files changed, 1492 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 create mode 100644 drivers/usb/host/xhci-mtk-sch.c
 create mode 100644 drivers/usb/host/xhci-mtk.c
 create mode 100644 drivers/usb/host/xhci-mtk.h

--
1.8.1.1.dirty



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#1270998 — [PATCH v12 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173

add xHCI and phy drivers for MT8173-EVB

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 16 +++++++++++
 arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 42 +++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 811cb76..9b1482a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -13,6 +13,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "mt8173.dtsi"
 
 / {
@@ -32,6 +33,15 @@
 	};
 
 	chosen { };
+
+	usb_p1_vbus: regulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &i2c1 {
@@ -408,3 +418,9 @@
 &uart0 {
 	status = "okay";
 };
+
+&usb30 {
+	vusb33-supply = <&mt6397_vusb_reg>;
+	vbus-supply = <&usb_p1_vbus>;
+	mediatek,wakeup-src = <1>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4dd5f93..c1fd275 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/mt8173-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8173-power.h>
 #include <dt-bindings/reset-controller/mt8173-resets.h>
 #include "mt8173-pinfunc.h"
@@ -510,6 +511,47 @@
 			status = "disabled";
 		};
 
+		usb30: usb@11270000 {
+			compatible = "mediatek,mt8173-xhci";
+			reg = <0 0x11270000 0 0x1000>,
+			      <0 0x11280700 0 0x0100>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+			clocks = <&topckgen CLK_TOP_USB30_SEL>,
+				 <&pericfg CLK_PERI_USB0>,
+				 <&pericfg CLK_PERI_USB1>;
+			clock-names = "sys_ck",
+				      "wakeup_deb_p0",
+				      "wakeup_deb_p1";
+			phys = <&phy_port0 PHY_TYPE_USB3>,
+			       <&phy_port1 PHY_TYPE_USB2>;
+			mediatek,syscon-wakeup = <&pericfg>;
+			status = "okay";
+		};
+
+		u3phy: usb-phy@11290000 {
+			compatible = "mediatek,mt8173-u3phy";
+			reg = <0 0x11290000 0 0x800>;
+			clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+			clock-names = "u3phya_ref";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "okay";
+
+			phy_port0: port@11290800 {
+				reg = <0 0x11290800 0 0x800>;
+				#phy-cells = <1>;
+				status = "okay";
+			};
+
+			phy_port1: port@11291000 {
+				reg = <0 0x11291000 0 0x800>;
+				#phy-cells = <1>;
+				status = "okay";
+			};
+		};
+
 		mmsys: clock-controller@14000000 {
 			compatible = "mediatek,mt8173-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
-- 
1.8.1.1.dirty

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#1273988

On 17.11.2015 11:18, Chunfeng Yun wrote:
>  From 577f68d9c0ca1531d5f9cae0dcbea2ba116c8551 Mon Sep 17 00:00:00 2001
> From: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Date: Tue, 17 Nov 2015 17:09:05 +0800
> Subject: [PATCH v12 0/3] Mediatek xHCI support
>
> The patch supports MediaTek's xHCI controller.
>
> There are some differences from xHCI spec:
> 1. The interval is specified in 250 * 8ns increments for Interrupt Moderation
> Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times as
> much as that defined in xHCI spec.
>
> 2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
> number of packets that remain to be transferred for a TD after processing all
> Max packets in all previous TRBs,that means don't include the current TRB's,
> but in xHCI spec it includes the current ones.
>
> 3. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK
> architecture defines some extra SW scheduling parameters for HW. According to
> these parameters provided by SW, the xHC can easily decide whether a
> synchronous endpoint should be scheduled in a specific uFrame. The extra SW
> scheduling parameters are put into reserved DWs in Slot and Endpoint Context.
> And a bandwidth scheduler algorithm is added to support such feature.
>
> A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
> supports two usb2.0 ports and one usb3.0 port.
>

Added to my tree, I'll send it forward to Greg shortly

Fixed the documentation "wakeup_deb_p0" -> "wakeup_deb_p1" typo as well

-Mathias  

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#1274596

Hi,
On Fri, 2015-11-20 at 13:20 +0200, Mathias Nyman wrote:
> On 17.11.2015 11:18, Chunfeng Yun wrote:
> >  From 577f68d9c0ca1531d5f9cae0dcbea2ba116c8551 Mon Sep 17 00:00:00 2001
> > From: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > Date: Tue, 17 Nov 2015 17:09:05 +0800
> > Subject: [PATCH v12 0/3] Mediatek xHCI support
> >
> > The patch supports MediaTek's xHCI controller.
> >
> > There are some differences from xHCI spec:
> > 1. The interval is specified in 250 * 8ns increments for Interrupt Moderation
> > Interval(IMODI) of the Interrupter Moderation(IMOD) register, it is 8 times as
> > much as that defined in xHCI spec.
> >
> > 2. For the value of TD Size in Normal TRB, MTK's xHCI controller defines a
> > number of packets that remain to be transferred for a TD after processing all
> > Max packets in all previous TRBs,that means don't include the current TRB's,
> > but in xHCI spec it includes the current ones.
> >
> > 3. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK
> > architecture defines some extra SW scheduling parameters for HW. According to
> > these parameters provided by SW, the xHC can easily decide whether a
> > synchronous endpoint should be scheduled in a specific uFrame. The extra SW
> > scheduling parameters are put into reserved DWs in Slot and Endpoint Context.
> > And a bandwidth scheduler algorithm is added to support such feature.
> >
> > A usb3.0 phy driver is also added which used by mt65xx SoCs platform, it
> > supports two usb2.0 ports and one usb3.0 port.
> >
> 
> Added to my tree, I'll send it forward to Greg shortly
> 
> Fixed the documentation "wakeup_deb_p0" -> "wakeup_deb_p1" typo as well
Thank you very much.
> 
> -Mathias  
> 


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