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[RFC] perf x86 intel: Question about pebs_data_source data

Started byJiri Olsa <jolsa@redhat.com>
First post2015-11-09 16:40 +0100
Last post2015-11-14 20:50 +0100
Articles 3 — 3 participants

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  [RFC] perf x86 intel: Question about pebs_data_source data Jiri Olsa <jolsa@redhat.com> - 2015-11-09 16:40 +0100
    Re: [RFC] perf x86 intel: Question about pebs_data_source data Stephane Eranian <eranian@google.com> - 2015-11-10 23:50 +0100
    Re: [RFC] perf x86 intel: Question about pebs_data_source data Andi Kleen <andi@firstfloor.org> - 2015-11-14 20:50 +0100

#1265766 — [RFC] perf x86 intel: Question about pebs_data_source data

FromJiri Olsa <jolsa@redhat.com>
Date2015-11-09 16:40 +0100
Subject[RFC] perf x86 intel: Question about pebs_data_source data
Message-ID<qsWI2-8g3-13@gated-at.bofh.it>
hi,
I was checking with SDM (September 2015) and I'd like if you
guys could help me with understanding of following array elements

I'm reffering to Table 18-19. Data Source Encoding for Load Latency Record

 - element 5
   SDM says:

   05H L3 HIT. Local or Remote home requests that hit the L3 cache and was
   serviced by another processor core with a cross core snoop where no modified
   copies were found. (clean).

   and we have L3 SNOOP MISS:
     OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */

   while the SDM indicates HIT

 - element 6
   SDM says:

   L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced
   by another processor core with a cross core snoop where modified copies were
   found. (HITM).
  
   and we have L3 SNOOP HIT:
     OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */

   while the SDM indicates HITM

I'm probably misunderstanding SDM (wouldn't be the first time) what do I miss?

thanks for comments,
jirka


---
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 5db1c7755548..000ab82d09e7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -57,8 +57,8 @@ static const u64 pebs_data_source[] = {
 	OP_LH | P(LVL, LFB) | P(SNOOP, NONE),	/* 0x02: LFB hit */
 	OP_LH | P(LVL, L2)  | P(SNOOP, NONE),	/* 0x03: L2 hit */
 	OP_LH | P(LVL, L3)  | P(SNOOP, NONE),	/* 0x04: L3 hit */
-	OP_LH | P(LVL, L3)  | P(SNOOP, MISS),	/* 0x05: L3 hit, snoop miss */
-	OP_LH | P(LVL, L3)  | P(SNOOP, HIT),	/* 0x06: L3 hit, snoop hit */
+	OP_LH | P(LVL, L3)  | P(SNOOP, HIT),	/* 0x05: L3 hit, snoop hit */
+	OP_LH | P(LVL, L3)  | P(SNOOP, HITM),	/* 0x06: L3 hit, snoop hitm */
 	OP_LH | P(LVL, L3)  | P(SNOOP, HITM),	/* 0x07: L3 hit, snoop hitm */
 	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
 	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
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#1266831

FromStephane Eranian <eranian@google.com>
Date2015-11-10 23:50 +0100
Message-ID<qtpTH-2Jl-11@gated-at.bofh.it>
In reply to#1265766
On Mon, Nov 9, 2015 at 7:36 AM, Jiri Olsa <jolsa@redhat.com> wrote:
>
> hi,
> I was checking with SDM (September 2015) and I'd like if you
> guys could help me with understanding of following array elements
>
> I'm reffering to Table 18-19. Data Source Encoding for Load Latency Record
>
>  - element 5
>    SDM says:
>
>    05H L3 HIT. Local or Remote home requests that hit the L3 cache and was
>    serviced by another processor core with a cross core snoop where no modified
>    copies were found. (clean).
>
>    and we have L3 SNOOP MISS:
>      OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
>
>    while the SDM indicates HIT
>
>  - element 6
>    SDM says:
>
>    L3 HIT. Local or Remote home requests that hit the L3 cache and was serviced
>    by another processor core with a cross core snoop where modified copies were
>    found. (HITM).
>
>    and we have L3 SNOOP HIT:
>      OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
>
>    while the SDM indicates HITM
>
I seem to recall there was something incorrect in the SDM and that's
why I had it
this way. But it would be useful to double-check with Intel again. Andi?


> I'm probably misunderstanding SDM (wouldn't be the first time) what do I miss?
>
> thanks for comments,
> jirka
>
>
> ---
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index 5db1c7755548..000ab82d09e7 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -57,8 +57,8 @@ static const u64 pebs_data_source[] = {
>         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
>         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
>         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
> -       OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
> -       OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
> +       OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x05: L3 hit, snoop hit */
> +       OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x06: L3 hit, snoop hitm */
>         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
>         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
>         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
--
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#1269531

FromAndi Kleen <andi@firstfloor.org>
Date2015-11-14 20:50 +0100
Message-ID<quOZH-8dy-1@gated-at.bofh.it>
In reply to#1265766
> I'm probably misunderstanding SDM (wouldn't be the first time) what do I miss?

Hi Jiri,

We checked the history, and it appears the SDM was not updated when the
definition of the bits changed (around Sandy Bridge, possibly Westmere).
So perf is correct for newer CPUs, but not for older, and we have to fork
the table. I'll work on a patch and also see that the SDM gets fixed.

-Andi
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