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Groups > linux.kernel > #1265356 > unrolled thread
| Started by | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| First post | 2015-11-09 06:30 +0100 |
| Last post | 2015-11-16 02:10 +0100 |
| Articles | 13 — 3 participants |
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[PATCH v5 00/11] exynos-ufs: add support for Exynos Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 06/11] scsi: ufs: add quirk to enable host controller without hce Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 01/11] Documentation: samsung-phy: Add dt bindings for UFS Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 03/11] scsi: ufs: add quirk to contain unconformable utrd field Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:30 +0100
[PATCH v5 08/11] scsi: ufs: add add specific callback for hibern8 Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:40 +0100
[PATCH v5 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:40 +0100
[PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:40 +0100
Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller Rob Herring <robh@kernel.org> - 2015-11-09 17:30 +0100
Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-10 09:40 +0100
[PATCH v5 07/11] scsi: ufs: add specific callback for nexus type Alim Akhtar <alim.akhtar@samsung.com> - 2015-11-09 06:40 +0100
Re: [PATCH v5 00/11] exynos-ufs: add support for Exynos Alim Akhtar <alim.akhtar@gmail.com> - 2015-11-16 02:10 +0100
| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 00/11] exynos-ufs: add support for Exynos |
| Message-ID | <qsNbI-292-3@gated-at.bofh.it> |
This patch-set introduces UFS (Universal Flash Storage) host support
for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver.
And it also contains some quirks handling for Exynos.
NOTE: ** This series has a dependency on [4]. **
-Changes since v4:
* Removed platform specific PHY ops as suggested by Kishon
* Rebased on the top of Yaniv Gardi's work [4]
* make use of newly introduce ufshcd_{get,set}_variant
* other small changes and improvements.
* rebased on the top of linux next-20151109
-Changes since v3:
* Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
* Restructure the driver to make it as a platform driver, rebased on top of [4].
* Addressed review comments from Arnd Bergmann[5].
* Other misc changes and improvements.
-Changes since v2:
* Addressed review comments from Kishon[1] and Rob Herring [2]
* Splited ufs dt binding documetation from ufs driver patch
-Changes since v1:
* Addressed review comments from Alexey[3] and various review comments from Amit.
* Updated email id of Seungwon as his samsung id is void now.
* Added ufs platform data
[1]-> https://lkml.org/lkml/2015/9/18/29
[2]-> https://lkml.org/lkml/2015/9/21/668
[3]-> https://lkml.org/lkml/2015/8/23/124
[4]-> https://lkml.org/lkml/2015/10/28/271
[5]-> https://lkml.org/lkml/2015/10/1/402
This patch set is tested on exynos7-espresso board.
Alim Akhtar (1):
Documentation: samsung-phy: Add dt bindings for UFS
Seungwon Jeon (10):
phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
scsi: ufs: add quirk to contain unconformable utrd field
scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
scsi: ufs: add quirk not to allow reset of interrupt aggregation
scsi: ufs: add quirk to enable host controller without hce
scsi: ufs: add specific callback for nexus type
scsi: ufs: add add specific callback for hibern8
scsi: ufs: make ufshcd_config_pwr_mode of non-static func
Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
controller
scsi: ufs-exynos: add UFS host support for Exynos SoCs
.../devicetree/bindings/phy/samsung-phy.txt | 22 +
.../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos-ufs.c | 241 ++++
drivers/phy/phy-exynos-ufs.h | 85 ++
drivers/phy/phy-exynos7-ufs.h | 89 ++
drivers/scsi/ufs/Kconfig | 12 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
drivers/scsi/ufs/ufs-exynos.c | 1304 ++++++++++++++++++++
drivers/scsi/ufs/ufs-exynos.h | 247 ++++
drivers/scsi/ufs/ufshcd.c | 168 ++-
drivers/scsi/ufs/ufshcd.h | 54 +
drivers/scsi/ufs/ufshci.h | 26 +-
drivers/scsi/ufs/unipro.h | 47 +
include/linux/phy/phy-exynos-ufs.h | 85 ++
18 files changed, 2647 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
create mode 100644 drivers/scsi/ufs/ufs-exynos.c
create mode 100644 drivers/scsi/ufs/ufs-exynos.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
--
1.7.10.4
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 06/11] scsi: ufs: add quirk to enable host controller without hce |
| Message-ID | <qsNbI-292-7@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
Some host controller doesn't support host controller enable via HCE.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 75 +++++++++++++++++++++++++++++++++++++++++++--
drivers/scsi/ufs/ufshcd.h | 5 +++
2 files changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ca7483cd899e..e8b96ec65987 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2107,6 +2107,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
}
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_RESET;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_err(hba->dev,
+ "dme-reset: error code %d\n", ret);
+
+ return ret;
+}
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
{
@@ -2642,7 +2688,7 @@ out:
}
/**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
* @hba: per adapter instance
*
* The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
*
* Returns 0 on success, non-zero value on failure
*/
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
{
int retry;
@@ -2715,6 +2761,31 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
}
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int ret;
+
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+ ufshcd_set_link_off(hba);
+ ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+ ret = ufshcd_dme_reset(hba);
+ if (!ret) {
+ ret = ufshcd_dme_enable(hba);
+ if (!ret)
+ ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
+ if (ret)
+ dev_err(hba->dev,
+ "Host controller enable failed with non-hce\n");
+ }
+ } else {
+ ret = ufshcd_hba_execute_hce(hba);
+ }
+
+ return ret;
+}
static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
{
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 4ae32e9316de..500e137bf68a 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -485,6 +485,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR UFS_BIT(8)
+ /*
+ * This quirks needs to be enabled if host controller cannot be
+ * enabled via HCE register.
+ */
+ #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks; /* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 01/11] Documentation: samsung-phy: Add dt bindings for UFS |
| Message-ID | <qsNbI-292-13@gated-at.bofh.it> |
| In reply to | #1265356 |
Adds exynos UFS PHY device tree bindings information.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../devicetree/bindings/phy/samsung-phy.txt | 22 ++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 0289d3b07853..565200d72e91 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -177,3 +177,25 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos7 soc series UFS PHY Controller
+---------------------------------------------
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible : compatible should be set to "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set
+- reg-names : reg name(s) must be 'phy-pma'
+- #phy-cells : must be zero
+- samsung,pmu-syscon : a phandle to the PMU system controller, no arguments
+
+Example:
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
--
1.7.10.4
--
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 02/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC |
| Message-ID | <qsNbI-292-11@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos-ufs.c | 241 ++++++++++++++++++++++++++++++++++++
drivers/phy/phy-exynos-ufs.h | 85 +++++++++++++
drivers/phy/phy-exynos7-ufs.h | 89 +++++++++++++
include/linux/phy/phy-exynos-ufs.h | 85 +++++++++++++
6 files changed, 508 insertions(+)
create mode 100644 drivers/phy/phy-exynos-ufs.c
create mode 100644 drivers/phy/phy-exynos-ufs.h
create mode 100644 drivers/phy/phy-exynos7-ufs.h
create mode 100644 include/linux/phy/phy-exynos-ufs.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859dd035..7d38a92e0297 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -389,4 +389,11 @@ config PHY_CYGNUS_PCIE
Enable this to support the Broadcom Cygnus PCIe PHY.
If unsure, say N.
+config PHY_EXYNOS_UFS
+ tristate "EXYNOS SoC series UFS PHY driver"
+ depends on OF && ARCH_EXYNOS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a81aa5..9bec4d1a89e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_EXYNOS_UFS) += phy-exynos-ufs.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000000000000..cb1aeaa3d4eb
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,241 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <essuuj@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-exynos-ufs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+ for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->id; (cfg)++)
+
+#define PHY_DEF_LANE_CNT 1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+ const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+ enum {LANE_0, LANE_1}; /* lane index */
+
+ switch (lane) {
+ case LANE_0:
+ writel(cfg->val, (phy)->reg_pma + cfg->off_0);
+ break;
+ case LANE_1:
+ if (cfg->id == PHY_TRSV_BLK)
+ writel(cfg->val, (phy)->reg_pma + cfg->off_1);
+ break;
+ }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+ if (IS_PWR_MODE_ANY(desc))
+ return true;
+
+ if (IS_PWR_MODE_HS(required_pwr) && IS_PWR_MODE_HS_ANY(desc))
+ return true;
+
+ if (COMP_PWR_MODE(required_pwr, desc))
+ return true;
+
+ if (COMP_PWR_MODE_MD(required_pwr, desc) &&
+ COMP_PWR_MODE_GEAR(required_pwr, desc) &&
+ COMP_PWR_MODE_SER(required_pwr, desc))
+ return true;
+
+ return false;
+}
+
+int exynos_ufs_phy_calibrate(struct phy *phy,
+ enum phy_cfg_tag tag, u8 pwr)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ struct exynos_ufs_phy_cfg **cfgs = ufs_phy->cfg;
+ const struct exynos_ufs_phy_cfg *cfg;
+ int i;
+
+ if (unlikely(tag < CFG_PRE_INIT || tag >= CFG_TAG_MAX)) {
+ dev_err(ufs_phy->dev, "invalid phy config index %d\n", tag);
+ return -EINVAL;
+ }
+
+ cfg = cfgs[tag];
+ if (!cfg)
+ goto out;
+
+ for_each_phy_cfg(cfg) {
+ for_each_phy_lane(ufs_phy, i) {
+ if (match_cfg_to_pwr_mode(cfg->desc, pwr))
+ exynos_ufs_phy_config(ufs_phy, cfg, i);
+ }
+ }
+
+out:
+ return 0;
+}
+
+void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+
+ ufs_phy->lane_cnt = lane_cnt;
+}
+
+int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy)
+{
+ struct exynos_ufs_phy *ufs_phy = get_exynos_ufs_phy(phy);
+ const unsigned int timeout_us = 100000;
+ const unsigned int sleep_us = 10;
+ u32 val;
+ int err;
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
+ val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy pll lock acquisition %d\n", err);
+ goto out;
+ }
+
+ err = readl_poll_timeout(
+ ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy cdr lock acquisition %d\n", err);
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+static int exynos_ufs_phy_power_on(struct phy *phy)
+{
+ struct exynos_ufs_phy *_phy = get_exynos_ufs_phy(phy);
+
+ exynos_ufs_phy_ctrl_isol(_phy, false);
+ return 0;
+}
+
+static int exynos_ufs_phy_power_off(struct phy *phy)
+{
+ struct exynos_ufs_phy *_phy = get_exynos_ufs_phy(phy);
+
+ exynos_ufs_phy_ctrl_isol(_phy, true);
+ return 0;
+}
+
+static struct phy_ops exynos_ufs_phy_ops = {
+ .power_on = exynos_ufs_phy_power_on,
+ .power_off = exynos_ufs_phy_power_off,
+}
+;
+static const struct of_device_id exynos_ufs_phy_match[];
+
+static int exynos_ufs_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ const struct of_device_id *match;
+ struct exynos_ufs_phy *phy;
+ struct phy *gen_phy;
+ struct phy_provider *phy_provider;
+ const struct exynos_ufs_phy_drvdata *drvdata;
+ int err = 0;
+
+ match = of_match_node(exynos_ufs_phy_match, dev->of_node);
+ if (!match) {
+ err = -EINVAL;
+ dev_err(dev, "failed to get match_node\n");
+ goto out;
+ }
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy-pma");
+ phy->reg_pma = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->reg_pma)) {
+ err = PTR_ERR(phy->reg_pma);
+ goto out;
+ }
+
+ phy->reg_pmu = syscon_regmap_lookup_by_phandle(
+ dev->of_node, "samsung,pmu-syscon");
+ if (IS_ERR(phy->reg_pmu)) {
+ err = PTR_ERR(phy->reg_pmu);
+ dev_err(dev, "failed syscon remap for pmu\n");
+ goto out;
+ }
+
+ gen_phy = devm_phy_create(dev, NULL, &exynos_ufs_phy_ops);
+ if (IS_ERR(gen_phy)) {
+ err = PTR_ERR(gen_phy);
+ dev_err(dev, "failed to create PHY for ufs-phy\n");
+ goto out;
+ }
+
+ drvdata = match->data;
+ phy->dev = dev;
+ phy->drvdata = drvdata;
+ phy->cfg = (struct exynos_ufs_phy_cfg **)drvdata->cfg;
+ phy->isol = &drvdata->isol;
+ phy->lane_cnt = PHY_DEF_LANE_CNT;
+
+ phy_set_drvdata(gen_phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ err = PTR_ERR(phy_provider);
+ dev_err(dev, "failed to register phy-provider\n");
+ goto out;
+ }
+out:
+ return err;
+}
+
+static const struct of_device_id exynos_ufs_phy_match[] = {
+ {
+ .compatible = "samsung,exynos7-ufs-phy",
+ .data = &exynos7_ufs_phy,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos_ufs_phy_match);
+
+static struct platform_driver exynos_ufs_phy_driver = {
+ .probe = exynos_ufs_phy_probe,
+ .driver = {
+ .name = "exynos-ufs-phy",
+ .of_match_table = exynos_ufs_phy_match,
+ },
+};
+module_platform_driver(exynos_ufs_phy_driver);
+MODULE_DESCRIPTION("EXYNOS SoC UFS PHY Driver");
+MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-exynos-ufs.h b/drivers/phy/phy-exynos-ufs.h
new file mode 100644
index 000000000000..820d879f393c
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.h
@@ -0,0 +1,85 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <essuuj@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef _PHY_EXYNOS_UFS_
+#define _PHY_EXYNOS_UFS_
+
+#define PHY_COMN_BLK 1
+#define PHY_TRSV_BLK 2
+#define END_UFS_PHY_CFG { 0 }
+#define PHY_TRSV_CH_OFFSET 0x30
+#define PHY_APB_ADDR(off) ((off) << 2)
+
+#define PHY_COMN_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = 0, \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_COMN_BLK, \
+}
+
+#define PHY_TRSV_REG_CFG(o, v, d) { \
+ .off_0 = PHY_APB_ADDR((o)), \
+ .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
+ .val = (v), \
+ .desc = (d), \
+ .id = PHY_TRSV_BLK, \
+}
+
+/* UFS PHY registers */
+#define PHY_PLL_LOCK_STATUS 0x1e
+#define PHY_CDR_LOCK_STATUS 0x5e
+
+#define PHY_PLL_LOCK_BIT BIT(5)
+#define PHY_CDR_LOCK_BIT BIT(4)
+
+struct exynos_ufs_phy_cfg {
+ u32 off_0;
+ u32 off_1;
+ u32 val;
+ u8 desc;
+ u8 id;
+};
+
+struct exynos_ufs_phy_drvdata {
+ const struct exynos_ufs_phy_cfg **cfg;
+ struct pmu_isol {
+ u32 offset;
+ u32 mask;
+ u32 en;
+ } isol;
+};
+
+struct exynos_ufs_phy {
+ struct device *dev;
+ void __iomem *reg_pma;
+ struct regmap *reg_pmu;
+ const struct exynos_ufs_phy_drvdata *drvdata;
+ struct exynos_ufs_phy_cfg **cfg;
+ const struct pmu_isol *isol;
+ u8 lane_cnt;
+};
+
+static inline struct exynos_ufs_phy *get_exynos_ufs_phy(struct phy *phy)
+{
+ return (struct exynos_ufs_phy *)phy_get_drvdata(phy);
+}
+
+static inline void exynos_ufs_phy_ctrl_isol(
+ struct exynos_ufs_phy *phy, u32 isol)
+{
+ regmap_update_bits(phy->reg_pmu, phy->isol->offset,
+ phy->isol->mask, isol ? 0 : phy->isol->en);
+}
+
+#include "phy-exynos7-ufs.h"
+
+#endif /* _PHY_EXYNOS_UFS_ */
diff --git a/drivers/phy/phy-exynos7-ufs.h b/drivers/phy/phy-exynos7-ufs.h
new file mode 100644
index 000000000000..6cd29d7fb200
--- /dev/null
+++ b/drivers/phy/phy-exynos7-ufs.h
@@ -0,0 +1,89 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-exynos-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct exynos_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct exynos_ufs_phy_cfg exynos7_post_init_cfg[] = {
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct exynos_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+ /* Setting order: 1st(0x16, 2nd(0x15) */
+ PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+ PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
+ PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
+ PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
+ END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B atfer PMC */
+static const struct exynos_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
+ PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG
+};
+
+static const struct exynos_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = exynos7_pre_init_cfg,
+ [CFG_POST_INIT] = exynos7_post_init_cfg,
+ [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
+ [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
+};
+
+static struct exynos_ufs_phy_drvdata exynos7_ufs_phy = {
+ .cfg = exynos7_ufs_phy_cfgs,
+ .isol = {
+ .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
+ .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
+ .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
+ },
+};
+
+#endif /* _PHY_EXYNOS7_UFS_H_ */
diff --git a/include/linux/phy/phy-exynos-ufs.h b/include/linux/phy/phy-exynos-ufs.h
new file mode 100644
index 000000000000..304df68fb9be
--- /dev/null
+++ b/include/linux/phy/phy-exynos-ufs.h
@@ -0,0 +1,85 @@
+/*
+ * phy-exynos-ufs.h - Header file for the UFS PHY of Exynos SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon <essuuj@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _PHY_EXYNOS_UFS_H_
+#define _PHY_EXYNOS_UFS_H_
+
+#include "phy.h"
+
+/* PHY calibration point */
+enum phy_cfg_tag {
+ CFG_PRE_INIT = 0,
+ CFG_POST_INIT = 1,
+ CFG_PRE_PWR_HS = 2,
+ CFG_POST_PWR_HS = 3,
+ CFG_TAG_MAX,
+};
+
+/* description for PHY calibration */
+enum {
+ /* applicable to any */
+ PWR_DESC_ANY = 0,
+ /* mode */
+ PWR_DESC_PWM = 1,
+ PWR_DESC_HS = 2,
+ /* series */
+ PWR_DESC_SER_A = 1,
+ PWR_DESC_SER_B = 2,
+ /* gear */
+ PWR_DESC_G1 = 1,
+ PWR_DESC_G2 = 2,
+ PWR_DESC_G3 = 3,
+ PWR_DESC_G4 = 4,
+ PWR_DESC_G5 = 5,
+ PWR_DESC_G6 = 6,
+ PWR_DESC_G7 = 7,
+ /* field mask */
+ MD_MASK = 0x3,
+ SR_MASK = 0x3,
+ GR_MASK = 0x7,
+};
+
+#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
+#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
+ (((s) & SR_MASK) << 2) | PWR_DESC_HS)
+#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
+#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
+#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
+#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
+#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
+#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
+#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_HS)
+#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_PWM)
+#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
+ PWR_DESC_ANY, PWR_DESC_ANY)
+#define IS_PWR_MODE_HS(d) (((d) & MD_MASK) == PWR_DESC_HS)
+#define IS_PWR_MODE_PWM(d) (((d) & MD_MASK) == PWR_DESC_PWM)
+#define IS_PWR_MODE_ANY(d) ((d) == PWR_MODE_ANY)
+#define IS_PWR_MODE_HS_ANY(d) ((d) == PWR_MODE_HS_ANY)
+#define COMP_PWR_MODE(a, b) ((a) == (b))
+#define COMP_PWR_MODE_GEAR(a, b) ((((a) >> 4) & GR_MASK) == \
+ (((b) >> 4) & GR_MASK))
+#define COMP_PWR_MODE_SER(a, b) ((((a) >> 2) & SR_MASK) == \
+ (((b) >> 2) & SR_MASK))
+#define COMP_PWR_MODE_MD(a, b) (((a) & MD_MASK) == ((b) & MD_MASK))
+
+int exynos_ufs_phy_calibrate(struct phy *phy, enum phy_cfg_tag tag, u8 pwr);
+void exynos_ufs_phy_set_lane_cnt(struct phy *phy, u8 lane_cnt);
+int exynos_ufs_phy_wait_for_lock_acq(struct phy *phy);
+
+#endif /* _PHY_EXYNOS_UFS_H_ */
--
1.7.10.4
--
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 04/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr |
| Message-ID | <qsNbI-292-17@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 21 +++++++++++++++++++--
drivers/scsi/ufs/ufshcd.h | 5 +++++
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 587a9c8fbfe9..2b16eb363203 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -356,7 +356,24 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
*/
static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
{
- ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos),
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+ if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+ ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+ else
+ ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
}
/**
@@ -3685,7 +3702,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
goto out;
spin_lock_irqsave(hba->host->host_lock, flags);
- ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+ ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 6cd542a803d5..d625d01110b0 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -474,6 +474,11 @@ struct ufs_hba {
*/
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRD UFS_BIT(6)
+ /*
+ * Cleaer handling for transfer/task request list is just opposite.
+ */
+ #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR UFS_BIT(7)
+
unsigned int quirks; /* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
--
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[toc] | [prev] | [next] | [standalone]
| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:30 +0100 |
| Subject | [PATCH v5 03/11] scsi: ufs: add quirk to contain unconformable utrd field |
| Message-ID | <qsNbI-292-15@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 28 +++++++++++++++++++++-------
drivers/scsi/ufs/ufshcd.h | 7 +++++++
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 131c72038bf8..587a9c8fbfe9 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
*
* Returns 0 in case of success, non-zero value in case of failure
*/
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
{
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
if (sg_segments) {
- lrbp->utr_descriptor_ptr->prd_table_length =
- cpu_to_le16((u16) (sg_segments));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16)(sg_segments *
+ sizeof(struct ufshcd_sg_entry)));
+ else
+ lrbp->utr_descriptor_ptr->prd_table_length =
+ cpu_to_le16((u16) (sg_segments));
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
- err = ufshcd_map_sg(lrbp);
+ err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, &hba->lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba *hba)
utrdlp[i].command_desc_base_addr_hi =
cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
+ if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+ utrdlp[i].response_upiu_offset =
+ cpu_to_le16(response_offset);
+ utrdlp[i].prd_table_offset =
+ cpu_to_le16(prdt_offset);
+ utrdlp[i].response_upiu_length =
+ cpu_to_le16(ALIGNED_UPIU_SIZE);
+ } else {
/* Response upiu and prdt offset should be in double words */
- utrdlp[i].response_upiu_offset =
+ utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
- utrdlp[i].prd_table_offset =
+ utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
- utrdlp[i].response_upiu_length =
+ utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+ }
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2570d9477b37..6cd542a803d5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -467,6 +467,13 @@ struct ufs_hba {
*/
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
+ /*
+ * This quirk needs to be enabled if host controller doesn't conform
+ * with UTRD. Some fields such as offset/length might not be in double
+ * word, but in byte.
+ */
+ #define UFSHCI_QUIRK_BYTE_ALIGN_UTRD UFS_BIT(6)
+
unsigned int quirks; /* Deviations from standard UFSHCI spec. */
wait_queue_head_t tm_wq;
--
1.7.10.4
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:40 +0100 |
| Subject | [PATCH v5 08/11] scsi: ufs: add add specific callback for hibern8 |
| Message-ID | <qsNln-2cc-3@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 33 +++++++++++++++++++++++++++++----
drivers/scsi/ufs/ufshcd.h | 10 ++++++++++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index eeb7835c52ab..075b7bf13080 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
bool skip_ref_clk);
static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
}
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+ return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
/*
* ufshcd_wait_for_register - wait for register value to change
* @hba - per-adapter interface
@@ -2394,7 +2403,7 @@ out:
return ret;
}
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
@@ -2403,7 +2412,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
}
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
{
struct uic_command uic_cmd = {0};
int ret;
@@ -2418,6 +2427,22 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
}
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+ int ret;
+
+ ufshcd_vops_hibern8_notify(hba, en, PRE_CHANGE);
+ ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+ __ufshcd_uic_hibern8_exit(hba);
+ if (ret)
+ goto out;
+
+ ufshcd_vops_hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+ return ret;
+}
+
/**
* ufshcd_init_pwr_info - setting the POR (power on reset)
* values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index b3dd08420100..9c69dd2f3672 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -262,6 +262,8 @@ struct ufs_pwr_mode_info {
* @specify_nexus_t_xfer_req:
* @specify_nexus_t_tm_req: called before command is issued to allow vendor
* specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried out
+ * to allow vendor spesific implementation.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -283,6 +285,7 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void (*hibern8_notify)(struct ufs_hba *, bool, bool);
void (*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void (*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
@@ -830,4 +833,11 @@ static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
if (hba->vops && hba->vops->specify_nexus_t_tm_req)
hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
}
+
+static inline void ufshcd_vops_hibern8_notify(struct ufs_hba *hba,
+ bool en, enum ufs_notify_change_status status)
+{
+ if (hba->vops && hba->vops->hibern8_notify)
+ hba->vops->hibern8_notify(hba, en, status);
+}
#endif /* End of Header */
--
1.7.10.4
--
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:40 +0100 |
| Subject | [PATCH v5 09/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func |
| Message-ID | <qsNlo-2cc-9@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 5 ++---
drivers/scsi/ufs/ufshcd.h | 2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 075b7bf13080..358d9114a1a5 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
- struct ufs_pa_layer_attr *desired_pwr_mode);
static int ufshcd_change_power_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *pwr_mode);
@@ -2592,7 +2590,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
* @hba: per-adapter instance
* @desired_pwr_mode: desired power configuration
*/
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
{
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2608,6 +2606,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
return ret;
}
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
/**
* ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9c69dd2f3672..8cad52c072d4 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -666,6 +666,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
u8 attr_set, u32 mib_val, u8 peer);
extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *desired_pwr_mode);
/* UIC command interfaces for DME primitives */
#define DME_LOCAL 0
--
1.7.10.4
--
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:40 +0100 |
| Subject | [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller |
| Message-ID | <qsNlo-2cc-15@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000000000000..08e2d1497b1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,104 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible : compatible name, contains "samsung,exynos7-ufs"
+- interrupts : <interrupt mapping for UFS host controller IRQ>
+- reg : Should contain HCI, vendor specific, UNIPRO and
+ UFS protector address space
+- reg-names : "hci", "vs_hci", "unipro", "ufsp";
+
+Optional properties:
+- vdd-hba-supply : phandle to UFS host controller supply regulator node
+- vcc-supply : phandle to VCC supply regulator node
+- vccq-supply : phandle to VCCQ supply regulator node
+- vccq2-supply : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
+ or 2.7-3.6V. This boolean property when set, specifies
+ to use low voltage range of 1.7-1.95V. Note for external
+ UFS cards this property is invalid and valid VCC range is
+ always 2.7-3.6V.
+- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
+- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
+- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
+
+- clocks : List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ "core", "sclk_unipro_main", "ref" and ref_parent
+
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are
+ "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+ allowed values are 1 or 2
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+ can be one of "HS_rate_b" or "HS_rate_a"
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+ 3 timers supported
+ <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+ 3 timers supported
+ <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
+ allowed step size is 0 to 3
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY
+ range is 1 to 9
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+ ufshc@0x15570000 {
+ compatible = "samsung,exynos7-ufs";
+ reg = <0x15570000 0x100>,
+ <0x15570100 0x100>,
+ <0x15571000 0x200>,
+ <0x15572000 0x300>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <0 200 0>;
+
+ vdd-hba-supply = <&xxx_reg0>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&xxx_reg1>;
+ vcc-supply-1p8;
+ vccq-supply = <&xxx_reg2>;
+ vccq2-supply = <&xxx_reg3>;
+ vcc-max-microamp = 500000;
+ vccq-max-microamp = 200000;
+ vccq2-max-microamp = 200000;
+
+ clocks = <&core 0>, <&ref 0>, <&iface 0>;
+ clock-names = "core", "sclk_unipro_main", "ref", "ref_parent";
+ freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
+
+ pclk-freq-avail-range = <70000000 133000000>;
+
+ ufs,pwr-attr-mode = "FAST";
+ ufs,pwr-attr-lane = <2>;
+ ufs,pwr-attr-gear = <2>;
+ ufs,pwr-attr-hs-series = "HS_rate_b";
+ ufs,pwr-local-l2-timer = <8000 28000 20000>;
+ ufs,pwr-remote-l2-timer = <12000 32000 16000>;
+ ufs-rx-adv-fine-gran-sup_en = <1>;
+ ufs-rx-adv-fine-gran-step = <3>;
+ ufs-rx-adv-min-activate-time-cap = <9>;
+ ufs-pa-granularity = <6>;
+ ufs-pa-tacctivate = <6>;
+ ufs-pa-hibern8time = <20>;
+ };
--
1.7.10.4
--
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-11-09 17:30 +0100 |
| Subject | Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller |
| Message-ID | <qsXur-mg-47@gated-at.bofh.it> |
| In reply to | #1265365 |
On Mon, Nov 09, 2015 at 10:56:26AM +0530, Alim Akhtar wrote:
> From: Seungwon Jeon <essuuj@gmail.com>
>
> This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
>
> Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
>
> diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> new file mode 100644
> index 000000000000..08e2d1497b1b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> @@ -0,0 +1,104 @@
> +* Exynos Universal Flash Storage (UFS) Host Controller
> +
> +UFSHC nodes are defined to describe on-chip UFS host controllers.
> +Each UFS controller instance should have its own node.
> +
> +Required properties:
> +- compatible : compatible name, contains "samsung,exynos7-ufs"
> +- interrupts : <interrupt mapping for UFS host controller IRQ>
> +- reg : Should contain HCI, vendor specific, UNIPRO and
> + UFS protector address space
> +- reg-names : "hci", "vs_hci", "unipro", "ufsp";
No phy for MPHY?
> +
> +Optional properties:
> +- vdd-hba-supply : phandle to UFS host controller supply regulator node
> +- vcc-supply : phandle to VCC supply regulator node
> +- vccq-supply : phandle to VCCQ supply regulator node
> +- vccq2-supply : phandle to VCCQ2 supply regulator node
> +- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
> + or 2.7-3.6V. This boolean property when set, specifies
> + to use low voltage range of 1.7-1.95V. Note for external
> + UFS cards this property is invalid and valid VCC range is
> + always 2.7-3.6V.
> +- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
> +- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
> +- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
Some of these are supplies to the flash chip, so you should make
these common properties (in a common doc).
> +- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
This should be determined from the regulator.
> +
> +- clocks : List of phandle and clock specifier pairs
> +- clock-names : List of clock input name strings sorted in the same
> + order as the clocks property.
> + "core", "sclk_unipro_main", "ref" and ref_parent
> +
> +- freq-table-hz : Array of <min max> operating frequencies stored in the same
> + order as the clocks property. If this property is not
> + defined or a value in the array is "0" then it is assumed
> + that the frequency is set by the parent clock or a
> + fixed rate clock source.
> +- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock
> +- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are
> + "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
ufs is not a vendor. Use a '-' rather than ','.
> +- ufs,pwr-attr-lane : specifies lane count value for power mode change
> + allowed values are 1 or 2
> +- ufs,pwr-attr-gear : specifies gear count value for power mode change
> + allowed values are 1 or 2
> +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
> + can be one of "HS_rate_b" or "HS_rate_a"
> +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
> + 3 timers supported
> + <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
> +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
> + 3 timers supported
> + <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
> +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
> + this is a boolean property.
> +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
> + allowed step size is 0 to 3
> +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY
> + range is 1 to 9
> +- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time
> +- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
> +- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
These are all M-PHY properties?
> +
> +Note: If above properties are not defined it can be assumed that the supply
> +regulators or clocks are always on.
> +
> +Example:
> + ufshc@0x15570000 {
> + compatible = "samsung,exynos7-ufs";
> + reg = <0x15570000 0x100>,
> + <0x15570100 0x100>,
> + <0x15571000 0x200>,
> + <0x15572000 0x300>;
> + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> + interrupts = <0 200 0>;
> +
> + vdd-hba-supply = <&xxx_reg0>;
> + vdd-hba-fixed-regulator;
> + vcc-supply = <&xxx_reg1>;
> + vcc-supply-1p8;
> + vccq-supply = <&xxx_reg2>;
> + vccq2-supply = <&xxx_reg3>;
> + vcc-max-microamp = 500000;
> + vccq-max-microamp = 200000;
> + vccq2-max-microamp = 200000;
> +
> + clocks = <&core 0>, <&ref 0>, <&iface 0>;
> + clock-names = "core", "sclk_unipro_main", "ref", "ref_parent";
> + freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
> +
> + pclk-freq-avail-range = <70000000 133000000>;
> +
> + ufs,pwr-attr-mode = "FAST";
> + ufs,pwr-attr-lane = <2>;
> + ufs,pwr-attr-gear = <2>;
> + ufs,pwr-attr-hs-series = "HS_rate_b";
> + ufs,pwr-local-l2-timer = <8000 28000 20000>;
> + ufs,pwr-remote-l2-timer = <12000 32000 16000>;
> + ufs-rx-adv-fine-gran-sup_en = <1>;
> + ufs-rx-adv-fine-gran-step = <3>;
> + ufs-rx-adv-min-activate-time-cap = <9>;
> + ufs-pa-granularity = <6>;
> + ufs-pa-tacctivate = <6>;
> + ufs-pa-hibern8time = <20>;
> + };
> --
> 1.7.10.4
>
> --
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-10 09:40 +0100 |
| Subject | Re: [PATCH v5 10/11] Documentation: devicetree: ufs: Add DT bindings for exynos UFS host controller |
| Message-ID | <qtcD8-2Fh-9@gated-at.bofh.it> |
| In reply to | #1265818 |
Hi Rob,
On 11/09/2015 09:53 PM, Rob Herring wrote:
> On Mon, Nov 09, 2015 at 10:56:26AM +0530, Alim Akhtar wrote:
>> From: Seungwon Jeon <essuuj@gmail.com>
>>
>> This adds Exynos Universal Flash Storage (UFS) Host Controller DT bindings.
>>
>> Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++++++++++++++++++++
>> 1 file changed, 104 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
>> new file mode 100644
>> index 000000000000..08e2d1497b1b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
>> @@ -0,0 +1,104 @@
>> +* Exynos Universal Flash Storage (UFS) Host Controller
>> +
>> +UFSHC nodes are defined to describe on-chip UFS host controllers.
>> +Each UFS controller instance should have its own node.
>> +
>> +Required properties:
>> +- compatible : compatible name, contains "samsung,exynos7-ufs"
>> +- interrupts : <interrupt mapping for UFS host controller IRQ>
>> +- reg : Should contain HCI, vendor specific, UNIPRO and
>> + UFS protector address space
>> +- reg-names : "hci", "vs_hci", "unipro", "ufsp";
>
> No phy for MPHY?
>
ufs-phy is documented, see 01/11 of this series.
>> +
>> +Optional properties:
>> +- vdd-hba-supply : phandle to UFS host controller supply regulator node
>> +- vcc-supply : phandle to VCC supply regulator node
>> +- vccq-supply : phandle to VCCQ supply regulator node
>> +- vccq2-supply : phandle to VCCQ2 supply regulator node
>> +- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
>> + or 2.7-3.6V. This boolean property when set, specifies
>> + to use low voltage range of 1.7-1.95V. Note for external
>> + UFS cards this property is invalid and valid VCC range is
>> + always 2.7-3.6V.
>> +- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
>> +- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
>> +- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
>
> Some of these are supplies to the flash chip, so you should make
> these common properties (in a common doc).
>
Ah, yes these are duplicated, already documented in common ufshcd file
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
What is the recommended way, do I need to include it here as well? or
just mentioning that "same as documented in ufshcd-pltfrm.txt"?
>> +- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
>
> This should be determined from the regulator.
>
Same as above already documented as part of ufshcd-pltfrm binding.
>> +
>> +- clocks : List of phandle and clock specifier pairs
>> +- clock-names : List of clock input name strings sorted in the same
>> + order as the clocks property.
>> + "core", "sclk_unipro_main", "ref" and ref_parent
>> +
>> +- freq-table-hz : Array of <min max> operating frequencies stored in the same
>> + order as the clocks property. If this property is not
>> + defined or a value in the array is "0" then it is assumed
>> + that the frequency is set by the parent clock or a
>> + fixed rate clock source.
>> +- pclk-freq-avail-range : specifies available frequency range(min/max) for APB clock
>> +- ufs,pwr-attr-mode : specifies mode value for power mode change, possible values are
>> + "FAST", "SLOW", "FAST_auto" and "SLOW_auto"
>
> ufs is not a vendor. Use a '-' rather than ','.
>
Ok will change.
>> +- ufs,pwr-attr-lane : specifies lane count value for power mode change
>> + allowed values are 1 or 2
>> +- ufs,pwr-attr-gear : specifies gear count value for power mode change
>> + allowed values are 1 or 2
>> +- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
>> + can be one of "HS_rate_b" or "HS_rate_a"
>> +- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
>> + 3 timers supported
>> + <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
>> +- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
>> + 3 timers supported
>> + <FC0ProtectionTimeOutVal,TC0ReplayTimeOutVal, AFC0ReqTimeOutVal>
>> +- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
>> + this is a boolean property.
>> +- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY,
>> + allowed step size is 0 to 3
>> +- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate time of MPHY
>> + range is 1 to 9
>> +- ufs-pa-granularity : specifies Granularity for PA_TActivate and PA_Hibern8Time
>> +- ufs-pa-tacctivate : specifies time to wake-up remote M-RX
>> +- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
>
> These are all M-PHY properties?
>
These are UIC (ufs interconnect) attributes related to M-PHY and Unipro
blocks.
>> +
>> +Note: If above properties are not defined it can be assumed that the supply
>> +regulators or clocks are always on.
>> +
>> +Example:
>> + ufshc@0x15570000 {
>> + compatible = "samsung,exynos7-ufs";
>> + reg = <0x15570000 0x100>,
>> + <0x15570100 0x100>,
>> + <0x15571000 0x200>,
>> + <0x15572000 0x300>;
>> + reg-names = "hci", "vs_hci", "unipro", "ufsp";
>> + interrupts = <0 200 0>;
>> +
>> + vdd-hba-supply = <&xxx_reg0>;
>> + vdd-hba-fixed-regulator;
>> + vcc-supply = <&xxx_reg1>;
>> + vcc-supply-1p8;
>> + vccq-supply = <&xxx_reg2>;
>> + vccq2-supply = <&xxx_reg3>;
>> + vcc-max-microamp = 500000;
>> + vccq-max-microamp = 200000;
>> + vccq2-max-microamp = 200000;
>> +
>> + clocks = <&core 0>, <&ref 0>, <&iface 0>;
>> + clock-names = "core", "sclk_unipro_main", "ref", "ref_parent";
>> + freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
>> +
>> + pclk-freq-avail-range = <70000000 133000000>;
>> +
>> + ufs,pwr-attr-mode = "FAST";
>> + ufs,pwr-attr-lane = <2>;
>> + ufs,pwr-attr-gear = <2>;
>> + ufs,pwr-attr-hs-series = "HS_rate_b";
>> + ufs,pwr-local-l2-timer = <8000 28000 20000>;
>> + ufs,pwr-remote-l2-timer = <12000 32000 16000>;
>> + ufs-rx-adv-fine-gran-sup_en = <1>;
>> + ufs-rx-adv-fine-gran-step = <3>;
>> + ufs-rx-adv-min-activate-time-cap = <9>;
>> + ufs-pa-granularity = <6>;
>> + ufs-pa-tacctivate = <6>;
>> + ufs-pa-hibern8time = <20>;
>> + };
>> --
>> 1.7.10.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
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>
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| From | Alim Akhtar <alim.akhtar@samsung.com> |
|---|---|
| Date | 2015-11-09 06:40 +0100 |
| Subject | [PATCH v5 07/11] scsi: ufs: add specific callback for nexus type |
| Message-ID | <qsNlo-2cc-19@gated-at.bofh.it> |
| In reply to | #1265356 |
From: Seungwon Jeon <essuuj@gmail.com>
Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.
Signed-off-by: Seungwon Jeon <essuuj@gmail.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufshcd.c | 3 +++
drivers/scsi/ufs/ufshcd.h | 19 +++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index e8b96ec65987..eeb7835c52ab 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1378,6 +1378,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1578,6 +1579,7 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = &wait;
spin_lock_irqsave(hba->host->host_lock, flags);
+ ufshcd_vops_specify_nexus_t_xfer_req(hba, tag, lrbp);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -3842,6 +3844,7 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
/* send command to the controller */
+ ufshcd_vops_specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, &hba->outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 500e137bf68a..b3dd08420100 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -259,6 +259,9 @@ struct ufs_pwr_mode_info {
* @pwr_change_notify: called before and after a power mode change
* is carried out to allow vendor spesific capabilities
* to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
@@ -280,6 +283,9 @@ struct ufs_hba_variant_ops {
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+ void (*specify_nexus_t_xfer_req)(struct ufs_hba *,
+ int, struct scsi_cmnd *);
+ void (*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void (*dbg_register_dump)(struct ufs_hba *hba);
@@ -811,4 +817,17 @@ static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
hba->vops->dbg_register_dump(hba);
}
+static inline void ufshcd_vops_specify_nexus_t_xfer_req(struct ufs_hba *hba,
+ int tag, struct ufshcd_lrb *lrbp)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+ hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
+}
+
+static inline void ufshcd_vops_specify_nexus_t_tm_req(struct ufs_hba *hba,
+ int free_slot, u8 tm_function)
+{
+ if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+ hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
+}
#endif /* End of Header */
--
1.7.10.4
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| From | Alim Akhtar <alim.akhtar@gmail.com> |
|---|---|
| Date | 2015-11-16 02:10 +0100 |
| Message-ID | <qvgsV-Bj-1@gated-at.bofh.it> |
| In reply to | #1265356 |
Hi Kishon,
Any more concern on the PHY part of this series?
Thanks!
On Mon, Nov 9, 2015 at 10:56 AM, Alim Akhtar <alim.akhtar@samsung.com> wrote:
> This patch-set introduces UFS (Universal Flash Storage) host support
> for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver.
> And it also contains some quirks handling for Exynos.
>
> NOTE: ** This series has a dependency on [4]. **
>
> -Changes since v4:
> * Removed platform specific PHY ops as suggested by Kishon
> * Rebased on the top of Yaniv Gardi's work [4]
> * make use of newly introduce ufshcd_{get,set}_variant
> * other small changes and improvements.
> * rebased on the top of linux next-20151109
>
> -Changes since v3:
> * Fixed compilation warrings as reported by "Kbuild Test Robot"[5].
> * Restructure the driver to make it as a platform driver, rebased on top of [4].
> * Addressed review comments from Arnd Bergmann[5].
> * Other misc changes and improvements.
>
> -Changes since v2:
> * Addressed review comments from Kishon[1] and Rob Herring [2]
> * Splited ufs dt binding documetation from ufs driver patch
>
> -Changes since v1:
> * Addressed review comments from Alexey[3] and various review comments from Amit.
> * Updated email id of Seungwon as his samsung id is void now.
> * Added ufs platform data
>
> [1]-> https://lkml.org/lkml/2015/9/18/29
> [2]-> https://lkml.org/lkml/2015/9/21/668
> [3]-> https://lkml.org/lkml/2015/8/23/124
> [4]-> https://lkml.org/lkml/2015/10/28/271
> [5]-> https://lkml.org/lkml/2015/10/1/402
>
> This patch set is tested on exynos7-espresso board.
>
>
> Alim Akhtar (1):
> Documentation: samsung-phy: Add dt bindings for UFS
>
> Seungwon Jeon (10):
> phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
> scsi: ufs: add quirk to contain unconformable utrd field
> scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
> scsi: ufs: add quirk not to allow reset of interrupt aggregation
> scsi: ufs: add quirk to enable host controller without hce
> scsi: ufs: add specific callback for nexus type
> scsi: ufs: add add specific callback for hibern8
> scsi: ufs: make ufshcd_config_pwr_mode of non-static func
> Documentation: devicetree: ufs: Add DT bindings for exynos UFS host
> controller
> scsi: ufs-exynos: add UFS host support for Exynos SoCs
>
> .../devicetree/bindings/phy/samsung-phy.txt | 22 +
> .../devicetree/bindings/ufs/ufs-exynos.txt | 104 ++
> drivers/phy/Kconfig | 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-exynos-ufs.c | 241 ++++
> drivers/phy/phy-exynos-ufs.h | 85 ++
> drivers/phy/phy-exynos7-ufs.h | 89 ++
> drivers/scsi/ufs/Kconfig | 12 +
> drivers/scsi/ufs/Makefile | 1 +
> drivers/scsi/ufs/ufs-exynos-hw.c | 131 ++
> drivers/scsi/ufs/ufs-exynos-hw.h | 43 +
> drivers/scsi/ufs/ufs-exynos.c | 1304 ++++++++++++++++++++
> drivers/scsi/ufs/ufs-exynos.h | 247 ++++
> drivers/scsi/ufs/ufshcd.c | 168 ++-
> drivers/scsi/ufs/ufshcd.h | 54 +
> drivers/scsi/ufs/ufshci.h | 26 +-
> drivers/scsi/ufs/unipro.h | 47 +
> include/linux/phy/phy-exynos-ufs.h | 85 ++
> 18 files changed, 2647 insertions(+), 20 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
> create mode 100644 drivers/phy/phy-exynos-ufs.c
> create mode 100644 drivers/phy/phy-exynos-ufs.h
> create mode 100644 drivers/phy/phy-exynos7-ufs.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
> create mode 100644 drivers/scsi/ufs/ufs-exynos.c
> create mode 100644 drivers/scsi/ufs/ufs-exynos.h
> create mode 100644 include/linux/phy/phy-exynos-ufs.h
>
> --
> 1.7.10.4
>
> --
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--
Regards,
Alim
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