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[tip:x86/urgent] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

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  [tip:x86/urgent] x86/cpu/intel:   Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield tip-bot for Andy Shevchenko <tipbot@zytor.com> - 2015-11-07 10:50 +0100

#1264782 — [tip:x86/urgent] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

Commit-ID:  354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9
Gitweb:     http://git.kernel.org/tip/354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9
Author:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Thu, 8 Oct 2015 18:56:26 +0300
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 7 Nov 2015 10:37:30 +0100

x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield

The Intel Merrifield SoC is a successor of the Intel MID line of
SoCs. Let's set the neccessary capability for that chip. See commit
c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3)
for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: http://lkml.kernel.org/r/1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/kernel/cpu/intel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98a13db..209ac1e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		switch (c->x86_model) {
 		case 0x27:	/* Penwell */
 		case 0x35:	/* Cloverview */
+		case 0x4a:	/* Merrifield */
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
--
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