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[PATCH RESEND 0/4] SMP support for Broadcom NSP

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  [PATCH RESEND 0/4] SMP support for Broadcom NSP Kapil Hali <kapilh@broadcom.com> - 2015-11-05 07:00 +0100
    [PATCH RESEND 4/4] ARM: BCM: Add SMP support for Broadcom 4708 Kapil Hali <kapilh@broadcom.com> - 2015-11-05 07:00 +0100
    [PATCH RESEND 2/4] ARM: dts: add SMP support for Broadcom NSP Kapil Hali <kapilh@broadcom.com> - 2015-11-05 07:00 +0100
    [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for Broadcom NSP Kapil Hali <kapilh@broadcom.com> - 2015-11-05 07:00 +0100
      Re: [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for  Broadcom NSP Rob Herring <robh@kernel.org> - 2015-11-05 21:50 +0100
        Re: [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for  Broadcom NSP Scott Branden <sbranden@broadcom.com> - 2015-11-05 22:00 +0100
    Re: [PATCH RESEND 0/4] SMP support for Broadcom NSP Russell King - ARM Linux <linux@arm.linux.org.uk> - 2015-11-05 10:40 +0100
      Re: [PATCH RESEND 0/4] SMP support for Broadcom NSP Hauke Mehrtens <hauke@hauke-m.de> - 2015-11-05 21:30 +0100
        Re: [PATCH RESEND 0/4] SMP support for Broadcom NSP Kapil Hali <kapilh@broadcom.com> - 2015-11-06 13:30 +0100
      Re: [PATCH RESEND 0/4] SMP support for Broadcom NSP Kapil Hali <kapilh@broadcom.com> - 2015-11-06 13:10 +0100

#1262946 — [PATCH RESEND 0/4] SMP support for Broadcom NSP

Hi,

This series adds SMP support for Broadcom's Northstar Plus SoC.

There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.

The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.

The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.

The second patch adds SMP support to the BCM NSP device tree file.

The third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.

The final patch, enables SMP on BCM 4708 and this patch is pulled
in from Jon Mason's patch from the mailing list.

This patch series is constructed based on Linux v4.3-rc2.

The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1

Jon Mason (1):
  ARM: BCM: Add SMP support for Broadcom 4708

Kapil Hali (3):
  dt-bindings: add SMP enable-method for Broadcom NSP
  ARM: dts: add SMP support for Broadcom NSP
  ARM: BCM: Add SMP support for Broadcom NSP

 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       |  36 ++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
 arch/arm/boot/dts/bcm-nsp.dtsi                     |  33 +++--
 arch/arm/boot/dts/bcm4708.dtsi                     |   2 +
 arch/arm/mach-bcm/Kconfig                          |   3 +
 arch/arm/mach-bcm/Makefile                         |  11 +-
 arch/arm/mach-bcm/bcm_nsp.h                        |  19 +++
 arch/arm/mach-bcm/headsmp.S                        |  37 ++++++
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c}        | 142 +++++++++++++++++++--
 9 files changed, 261 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
 create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
 create mode 100644 arch/arm/mach-bcm/headsmp.S
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)

-- 
2.1.0

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#1262947 — [PATCH RESEND 4/4] ARM: BCM: Add SMP support for Broadcom 4708

From: Jon Mason <jonmason@broadcom.com>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..22a41df 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,8 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff0400>;
 
 		cpu@0 {
 			device_type = "cpu";
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2e9dbb5..4fc8fa3 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC
+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 36a4ca30..3ca1cf1 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP)		+= headsmp.o platsmp.o
+endif
 
 # BCM63XXx
 ifeq ($(CONFIG_ARCH_BCM_63XX),y)
-- 
2.1.0

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#1262948 — [PATCH RESEND 2/4] ARM: dts: add SMP support for Broadcom NSP

Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d1875d9 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
 	model = "Broadcom Northstar Plus SoC";
 	interrupt-parent = <&gic>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x1>;
+		};
+	};
+
 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19020000 0x00003000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpu@0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				next-level-cache = <&L2>;
-				reg = <0x0>;
-			};
-		};
-
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0x2000 0x1000>;
-- 
2.1.0

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#1262949 — [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU pen-release mechanism.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..8506da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..6abe3f3 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
-- 
2.1.0

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#1263543 — Re: [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

On Thu, Nov 05, 2015 at 12:51:18AM -0500, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU pen-release mechanism.
> 
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";

This is supposed to be per core.

> +  - secondary-boot-reg = <...>;

What happens with more than 2 cores?

> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.
> +
> +Example:
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "brcm,bcm-nsp-smp";
> +		secondary-boot-reg = <0xffff042c>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <0>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <1>;
> +		};
> +	};
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>  			    "allwinner,sun8i-a23"
>  			    "arm,psci"
>  			    "brcm,brahma-b15"
> +			    "brcm,bcm-nsp-smp"
>  			    "marvell,armada-375-smp"
>  			    "marvell,armada-380-smp"
>  			    "marvell,armada-390-smp"
> -- 
> 2.1.0
> 
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#1263545 — Re: [PATCH RESEND 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

Hi Rob,

On 15-11-05 12:48 PM, Rob Herring wrote:
> On Thu, Nov 05, 2015 at 12:51:18AM -0500, Kapil Hali wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU pen-release mechanism.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>>   .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>   Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>   2 files changed, 37 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
>
> This is supposed to be per core.
>
>> +  - secondary-boot-reg = <...>;
>
> What happens with more than 2 cores?
>
I'm pretty sure nothing - all of these SoCs have 1 or 2 cores.

Regards,
Scott
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#1263041

On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote:
> Hi,
> 
> This series adds SMP support for Broadcom's Northstar Plus SoC.
> 
> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
> BCM NSP SoC, has a typical such mechanism - after power-on, the
> secondary core is held in a standby state, primary core provides a
> startup address for the secondary core and wakes it up. Booting of
> the secondary core is serialized using pen_release global variable.

Why do you need the pen_release stuff?  The above implies that you
have only one secondary core, and you can control when it comes out
of standby state.

Please, don't assume that the pen_release stuff is any kind of recommended
or standardised system.  It isn't.  It's a hack for ARMs evaluation
platforms.

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#1263539

On 11/05/2015 10:34 AM, Russell King - ARM Linux wrote:
> On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote:
>> Hi,
>>
>> This series adds SMP support for Broadcom's Northstar Plus SoC.
>>
>> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
>> BCM NSP SoC, has a typical such mechanism - after power-on, the
>> secondary core is held in a standby state, primary core provides a
>> startup address for the secondary core and wakes it up. Booting of
>> the secondary core is serialized using pen_release global variable.
> 
> Why do you need the pen_release stuff?  The above implies that you
> have only one secondary core, and you can control when it comes out
> of standby state.
> 
> Please, don't assume that the pen_release stuff is any kind of recommended
> or standardised system.  It isn't.  It's a hack for ARMs evaluation
> platforms.
> 

I tried to remove the pen code because I also thought/hoped that it is
useless, but the 2. CPU did not boot any more after I removed it. I do
not know the internals of SoC, but it looks like this is needed.

I described it here:
http://www.spinics.net/lists/arm-kernel/msg452178.html

I removed this comparison and the jump afterwards ("cmp     r7, r0") and
the 2. CPU did not boot any more. Is this pen stuff some kind of
workaround for some bug in the silicon?

Hauke
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#1263971

On 11/6/2015 1:55 AM, Hauke Mehrtens wrote:
> On 11/05/2015 10:34 AM, Russell King - ARM Linux wrote:
>> On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote:
>>> Hi,
>>>
>>> This series adds SMP support for Broadcom's Northstar Plus SoC.
>>>
>>> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
>>> BCM NSP SoC, has a typical such mechanism - after power-on, the
>>> secondary core is held in a standby state, primary core provides a
>>> startup address for the secondary core and wakes it up. Booting of
>>> the secondary core is serialized using pen_release global variable.
>>
>> Why do you need the pen_release stuff?  The above implies that you
>> have only one secondary core, and you can control when it comes out
>> of standby state.
>>
>> Please, don't assume that the pen_release stuff is any kind of recommended
>> or standardised system.  It isn't.  It's a hack for ARMs evaluation
>> platforms.
>>
> 
> I tried to remove the pen code because I also thought/hoped that it is
> useless, but the 2. CPU did not boot any more after I removed it. I do
> not know the internals of SoC, but it looks like this is needed.
> 
> I described it here:
> http://www.spinics.net/lists/arm-kernel/msg452178.html
> 
> I removed this comparison and the jump afterwards ("cmp     r7, r0") and
> the 2. CPU did not boot any more. Is this pen stuff some kind of
> workaround for some bug in the silicon?
> 
pen stuff is not a work around for any bug in BCM NSP silicon. It was the
mechanism to bring-up SMP on some of the ARM based SoCs and many silicon
vendors seem to consider it as a generic mechanism for controlled bring-up
of SMP. But as is clear from Russel King's comments, it is not a 
standardized recommended method.
Also, I removed the pen_release method and it works on BCM NSP SoCs. I 
will add the changes in the next patch set.
> Hauke
> 
Thanks,
Kapil Hali
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#1263955

On 11/5/2015 3:04 PM, Russell King - ARM Linux wrote:
> On Thu, Nov 05, 2015 at 12:51:17AM -0500, Kapil Hali wrote:
>> Hi,
>>
>> This series adds SMP support for Broadcom's Northstar Plus SoC.
>>
>> There are similar SMP enablement methods for many ARMv7 bsed SoCs.
>> BCM NSP SoC, has a typical such mechanism - after power-on, the
>> secondary core is held in a standby state, primary core provides a
>> startup address for the secondary core and wakes it up. Booting of
>> the secondary core is serialized using pen_release global variable.
> 
> Why do you need the pen_release stuff?  The above implies that you
> have only one secondary core, and you can control when it comes out
> of standby state.
> 
We can initiate a wake-up of the secondary core. I tested the changes
without pen_release method and it works. However, as I understand, I
think there is no other way for the primary core to know if the 
secondary core has come out of standby state other than pen_release
mechanism. When there is no other method available, will not 
smp_boot_secondary() always return successful wake-up of the
secondary core?

> Please, don't assume that the pen_release stuff is any kind of recommended
> or standardised system.  It isn't.  It's a hack for ARMs evaluation
> platforms.
> 
Got it. As pen_release is forbidden, I will change the SMP mechanism
to remove pen_release method in the new patch set.

Thanks,
Kapil

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