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[PATCH V2] x86/AMD: Fix LLC topology for AMD Fam17h systems

Started byAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
First post2015-11-03 21:40 +0100
Last post2015-11-07 10:50 +0100
Articles 3 — 2 participants

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  [PATCH V2] x86/AMD: Fix LLC topology for AMD Fam17h systems Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2015-11-03 21:40 +0100
    [tip:x86/urgent] x86/AMD:   Fix last level cache topology for AMD Fam17h systems tip-bot for Aravind Gopalakrishnan <tipbot@zytor.com> - 2015-11-04 13:00 +0100
    [tip:x86/urgent] x86/AMD:   Fix last level cache topology for AMD Fam17h systems tip-bot for Aravind Gopalakrishnan <tipbot@zytor.com> - 2015-11-07 10:50 +0100

#1261873 — [PATCH V2] x86/AMD: Fix LLC topology for AMD Fam17h systems

FromAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Date2015-11-03 21:40 +0100
Subject[PATCH V2] x86/AMD: Fix LLC topology for AMD Fam17h systems
Message-ID<qqQx3-7Ef-1@gated-at.bofh.it>
On AMD Fam17h systems, the last level cache is not resident in
Northbridge. Therefore, we cannot assign cpu_llc_id to same
value as Node ID (as we have been doing currently)

We should rather look at the ApicID bits of the core to provide
us the last level cache ID info. Doing that here.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
Changes in V2:
 - Move LLC calculation logic to amd_detect_cmp() and change patch
   header as a result. (This in turn fixes the issue found by
   kbuild bot on the V1 patch)
   
 arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..dab371e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,8 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
 	unsigned bits;
 	int cpu = smp_processor_id();
+	unsigned int apicid = c->apicid;
+	unsigned int socket_id, core_complex_id;
 
 	bits = c->x86_coreid_bits;
 	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +363,17 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 	/* use socket ID also for last level cache */
 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 	amd_get_topology(c);
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id = (apicid >> bits) - 1;
+	core_complex_id = (apicid & ((1 << bits) - 1)) >> 3;
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }
 
-- 
2.6.1

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#1262238 — [tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems

Fromtip-bot for Aravind Gopalakrishnan <tipbot@zytor.com>
Date2015-11-04 13:00 +0100
Subject[tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems
Message-ID<qr4To-8nc-17@gated-at.bofh.it>
In reply to#1261873
Commit-ID:  e5e84a26ef2909964d964224b805236293fb4c63
Gitweb:     http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63
Author:     Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 4 Nov 2015 12:52:06 +0100

x86/AMD: Fix last level cache topology for AMD Fam17h systems

On AMD Fam17h systems, the last level cache is not resident in the
northbridge. Therefore, we cannot assign cpu_llc_id to the same value as
Node ID as we have been doing until now.

We should rather look at the ApicID bits of the core to provide us the
last level cache ID info.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jacob Shin <jacob.w.shin@gmail.com>
Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..a8816b3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
 	unsigned bits;
 	int cpu = smp_processor_id();
+	unsigned int socket_id, core_complex_id;
 
 	bits = c->x86_coreid_bits;
 	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 	/* use socket ID also for last level cache */
 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 	amd_get_topology(c);
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id	= (c->apicid >> bits) - 1;
+	core_complex_id	= (c->apicid & ((1 << bits) - 1)) >> 3;
+
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }
 
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#1264777 — [tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems

Fromtip-bot for Aravind Gopalakrishnan <tipbot@zytor.com>
Date2015-11-07 10:50 +0100
Subject[tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems
Message-ID<qs8id-xb-1@gated-at.bofh.it>
In reply to#1261873
Commit-ID:  3849e91f571dcb48cf2c8143480c59137d44d6bc
Gitweb:     http://git.kernel.org/tip/3849e91f571dcb48cf2c8143480c59137d44d6bc
Author:     Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 7 Nov 2015 10:37:51 +0100

x86/AMD: Fix last level cache topology for AMD Fam17h systems

On AMD Fam17h systems, the last level cache is not resident in the
northbridge. Therefore, we cannot assign cpu_llc_id to the same value as
Node ID as we have been doing until now.

We should rather look at the ApicID bits of the core to provide us the
last level cache ID info.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jacob Shin <jacob.w.shin@gmail.com>
Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..a8816b3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
 	unsigned bits;
 	int cpu = smp_processor_id();
+	unsigned int socket_id, core_complex_id;
 
 	bits = c->x86_coreid_bits;
 	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 	/* use socket ID also for last level cache */
 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 	amd_get_topology(c);
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id	= (c->apicid >> bits) - 1;
+	core_complex_id	= (c->apicid & ((1 << bits) - 1)) >> 3;
+
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }
 
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