Groups > linux.kernel > #1259998 > unrolled thread

[PATCH v1 00/20] eznps a new ARC platform

Started by	Noam Camus <noamc@ezchip.com>
First post	2015-10-31 14:20 +0100
Last post	2015-11-09 14:00 +0100
Articles	20 on this page of 41 — 6 participants

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  [PATCH v1 00/20] eznps a new ARC platform Noam Camus <noamc@ezchip.com> - 2015-10-31 14:20 +0100
    Re: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Daniel Lezcano <daniel.lezcano@linaro.org> - 2015-11-01 21:50 +0100
      RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Noam Camus <noamc@ezchip.com> - 2015-11-02 09:00 +0100
    RE: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL() Noam Camus <noamc@ezchip.com> - 2015-11-02 07:30 +0100
    Re: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL() Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 07:30 +0100
    Re: [PATCH v1 09/20] ARC: add CONFIG_CLKSRC_OF support to  time_init() Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 07:40 +0100
    Re: [PATCH v1 08/20] ARC: Use res_service as entry point for  secondaries Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 07:40 +0100
      RE: [PATCH v1 08/20] ARC: Use res_service as entry point for  secondaries Noam Camus <noamc@ezchip.com> - 2015-11-02 09:10 +0100
    Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu  barrier Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 08:50 +0100
      Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu  barrier Peter Zijlstra <peterz@infradead.org> - 2015-11-02 10:30 +0100
    Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax() Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 09:00 +0100
    Re: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 09:00 +0100
      RE: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ Noam Camus <noamc@ezchip.com> - 2015-11-02 13:20 +0100
    Re: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 09:10 +0100
      RE: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers Noam Camus <noamc@ezchip.com> - 2015-11-02 14:10 +0100
    Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant Peter Zijlstra <peterz@infradead.org> - 2015-11-02 10:20 +0100
    Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax() Peter Zijlstra <peterz@infradead.org> - 2015-11-02 10:30 +0100
      RE: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax() Noam Camus <noamc@ezchip.com> - 2015-11-03 15:10 +0100
    Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 10:50 +0100
      Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant Peter Zijlstra <peterz@infradead.org> - 2015-11-02 11:10 +0100
    Re: [PATCH v1 11/20] ARC: [plat-eznps] Add eznps platform Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 12:00 +0100
      RE: [PATCH v1 11/20] ARC: [plat-eznps] Add eznps platform Noam Camus <noamc@ezchip.com> - 2015-11-03 17:10 +0100
      RE: [PATCH v1 11/20] ARC: [plat-eznps] Add eznps platform Noam Camus <noamc@ezchip.com> - 2015-11-04 13:40 +0100
    Re: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 12:10 +0100
      RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Noam Camus <noamc@ezchip.com> - 2015-11-03 17:10 +0100
    Re: [PATCH v1 20/20] ARC: Add eznps platform to Kconfig and Makefile Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 12:10 +0100
      RE: [PATCH v1 20/20] ARC: Add eznps platform to Kconfig and Makefile Noam Camus <noamc@ezchip.com> - 2015-11-03 16:40 +0100
    Re: [PATCH v1 13/20] ARC: [plat-eznps] Use dedicated  bitops/atomic/cmpxchg Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-02 13:00 +0100
    Re: [PATCH v1 00/20] eznps a new ARC platform Vineet Gupta <vgupta@synopsys.com> - 2015-11-04 16:40 +0100
      RE: [PATCH v1 00/20] eznps a new ARC platform Noam Camus <noamc@ezchip.com> - 2015-11-04 17:00 +0100
        RE: [PATCH v1 00/20] eznps a new ARC platform Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-04 18:50 +0100
    Re: [PATCH v1 11/20] ARC: [plat-eznps] Add eznps platform Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-05 06:20 +0100
    Re: [PATCH v2 03/19] clocksource: Add NPS400 timers driver Thomas Gleixner <tglx@linutronix.de> - 2015-11-07 12:30 +0100
    Re: [PATCH v2 04/19] irqchip: add nps Internal and external  irqchips Thomas Gleixner <tglx@linutronix.de> - 2015-11-07 12:40 +0100
      Re: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips Noam Camus <noamc@ezchip.com> - 2015-11-07 22:00 +0100
        Re: [PATCH v2 04/19] irqchip: add nps Internal and external  irqchips Thomas Gleixner <tglx@linutronix.de> - 2015-11-08 01:00 +0100
    Re: [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Peter Zijlstra <peterz@infradead.org> - 2015-11-09 11:10 +0100
      Re: [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-11-09 11:30 +0100
        Re: [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Peter Zijlstra <peterz@infradead.org> - 2015-11-09 11:50 +0100
          Re: [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Vineet Gupta <vgupta@synopsys.com> - 2015-11-09 13:30 +0100
            Re: [PATCH v2 16/19] ARC: [plat-eznps] Use dedicated cpu_relax() Peter Zijlstra <peterz@infradead.org> - 2015-11-09 14:00 +0100

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#1259998 — [PATCH v1 00/20] eznps a new ARC platform

From	Noam Camus <noamc@ezchip.com>
Date	2015-10-31 14:20 +0100
Subject	[PATCH v1 00/20] eznps a new ARC platform
Message-ID	<qpEeC-3hu-3@gated-at.bofh.it>

From: Noam Camus <noamc@ezchip.com>

This set introduce new platform to ARC architecture.
Platform name called "eznps" for working with EZchip NPS400
Network Proccessor.
NPS400 is targeted to service "fast path" network applications.

NPS400 got mesh of 256 extended ARC cores (AKA CTOP), each core
got 16 HW threats. This is basically SMT core where at any point of
time only one HW thread is active.
Each core have HW scheduler that round robin between eligible HW
threads. Totaly, kernel sees 4096 CPUs which I belive is a high record.
There is no cache coherency between cores so generic user applications
and kernel do not use D$.

Cores got special memory mappings for huge pages (8MB).
Mapping is static and should provide application enough memory without
any "TLB miss". This mapping is on top of TLB mapping.

This is a basic set that will later be followed with additional
set of patches with all advanced features.

Many thanks to all people helping to make this happen.

Regards,
Noam Camus

Noam Camus (17):
  Documentation: Add EZchip vendor to binding list
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips
  ARC: Set vmalloc size from configuration
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Mark cpu online only after it has executed the per cpu init
    hook.
  ARC: mm: use generic macros _BITUL()
  ARC: add CONFIG_CLKSRC_OF support to time_init()
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Use dedicated bitops/atomic/cmpxchg
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: [plat-eznps] define IPI_IRQ
  ARC: Add eznps platform to Kconfig and Makefile

Tal Zilcer (3):
  ARC: Use res_service as entry point for secondaries
  ARC: [plat-eznps] Use dedicated cpu_relax()
  ARC: [plat-eznps] replace sync with proper cpu barrier

 Documentation/devicetree/bindings/arc/eznps.txt    |    7 +
 .../interrupt-controller/ezchip,nps400-ic.txt      |   17 ++
 .../bindings/timer/ezchip,nps400-timer.txt         |   11 +
 .../devicetree/bindings/vendor-prefixes.txt        |    1 +
 MAINTAINERS                                        |    6 +
 arch/arc/Kconfig                                   |    9 +
 arch/arc/Makefile                                  |    9 +
 arch/arc/boot/dts/eznps.dts                        |   76 ++++++
 arch/arc/configs/nps_defconfig                     |   85 +++++++
 arch/arc/include/asm/atomic.h                      |   69 +++++
 arch/arc/include/asm/barrier.h                     |    8 +
 arch/arc/include/asm/bitops.h                      |   49 ++++
 arch/arc/include/asm/cmpxchg.h                     |   49 ++++
 arch/arc/include/asm/entry-compact.h               |    8 +
 arch/arc/include/asm/irq.h                         |    4 +
 arch/arc/include/asm/pgtable.h                     |    2 +-
 arch/arc/include/asm/processor.h                   |   32 ++-
 arch/arc/include/asm/setup.h                       |    4 +
 arch/arc/include/asm/smp.h                         |    2 +-
 arch/arc/include/asm/spinlock.h                    |   14 +
 arch/arc/kernel/ctx_sw.c                           |   20 ++
 arch/arc/kernel/smp.c                              |    9 +-
 arch/arc/kernel/time.c                             |    4 +
 arch/arc/mm/tlb.c                                  |   12 +
 arch/arc/plat-eznps/Kconfig                        |   34 +++
 arch/arc/plat-eznps/Makefile                       |    7 +
 arch/arc/plat-eznps/entry.S                        |   76 ++++++
 arch/arc/plat-eznps/include/plat/ctop.h            |  265 ++++++++++++++++++++
 arch/arc/plat-eznps/include/plat/mtm.h             |   60 +++++
 arch/arc/plat-eznps/include/plat/smp.h             |   27 ++
 arch/arc/plat-eznps/mtm.c                          |  152 +++++++++++
 arch/arc/plat-eznps/platform.c                     |   40 +++
 arch/arc/plat-eznps/smp.c                          |  160 ++++++++++++
 drivers/clocksource/Makefile                       |    1 +
 drivers/clocksource/timer-nps.c                    |  103 ++++++++
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-eznps.c                        |  222 ++++++++++++++++
 37 files changed, 1644 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arc/eznps.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 arch/arc/boot/dts/eznps.dts
 create mode 100644 arch/arc/configs/nps_defconfig
 create mode 100644 arch/arc/plat-eznps/Kconfig
 create mode 100644 arch/arc/plat-eznps/Makefile
 create mode 100644 arch/arc/plat-eznps/entry.S
 create mode 100644 arch/arc/plat-eznps/include/plat/ctop.h
 create mode 100644 arch/arc/plat-eznps/include/plat/mtm.h
 create mode 100644 arch/arc/plat-eznps/include/plat/smp.h
 create mode 100644 arch/arc/plat-eznps/mtm.c
 create mode 100644 arch/arc/plat-eznps/platform.c
 create mode 100644 arch/arc/plat-eznps/smp.c
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c

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#1260236 — Re: [PATCH v1 02/20] clocksource: Add NPS400 timers driver

From	Daniel Lezcano <daniel.lezcano@linaro.org>
Date	2015-11-01 21:50 +0100
Subject	Re: [PATCH v1 02/20] clocksource: Add NPS400 timers driver
Message-ID	<qq7JD-4Bn-1@gated-at.bofh.it>
In reply to	#1259998

On 10/31/2015 02:15 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>

Hi Noam,

Added Thomas Gleixner and John Stultz.

> ---
>   .../bindings/timer/ezchip,nps400-timer.txt         |   11 ++
>   drivers/clocksource/Makefile                       |    1 +
>   drivers/clocksource/timer-nps.c                    |  103 ++++++++++++++++++++
>   3 files changed, 115 insertions(+), 0 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
>   create mode 100644 drivers/clocksource/timer-nps.c
>
> diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> new file mode 100644
> index 0000000..c5102c2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> @@ -0,0 +1,11 @@
> +NPS Network Processor
> +
> +Required properties:
> +
> +- compatible :	should be "ezchip,nps400-timer"
> +
> +Example:
> +
> +timer {
> +	compatible = "ezchip,nps400-timer";
> +};
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 5c00863..28c17dc 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
>   obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
>   obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
>   obj-$(CONFIG_CLKSRC_PISTACHIO)	+= time-pistachio.o
> +obj-$(CONFIG_ARC_PLAT_EZNPS)	+= timer-nps.o

Please add an entry in the clocksource's Kconfig.

eg:

config NPS400_TIMER
	bool "NPS400 clocksource driver" if COMPILE_TEST
	help
	  NPS400 clocksource support.

and in the platform's Kconfig:

select NPS400_TIMER


>   obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
>   obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o
> diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
> new file mode 100644
> index 0000000..83a0a9d
> --- /dev/null
> +++ b/drivers/clocksource/timer-nps.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright(c) 2015 EZchip Technologies.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * The full GNU General Public License is included in this distribution in
> + * the file called "COPYING".
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqreturn.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_fdt.h>
> +#include <plat/ctop.h>

Are you sure all the headers are needed ?

> +#define NPS_MSU_TICK_LOW	0xC8
> +#define NPS_CLUSTER_OFFSET	8
> +#define NPS_CLUSTER_NUM		16
> +
> +static u32 nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
> +
> +/*
> + * To get the value from the Global Timer Counter register proceed as follows:
> + * 1. Read the upper 32-bit timer counter register
> + * 2. Read the lower 32-bit timer counter register
> + * 3. Read the upper 32-bit timer counter register again. If the value is
> + *  different to the 32-bit upper value read previously, go back to step 2.
> + *  Otherwise the 64-bit timer counter value is correct.
> + */
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> +	u64 counter;
> +	u32 lower;
> +	u32 upper, old_upper;
> +	int cpu;
> +	int cluster;
> +	void *lower_p, *upper_p;
> +	unsigned long flags;
> +
> +	local_irq_save(flags);

Why do you need to disable the interrupt here ?

> +	cpu = smp_processor_id();
> +	cluster = cpu >> NPS_CLUSTER_OFFSET;
> +	lower_p = (void *)nps_msu_reg_low_addr[cluster];
> +	upper_p = lower_p + 4;
> +	local_irq_restore(flags);
> +
> +	upper = ioread32be(upper_p);
> +	do {
> +		old_upper = upper;
> +		lower = ioread32be(lower_p);
> +		upper = ioread32be(upper_p);
> +	} while (upper != old_upper);
> +
> +	counter = upper;
> +	counter <<= 32;
> +	counter |= lower;
> +	return (cycle_t)counter;

May be you can consider using only the 32bits. Sometimes it is faster 
than using 64bits arithmetic and reading the register three times.

https://lkml.org/lkml/2014/6/20/431

> +}
> +
> +static struct clocksource nps_counter = {
> +	.name	= "EZnps-tick",
> +	.rating = 301,
> +	.read   = nps_clksrc_read,
> +	.mask   = CLOCKSOURCE_MASK(64),
> +	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void __init nps_setup_clocksource(struct device_node *node)
> +{
> +	struct clocksource *clksrc = &nps_counter;
> +	unsigned long rate, dt_root;
> +	int ret, cluster;
> +
> +	for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
> +		nps_msu_reg_low_addr[cluster] =
> +			nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
> +				 NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
> +
> +	dt_root = of_get_flat_dt_root();
> +	rate = (u32)of_get_flat_dt_prop(dt_root, "clock-frequency", NULL);

Why are you using 'of_get_flat_dt_root' / 'of_get_flat_dt_prop' ?

> +	ret = clocksource_register_hz(clksrc, rate);
> +	if (ret)
> +		pr_err("Couldn't register clock source.\n");
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(nps_400, "nps,400-timer",
> +		       nps_setup_clocksource);
>


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#1260443 — RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-02 09:00 +0100
Subject	RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver
Message-ID	<qqic3-2C5-47@gated-at.bofh.it>
In reply to	#1260236

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IGlzIGp1c3RpZmllZC4NCg0KLU5vYW0NCg0K
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#1260407 — RE: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-02 07:30 +0100
Subject	RE: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()
Message-ID	<qqgMW-1TU-1@gated-at.bofh.it>
In reply to	#1259998

From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
Sent: Monday, November 02, 2015 8:24 AM

> For bisectability, please squash this with patch 4/20, and append the changelog of this patch to 4/20

OK
- Noam

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#1260409 — Re: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 07:30 +0100
Subject	Re: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()
Message-ID	<qqgMW-1TU-5@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:49 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> PGDIR_SIZE() cannot use "1UL" since it is called from mm/tlbex.S
> by VMALLOC_START. _BITUL() solves this build error.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> ---
>  arch/arc/include/asm/pgtable.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
> index 57af2f0..372a282 100644
> --- a/arch/arc/include/asm/pgtable.h
> +++ b/arch/arc/include/asm/pgtable.h
> @@ -210,7 +210,7 @@
>  #define BITS_FOR_PGD	(32 - BITS_FOR_PTE - BITS_IN_PAGE)
>  
>  #define PGDIR_SHIFT	(32 - BITS_FOR_PGD)
> -#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)	/* vaddr span, not PDG sz */
> +#define PGDIR_SIZE	_BITUL(PGDIR_SHIFT)	/* vaddr span, not PDG sz */
>  #define PGDIR_MASK	(~(PGDIR_SIZE-1))
>  
>  #define	PTRS_PER_PTE	_BITUL(BITS_FOR_PTE)

For bisectability, please squash this with patch 4/20, and append the changelog of
this patch to 4/20

-Vineet

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#1260411 — Re: [PATCH v1 09/20] ARC: add CONFIG_CLKSRC_OF support to time_init()

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 07:40 +0100
Subject	Re: [PATCH v1 09/20] ARC: add CONFIG_CLKSRC_OF support to time_init()
Message-ID	<qqgWC-1X7-7@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:50 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> External clock source can be used if included by one of
> DTS file of a chosen platform.
> Signed-off-by: Noam Camus <noamc@ezchip.com>

Acked-by: Vineet Gupta <vgupta@synopsys.com>

> ---
>  arch/arc/kernel/time.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
> index dfad287..5313961 100644
> --- a/arch/arc/kernel/time.c
> +++ b/arch/arc/kernel/time.c
> @@ -283,6 +283,10 @@ void __init time_init(void)
>  		 */
>  		clocksource_register_hz(&arc_counter, arc_get_core_freq());
>  
> +#ifdef CONFIG_CLKSRC_OF
> +	clocksource_of_init();
> +#endif
> +
>  	/* sets up the periodic event timer */
>  	arc_local_timer_setup();
>  }

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#1260412 — Re: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 07:40 +0100
Subject	Re: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries
Message-ID	<qqgWC-1X7-3@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:50 PM, Noam Camus wrote:
> From: Tal Zilcer <talz@ezchip.com>
>
> At cpu_kick() we call res_service which can be implement by each
> platform and override gerneric weak definition.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> ---
>  arch/arc/include/asm/smp.h |    2 +-
>  arch/arc/kernel/smp.c      |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
> index 133c867..db05793 100644
> --- a/arch/arc/include/asm/smp.h
> +++ b/arch/arc/include/asm/smp.h
> @@ -30,7 +30,7 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
>   * APIs provided by arch SMP code to rest of arch code
>   */
>  extern void __init smp_init_cpus(void);
> -extern void first_lines_of_secondary(void);
> +extern void res_service(void);
>  extern const char *arc_platform_smp_cpuinfo(void);
>  
>  /*
> diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
> index 946109f..546079f 100644
> --- a/arch/arc/kernel/smp.c
> +++ b/arch/arc/kernel/smp.c
> @@ -167,7 +167,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
>  
>  	if (plat_smp_ops.cpu_kick)
>  		plat_smp_ops.cpu_kick(cpu,
> -				(unsigned long)first_lines_of_secondary);
> +				(unsigned long)res_service);

So I recently added the explicit handling of halt-on-reset vs. run-on-reset (for
non master cores)
This will cause infinite loop for non masters for run-on-reset ?

I'd suggest leave this arg alone and use whatever PC is needed inside your kick
routine

>  	else
>  		arc_default_smp_cpu_kick(cpu, (unsigned long)NULL);
>  

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#1260444 — RE: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-02 09:10 +0100
Subject	RE: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries
Message-ID	<qqilH-2Ut-3@gated-at.bofh.it>
In reply to	#1260412

From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
Sent: Monday, November 02, 2015 8:38 AM

> I'd suggest leave this arg alone and use whatever PC is needed inside your kick routine
OK

- Noam 

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#1260434 — Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 08:50 +0100
Subject	Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier
Message-ID	<qqi2n-2yF-41@gated-at.bofh.it>
In reply to	#1259998

+CC Peter.

On Saturday 31 October 2015 06:53 PM, Noam Camus wrote:
> From: Tal Zilcer <talz@ezchip.com>
>
> In SMT system like we have the generic "sync" is not working with
> HW threads. The replacement is "schd.rw" instruction that is served
> as cpu barrier for HW threads.
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> ---
>  arch/arc/kernel/ctx_sw.c |    7 +++++++
>  1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c
> index 92e2e82..2a2f50e 100644
> --- a/arch/arc/kernel/ctx_sw.c
> +++ b/arch/arc/kernel/ctx_sw.c
> @@ -61,7 +61,11 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
>  		"st      sp, [r24]       \n\t"
>  #endif
>  
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +		".word %5   \n\t"
> +#else
>  		"sync   \n\t"
> +#endif
>  
>  		/*
>  		 * setup _current_task with incoming tsk.
> @@ -122,6 +126,9 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
>  #ifdef CONFIG_ARC_PLAT_EZNPS
>  		, "i"(CTOP_AUX_LOGIC_GLOBAL_ID)
>  #endif
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +		, "i"(CTOP_INST_SCHD_RW)
> +#endif
>  		: "blink"
>  	);

Since u bring this up - I think we don't need the original SYNC and/or SMT thread
schedule at all.
The SYNC here is a historic relic at best and we can get rid of it per reasoning
below:

In UP context it is obviously useless, why would we want to stall the core for all
updates to stack memory of t0 to complete before loading kernel ode callee
registers from t1 stack's memory.

In SMP, we could have a potential race in which outdoing task could be
concurrently picked for running, thus the writes to stack here need to be visible
before the reads from stack on other core. But I think since this is the same rq,
there would be a taken spinlock and once a core gives it up, an smp barrier would
come naturally.

Peter do u concur ?
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#1260490 — Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-11-02 10:30 +0100
Subject	Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier
Message-ID	<qqjB8-3zJ-17@gated-at.bofh.it>
In reply to	#1260434

On Mon, Nov 02, 2015 at 07:48:54AM +0000, Vineet Gupta wrote:
> Since u bring this up - I think we don't need the original SYNC and/or
> SMT thread schedule at all.  The SYNC here is a historic relic at best
> and we can get rid of it per reasoning below:
> 
> In UP context it is obviously useless, why would we want to stall the
> core for all updates to stack memory of t0 to complete before loading
> kernel ode callee registers from t1 stack's memory.
> 
> In SMP, we could have a potential race in which outdoing task could be
> concurrently picked for running, thus the writes to stack here need to
> be visible before the reads from stack on other core. But I think
> since this is the same rq, there would be a taken spinlock and once a
> core gives it up, an smp barrier would come naturally.
> 
> Peter do u concur ?

I'm still somewhat jet-lagged, but I think the below reference should
answer your question:

lkml.kernel.org/r/20150917130125.GL3816@twins.programming.kicks-ass.net

I (still) need to update that patch and send it out again.

But I think it answers your question; we do not rely on arch code to
provide barriers for the generic code.

Now, if for some reason the arch code has further constraints, then
maybe, but I don't think so.
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#1260437 — Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 09:00 +0100
Subject	Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()
Message-ID	<qqic2-2C5-7@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:52 PM, Noam Camus wrote:
> From: Tal Zilcer <talz@ezchip.com>
>
> Since the CTOP is SMT hardware multi-threaded, we need to hint
> the HW that now will be a very good time to do a hardware
> thread context switching. This is done by issuing the schd.rw
> instruction (binary coded here so as to not require specific
> revision of GCC to build the kernel).
> sched.rw means that Thread becomes eligible for execution by
> the threads scheduler after all pending read/write
> transactions were completed.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Peter Zijlstra <peterz@infradead.org>

Acked-by: Vineet Gupta <vgupta@synopsys.com>

> ---
>  arch/arc/include/asm/processor.h |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
> index 7266ede..f1a51a6 100644
> --- a/arch/arc/include/asm/processor.h
> +++ b/arch/arc/include/asm/processor.h
> @@ -58,7 +58,12 @@ struct task_struct;
>   * get optimised away by gcc
>   */
>  #ifdef CONFIG_SMP
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +#define cpu_relax()     \
> +	__asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
> +#else
>  #define cpu_relax()	__asm__ __volatile__ ("" : : : "memory")
> +#endif
>  #else
>  #define cpu_relax()	do { } while (0)
>  #endif

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#1260438 — Re: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 09:00 +0100
Subject	Re: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ
Message-ID	<qqic2-2C5-15@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> We add IPI irq definition to be used later by any
> irqchip such NPS400 IC.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>

Again this break bisectability - it needs to be placed before you use this #define
in patch 3/20.
Anyhow since you are doing stuff via DT, why not get this value from DT itself
instead of hard coding.

> ---
>  arch/arc/include/asm/irq.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
> index 4fd7d62..c5f8f0f 100644
> --- a/arch/arc/include/asm/irq.h
> +++ b/arch/arc/include/asm/irq.h
> @@ -16,7 +16,11 @@
>  #ifdef CONFIG_ISA_ARCOMPACT
>  #define TIMER0_IRQ      3
>  #define TIMER1_IRQ      4
> +#if defined(CONFIG_SMP) && defined(CONFIG_ARC_PLAT_EZNPS)
> +#define IPI_IRQ         5
> +#else
>  #define IPI_IRQ		(NR_CPU_IRQS-1) /* dummy to enable SMP build for up hardware */
> +#endif
>  #else
>  #define TIMER0_IRQ      16
>  #define TIMER1_IRQ      17

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#1260591 — RE: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-02 13:20 +0100
Subject	RE: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ
Message-ID	<qqmfD-5cO-15@gated-at.bofh.it>
In reply to	#1260438

> From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
> Sent: Monday, November 02, 2015 9:53 AM

> Again this break bisectability - it needs to be placed before you use this #define in patch 3/20.
> Anyhow since you are doing stuff via DT, why not get this value from DT itself instead of hard coding.

OK I will change order.
However last commit should protect us since without it nothing will be compiled.

-Noam
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#1260449 — Re: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 09:10 +0100
Subject	Re: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers
Message-ID	<qqilI-2Ut-23@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:52 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> NPS device got 256 cores and each got 16 HW threads (SMT).
> We use EZchip dedicated ISA to trigger HW scheduler of the
> core that current HW thread belongs to.
> This scheduling makes sure that data beyond barrier is available
> to all HW threads in core and by that to all in device (4K).
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> ---
>  arch/arc/include/asm/barrier.h |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h
> index a720998..c8229b8 100644
> --- a/arch/arc/include/asm/barrier.h
> +++ b/arch/arc/include/asm/barrier.h
> @@ -34,6 +34,12 @@
>  
>  #ifdef CONFIG_ISA_ARCOMPACT
>  
> +#ifdef CONFIG_ARC_PLAT_EZNPS
> +#include <plat/ctop.h>
> +#define mb()	asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
> +#define rmb()	asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory")

Do u need this even for mandatory barriers whose semantics are not related to SMP
at all ? I think you need them only for smb_*

Following is a good introduction to difference between the two !
https://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel

> +#else
> +
>  /*
>   * ARCompact based cores (ARC700) only have SYNC instruction which is super
>   * heavy weight as it flushes the pipeline as well.
> @@ -41,6 +47,8 @@
>   */
>  
>  #define mb()	asm volatile("sync\n" : : : "memory")
> +#endif /* CONFIG_ARC_PLAT_EZNPS */
> +
>  #endif
>  
>  #include <asm-generic/barrier.h>

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#1260633 — RE: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-02 14:10 +0100
Subject	RE: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers
Message-ID	<qqn24-5Jb-63@gated-at.bofh.it>
In reply to	#1260449

From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
Sent: Monday, November 02, 2015 10:03 AM

> Do u need this even for mandatory barriers whose semantics are not related to SMP at all ? I think you need them only for smb_*
Yes I do.
For example it is used to proceed access to our Global Interrupt Manager (GIM) when we want to make sure that driver of some device committed all read/writes before we are acknowledging the GIM.
We are not falling to use "sync" since we prefer to have HW thread schedule in the meantime we wait for load/store to be done.

- Noam
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#1260482 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-11-02 10:20 +0100
Subject	Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant
Message-ID	<qqjrs-3wz-27@gated-at.bofh.it>
In reply to	#1259998

On Sat, Oct 31, 2015 at 03:15:12PM +0200, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
> 
> If we hold rw->lock_mutex and interrupt occures we may
> end up spinning on it for ever during softirq.
> 
> Below you may see an example for interrupt we get while
> nl_table_lock is holding its rw->lock_mutex and we spinned
> on it for ever.
> 
> The concept for the fix was taken from SPARC.
> 
> [2015-05-12 19:16:12] Stack Trace:
> [2015-05-12 19:16:12]   arc_unwind_core+0xb8/0x11c
> [2015-05-12 19:16:12]   dump_stack+0x68/0xac
> [2015-05-12 19:16:12]   _raw_read_lock+0xa8/0xac
> [2015-05-12 19:16:12]   netlink_broadcast_filtered+0x56/0x35c
> [2015-05-12 19:16:12]   nlmsg_notify+0x42/0xa4
> [2015-05-12 19:16:13]   neigh_update+0x1fe/0x44c
> [2015-05-12 19:16:13]   neigh_event_ns+0x40/0xa4
> [2015-05-12 19:16:13]   arp_process+0x46e/0x5a8
> [2015-05-12 19:16:13]   __netif_receive_skb_core+0x358/0x500
> [2015-05-12 19:16:13]   process_backlog+0x92/0x154
> [2015-05-12 19:16:13]   net_rx_action+0xb8/0x188
> [2015-05-12 19:16:13]   __do_softirq+0xda/0x1d8
> [2015-05-12 19:16:14]   irq_exit+0x8a/0x8c
> [2015-05-12 19:16:14]   arch_do_IRQ+0x6c/0xa8
> [2015-05-12 19:16:14]   handle_interrupt_level1+0xe4/0xf0
> 
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Peter Zijlstra <peterz@infradead.org>

It might make sense to note that this is a lock internal lock and since
the lock is free to be used from any context, the lock needs to be
IRQ-safe.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

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#1260488 — Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-11-02 10:30 +0100
Subject	Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()
Message-ID	<qqjB8-3zJ-11@gated-at.bofh.it>
In reply to	#1259998

On Sat, Oct 31, 2015 at 03:15:23PM +0200, Noam Camus wrote:
> From: Tal Zilcer <talz@ezchip.com>
> 
> Since the CTOP is SMT hardware multi-threaded, we need to hint
> the HW that now will be a very good time to do a hardware
> thread context switching. This is done by issuing the schd.rw
> instruction (binary coded here so as to not require specific
> revision of GCC to build the kernel).
> sched.rw means that Thread becomes eligible for execution by
> the threads scheduler after all pending read/write
> transactions were completed.
> 
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> ---
>  arch/arc/include/asm/processor.h |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
> index 7266ede..f1a51a6 100644
> --- a/arch/arc/include/asm/processor.h
> +++ b/arch/arc/include/asm/processor.h
> @@ -58,7 +58,12 @@ struct task_struct;
>   * get optimised away by gcc
>   */
>  #ifdef CONFIG_SMP
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +#define cpu_relax()     \
> +	__asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
> +#else
>  #define cpu_relax()	__asm__ __volatile__ ("" : : : "memory")
> +#endif
>  #else
>  #define cpu_relax()	do { } while (0)
>  #endif

At which point you might want to revisit:

arch/arc/include/asm/processor.h:#define cpu_relax_lowlatency() cpu_relax()

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#1261523 — RE: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

From	Noam Camus <noamc@ezchip.com>
Date	2015-11-03 15:10 +0100
Subject	RE: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()
Message-ID	<qqKrF-3Jf-31@gated-at.bofh.it>
In reply to	#1260488

From: Peter Zijlstra [mailto:peterz@infradead.org] 
Sent: Monday, November 02, 2015 11:22 AM


> At which point you might want to revisit:

> arch/arc/include/asm/processor.h:#define cpu_relax_lowlatency() cpu_relax()
Thanks, I will define this as barrier since cpu_relax() may take out current logical CPU for many cycles.
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#1260499 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant

From	Vineet Gupta <Vineet.Gupta1@synopsys.com>
Date	2015-11-02 10:50 +0100
Subject	Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant
Message-ID	<qqjUt-3G6-11@gated-at.bofh.it>
In reply to	#1259998

On Saturday 31 October 2015 06:45 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
> 
> If we hold rw->lock_mutex and interrupt occures we may
> end up spinning on it for ever during softirq.
> 
> Below you may see an example for interrupt we get while
> nl_table_lock is holding its rw->lock_mutex and we spinned
> on it for ever.
> 
> The concept for the fix was taken from SPARC.
> 
> [2015-05-12 19:16:12] Stack Trace:
> [2015-05-12 19:16:12]   arc_unwind_core+0xb8/0x11c
> [2015-05-12 19:16:12]   dump_stack+0x68/0xac
> [2015-05-12 19:16:12]   _raw_read_lock+0xa8/0xac
> [2015-05-12 19:16:12]   netlink_broadcast_filtered+0x56/0x35c
> [2015-05-12 19:16:12]   nlmsg_notify+0x42/0xa4
> [2015-05-12 19:16:13]   neigh_update+0x1fe/0x44c
> [2015-05-12 19:16:13]   neigh_event_ns+0x40/0xa4
> [2015-05-12 19:16:13]   arp_process+0x46e/0x5a8
> [2015-05-12 19:16:13]   __netif_receive_skb_core+0x358/0x500
> [2015-05-12 19:16:13]   process_backlog+0x92/0x154
> [2015-05-12 19:16:13]   net_rx_action+0xb8/0x188
> [2015-05-12 19:16:13]   __do_softirq+0xda/0x1d8
> [2015-05-12 19:16:14]   irq_exit+0x8a/0x8c
> [2015-05-12 19:16:14]   arch_do_IRQ+0x6c/0xa8
> [2015-05-12 19:16:14]   handle_interrupt_level1+0xe4/0xf0
> 
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> ---
>  arch/arc/include/asm/spinlock.h |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
> index db8c59d..800e7c4 100644
> --- a/arch/arc/include/asm/spinlock.h
> +++ b/arch/arc/include/asm/spinlock.h
> @@ -610,7 +610,9 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
>  static inline int arch_read_trylock(arch_rwlock_t *rw)
>  {
>  	int ret = 0;
> +	unsigned long flags;
>  
> +	local_irq_save(flags);
>  	arch_spin_lock(&(rw->lock_mutex));
>  
>  	/*
> @@ -623,6 +625,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
>  	}
>  
>  	arch_spin_unlock(&(rw->lock_mutex));
> +	local_irq_restore(flags);
>  
>  	smp_mb();
>  	return ret;
> @@ -632,7 +635,9 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
>  static inline int arch_write_trylock(arch_rwlock_t *rw)
>  {
>  	int ret = 0;
> +	unsigned long flags;
>  
> +	local_irq_save(flags);
>  	arch_spin_lock(&(rw->lock_mutex));
>  
>  	/*
> @@ -646,6 +651,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
>  		ret = 1;
>  	}
>  	arch_spin_unlock(&(rw->lock_mutex));
> +	local_irq_restore(flags);
>  
>  	return ret;
>  }
> @@ -664,16 +670,24 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
>  
>  static inline void arch_read_unlock(arch_rwlock_t *rw)
>  {
> +	unsigned long flags;
> +
> +	local_irq_save(flags);
>  	arch_spin_lock(&(rw->lock_mutex));


Isn't raw_spin_lock_irqsave() equivalent and more concise ?


>  	rw->counter++;
>  	arch_spin_unlock(&(rw->lock_mutex));
> +	local_irq_restore(flags);
>  }
>  
>  static inline void arch_write_unlock(arch_rwlock_t *rw)
>  {
> +	unsigned long flags;
> +
> +	local_irq_save(flags);
>  	arch_spin_lock(&(rw->lock_mutex));
>  	rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
>  	arch_spin_unlock(&(rw->lock_mutex));
> +	local_irq_restore(flags);
>  }
>  
>  #endif
> 

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#1260511 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-11-02 11:10 +0100
Subject	Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant
Message-ID	<qqkdQ-42a-35@gated-at.bofh.it>
In reply to	#1260499

On Mon, Nov 02, 2015 at 03:12:49PM +0530, Vineet Gupta wrote:
> > @@ -664,16 +670,24 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
> >  
> >  static inline void arch_read_unlock(arch_rwlock_t *rw)
> >  {
> > +	unsigned long flags;
> > +
> > +	local_irq_save(flags);
> >  	arch_spin_lock(&(rw->lock_mutex));
> 
> 
> Isn't raw_spin_lock_irqsave() equivalent and more concise ?

You might run into header file recursion issues; also raw_spinlock has
lockdep annotations added, whereas the above does not.
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Page 1 of 3 [1] 2 3 Next page →

csiph-web

[PATCH v1 00/20] eznps a new ARC platform

Contents

#1259998 — [PATCH v1 00/20] eznps a new ARC platform

#1260236 — Re: [PATCH v1 02/20] clocksource: Add NPS400 timers driver

#1260443 — RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver

#1260407 — RE: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()

#1260409 — Re: [PATCH v1 07/20] ARC: mm: use generic macros _BITUL()

#1260411 — Re: [PATCH v1 09/20] ARC: add CONFIG_CLKSRC_OF support to time_init()

#1260412 — Re: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries

#1260444 — RE: [PATCH v1 08/20] ARC: Use res_service as entry point for secondaries

#1260434 — Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier

#1260490 — Re: [PATCH v1 19/20] ARC: [plat-eznps] replace sync with proper cpu barrier

#1260437 — Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

#1260438 — Re: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ

#1260591 — RE: [PATCH v1 18/20] ARC: [plat-eznps] define IPI_IRQ

#1260449 — Re: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers

#1260633 — RE: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers

#1260482 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant

#1260488 — Re: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

#1261523 — RE: [PATCH v1 16/20] ARC: [plat-eznps] Use dedicated cpu_relax()

#1260499 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant

#1260511 — Re: [PATCH v1 05/20] ARC: rwlock: disable interrupts in !LLSC variant