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| Started by | Boqun Feng <boqun.feng@gmail.com> |
|---|---|
| First post | 2015-11-02 02:40 +0100 |
| Last post | 2015-11-02 10:20 +0100 |
| Articles | 3 — 3 participants |
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[PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Boqun Feng <boqun.feng@gmail.com> - 2015-11-02 02:40 +0100
Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> - 2015-11-02 03:30 +0100
Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered Peter Zijlstra <peterz@infradead.org> - 2015-11-02 10:20 +0100
| From | Boqun Feng <boqun.feng@gmail.com> |
|---|---|
| Date | 2015-11-02 02:40 +0100 |
| Subject | [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered |
| Message-ID | <qqcgh-7te-3@gated-at.bofh.it> |
According to memory-barriers.txt: > Any atomic operation that modifies some state in memory and returns > information about the state (old or new) implies an SMP-conditional > general memory barrier (smp_mb()) on each side of the actual > operation ... Which mean these operations should be fully ordered. However on PPC, PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, which is currently "lwsync" if SMP=y. The leading "lwsync" can not guarantee fully ordered atomics, according to Paul Mckenney: https://lkml.org/lkml/2015/10/14/970 To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee the fully-ordered semantics. This also makes futex atomics fully ordered, which can avoid possible memory ordering problems if userspace code relies on futex system call for fully ordered semantics. Cc: <stable@vger.kernel.org> # 3.4+ Signed-off-by: Boqun Feng <boqun.feng@gmail.com> --- These two are separated and splited from the patchset of powerpc atomic variants implementation, whose link is: https://lkml.org/lkml/2015/10/26/141 Based on next branch of powerpc tree, tested by 0day. arch/powerpc/include/asm/synch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h index e682a71..c508686 100644 --- a/arch/powerpc/include/asm/synch.h +++ b/arch/powerpc/include/asm/synch.h @@ -44,7 +44,7 @@ static inline void isync(void) MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup); #define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER) #define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n" -#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n" +#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n" #define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n" #else #define PPC_ACQUIRE_BARRIER -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> |
|---|---|
| Date | 2015-11-02 03:30 +0100 |
| Subject | Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered |
| Message-ID | <qqd2G-7YD-1@gated-at.bofh.it> |
| In reply to | #1260291 |
On Mon, Nov 02, 2015 at 09:30:31AM +0800, Boqun Feng wrote: > According to memory-barriers.txt: > > > Any atomic operation that modifies some state in memory and returns > > information about the state (old or new) implies an SMP-conditional > > general memory barrier (smp_mb()) on each side of the actual > > operation ... > > Which mean these operations should be fully ordered. However on PPC, > PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, > which is currently "lwsync" if SMP=y. The leading "lwsync" can not > guarantee fully ordered atomics, according to Paul Mckenney: > > https://lkml.org/lkml/2015/10/14/970 > > To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee > the fully-ordered semantics. > > This also makes futex atomics fully ordered, which can avoid possible > memory ordering problems if userspace code relies on futex system call > for fully ordered semantics. > > Cc: <stable@vger.kernel.org> # 3.4+ > Signed-off-by: Boqun Feng <boqun.feng@gmail.com> Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> > --- > These two are separated and splited from the patchset of powerpc atomic > variants implementation, whose link is: > > https://lkml.org/lkml/2015/10/26/141 > > Based on next branch of powerpc tree, tested by 0day. > > arch/powerpc/include/asm/synch.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h > index e682a71..c508686 100644 > --- a/arch/powerpc/include/asm/synch.h > +++ b/arch/powerpc/include/asm/synch.h > @@ -44,7 +44,7 @@ static inline void isync(void) > MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup); > #define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER) > #define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n" > -#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n" > +#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n" > #define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n" > #else > #define PPC_ACQUIRE_BARRIER > -- > 2.6.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Date | 2015-11-02 10:20 +0100 |
| Subject | Re: [PATCH powerpc/next 1/2] powerpc: Make value-returning atomics fully ordered |
| Message-ID | <qqjrr-3wz-3@gated-at.bofh.it> |
| In reply to | #1260291 |
On Mon, Nov 02, 2015 at 09:30:31AM +0800, Boqun Feng wrote: > According to memory-barriers.txt: > > > Any atomic operation that modifies some state in memory and returns > > information about the state (old or new) implies an SMP-conditional > > general memory barrier (smp_mb()) on each side of the actual > > operation ... > > Which mean these operations should be fully ordered. However on PPC, > PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, > which is currently "lwsync" if SMP=y. The leading "lwsync" can not > guarantee fully ordered atomics, according to Paul Mckenney: > > https://lkml.org/lkml/2015/10/14/970 > > To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee > the fully-ordered semantics. > > This also makes futex atomics fully ordered, which can avoid possible > memory ordering problems if userspace code relies on futex system call > for fully ordered semantics. > > Cc: <stable@vger.kernel.org> # 3.4+ > Signed-off-by: Boqun Feng <boqun.feng@gmail.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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