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| Started by | Caesar Wang <wxt@rock-chips.com> |
|---|---|
| First post | 2015-11-03 09:20 +0100 |
| Last post | 2015-11-03 11:30 +0100 |
| Articles | 4 — 4 participants |
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[RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 Caesar Wang <wxt@rock-chips.com> - 2015-11-03 09:20 +0100
Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 Arnd Bergmann <arnd@arndb.de> - 2015-11-03 09:50 +0100
Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 Caesar Wang <caesar.upstream@gmail.com> - 2015-11-03 10:10 +0100
Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 kbuild test robot <lkp@intel.com> - 2015-11-03 11:30 +0100
| From | Caesar Wang <wxt@rock-chips.com> |
|---|---|
| Date | 2015-11-03 09:20 +0100 |
| Subject | [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 |
| Message-ID | <qqEYW-9k-27@gated-at.bofh.it> |
From: Huang Tao <huangtao@rock-chips.com> On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM instruction. This workaround setting bit[12] of the Feature Register prevents the erratum. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- arch/arm/Kconfig | 13 +++++++++++++ arch/arm/mm/proc-v7.S | 12 ++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 639411f..554b57a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1263,6 +1263,19 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_818325 + bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 818325 Cortex-A12 + (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of + two conditional store instructions with opposite condition code and + updating the same register, the system might enter a deadlock if the + second conditional instruction is an UNPREDICTABLE STR or STM + instruction. This workaround setting bit[12] of the Feature Register + prevents the erratum. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index de2b246..2b338ec 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -439,6 +439,18 @@ __v7_setup_cont: teq r0, r10 beq __ca9_errata + /* Cortex-A12 Errata */ + ldr r10, =0x00000c0d @ Cortex-A12 primary part number + teq r0, r10 + bne 5f +#ifdef CONFIG_ARM_ERRATA_818325 + teq r6, #0x00 @ present in r0p0 + teqne r6, #0x01 @ present in r0p1-00lac0-rc11 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 12 @ set bit #12 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register + isb +#endif /* Cortex-A15 Errata */ ldr r10, =0x00000c0f @ Cortex-A15 primary part number teq r0, r10 -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2015-11-03 09:50 +0100 |
| Message-ID | <qqFrY-jV-19@gated-at.bofh.it> |
| In reply to | #1261276 |
On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote: > > + /* Cortex-A12 Errata */ > + ldr r10, =0x00000c0d @ Cortex-A12 primary part number > + teq r0, r10 > + bne 5f > +#ifdef CONFIG_ARM_ERRATA_818325 > + teq r6, #0x00 @ present in r0p0 > + teqne r6, #0x01 @ present in r0p1-00lac0-rc11 > + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register > + orreq r10, r10, #1 << 12 @ set bit #12 > + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register > + isb > +#endif > /* Cortex-A15 Errata */ > Does this still build? You seem to have lost the '5:' label. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Caesar Wang <caesar.upstream@gmail.com> |
|---|---|
| Date | 2015-11-03 10:10 +0100 |
| Subject | Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 |
| Message-ID | <qqFLl-Gf-33@gated-at.bofh.it> |
| In reply to | #1261303 |
在 2015年11月03日 16:45, Arnd Bergmann 写道:
> On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote:
>> + /* Cortex-A12 Errata */
>> + ldr r10, =0x00000c0d @ Cortex-A12 primary part number
>> + teq r0, r10
>> + bne 5f
beq __ca15_errata:
>> +#ifdef CONFIG_ARM_ERRATA_818325
>> + teq r6, #0x00 @ present in r0p0
>> + teqne r6, #0x01 @ present in r0p1-00lac0-rc11
>> + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
>> + orreq r10, r10, #1 << 12 @ set bit #12
>> + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
>> + isb
>> +#endif
>> /* Cortex-A15 Errata */
>>
> Does this still build? You seem to have lost the '5:' label.
No, I didn't have build in next kernel.
Yup, the patch need a bit change from the message.
commit 17e7bf86690eaad4906d2295f0bd171cc194633b
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat Apr 4 21:34:33 2015 +0100
ARM: proc-v7: move CPU errata out of line
-----
Original patch:
https://patchwork.kernel.org/patch/4735341/
Applied and verified on kernel V3.14.
>
> Arnd
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Thanks,
Caesar
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| From | kbuild test robot <lkp@intel.com> |
|---|---|
| Date | 2015-11-03 11:30 +0100 |
| Subject | Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 |
| Message-ID | <qqH0K-1sK-13@gated-at.bofh.it> |
| In reply to | #1261276 |
[Multipart message — attachments visible in raw view] — view raw
Hi Huang,
[auto build test ERROR on mvebu/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
url: https://github.com/0day-ci/linux/commits/Caesar-Wang/ARM-errata-Workaround-for-Cortex-A12-erratum-818325/20151103-163417
config: arm-prima2_defconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
/tmp/ccjF0uyl.s: Assembler messages:
>> /tmp/ccjF0uyl.s: Error: local label `"5" (instance number 1 of a fb label)' is not defined
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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