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[PATCH 00/19] drm: Add Allwinner A10 display engine support

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  [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Chen-Yu Tsai <wens@csie.org> - 2015-10-30 16:30 +0100
        Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 20:40 +0100
    [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:30 +0100
        Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 23:20 +0100
    [PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 02/19] clk: sunxi: Add PLL3 clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:40 +0100
    [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Chen-Yu Tsai <wens@csie.org> - 2015-10-30 17:10 +0100
        Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Hans de Goede <hdegoede@redhat.com> - 2015-10-30 17:40 +0100
    [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2015-10-30 17:50 +0100
        Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Thierry Reding <thierry.reding@gmail.com> - 2015-10-30 18:40 +0100
          Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2015-11-01 15:40 +0100
        Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 23:40 +0100
    [PATCH 18/19] ARM: sun5i: r8: Add AHB gates to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output Jonathan Liu <net147@gmail.com> - 2015-11-02 04:00 +0100
        Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:40 +0100
    [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex  LCD-OLinuXino-4.3TS Thierry Reding <thierry.reding@gmail.com> - 2015-10-30 18:40 +0100
        Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex  LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:50 +0100
    [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 01/19] clk: sunxi: Add display clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:30 +0100
        Re: [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 00:40 +0100
          Re: [PATCH 01/19] clk: sunxi: Add display clock Stephen Boyd <sboyd@codeaurora.org> - 2015-11-12 21:40 +0100
      Re: [PATCH 01/19] clk: sunxi: Add display clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:30 +0100
        Re: [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 20:50 +0100
    [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Chen-Yu Tsai <wens@csie.org> - 2015-11-09 05:30 +0100
    [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:40 +0100
        Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:20 +0100
      Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:00 +0100
        Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:10 +0100
          Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Chen-Yu Tsai <wens@csie.org> - 2015-11-09 04:40 +0100
    [PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
      Re: [PATCH 05/19] clk: sunxi: add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2015-11-09 05:20 +0100
        Re: [PATCH 05/19] clk: sunxi: add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2015-11-13 09:10 +0100
    [PATCH 13/19] drm: sun4i: tv: Add NTSC output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
    Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter <daniel@ffwll.ch> - 2015-10-30 16:10 +0100
      Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-12 06:20 +0100
    Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Chen-Yu Tsai <wens@csie.org> - 2015-11-09 04:50 +0100
    Re: [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-11 23:20 +0100

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#1259525 — [PATCH 00/19] drm: Add Allwinner A10 display engine support

Hi everyone,

The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.

Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
example), and the output availables will change too (HDMI, composite,
VGA on the A20, none of them on the A13).

On most featured SoCs, it looks like that:

 +--------------------------------------------+
 |                    RAM                     |
 +--------------------------------------------+
       |            |      |            |
       v            |      |            v
 +----------------+ |      | +----------------+
 |    Frontend    | |      | |    Frontend    |
 +----------------+ |      | +----------------+
         |          |      |         |
         v          |      |         v
 +----------------+ |      | +----------------+
 |    Backend     |<+      +>|    Backend     |
 +----------------+          +----------------+
         |                           |
         v                           v
 +----------------+          +----------------+---> LVDS
 |      TCON      |          |      TCON      |---> RGB
 +----------------+          +----------------+
       |       +---+       +---+          |
       |           |       |              |
       v           v       v              v
 +------------+  +------------+  +------------+---> VGA
 | TV Encoder |  |    HDMI    |  | TV Encoder |---> Composite
 +------------+  +------------+  +------------+

The current code only assumes that there is a single instance of all
the controllers. It also supports only the RGB and Composite
interfaces.

A few more things are missing though, and will be supported
eventually:
  - Overscan support
  - Asynchronous page flip
  - Multiple plane support
  - Composite / VGA Hotplug detection
  - More outputs
  - Support for several videos pipelines

And there's one big gotcha: thhe code to parse the mode from the
kernel commandline doesn't seem to support named modes. Since we
expose the various TV standards through named modes, it means that
there's no way to use a particular standard to display something
during the kernel boot. The default will always be used, in other
words, PAL.

A few more questions that are probably going to be raised during the
review:
  - How do you associate private data to a mode, for example to deal
    with the non-generic, driver-specific settings required to deal
    with the various TV standards? drm_display_mode seems to have a
    private field, but it isn't always preserved.
  - How do you setup properties in the kernel command line? In order
    to have a decent display during boot on relevant interfaces, you
    probably want to setup the overscan beforehand. Overscan seems to
    be handled through properties, and afaik, there's no way to set
    that from the cmdline. Should we use a kernel parameter to set the
    default value instead?

Thanks!
Maxime

Maxime Ripard (19):
  clk: sunxi: Add display clock
  clk: sunxi: Add PLL3 clock
  clk: sunxi: Add TCON channel0 clock
  clk: sunxi: Add TCON channel1 clock
  clk: sunxi: add DRAM gates
  clk: sunxi: Add Allwinner R8 AHB gates support
  drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS
  drm: Add Allwinner A10 Display Engine support
  drm: sun4i: Add DT bindings documentation
  drm: sun4i: Add RGB output
  drm: sun4i: Add composite output
  drm: sun4i: tv: Add PAL output standard
  drm: sun4i: tv: Add NTSC output standard
  ARM: sun5i: dt: Add pll3 and pll7 clocks
  ARM: sun5i: dt: Add display and TCON clocks
  ARM: sun5i: dt: Add DRAM gates
  ARM: sun5i: dt: Add display blocks to the DTSI
  ARM: sun5i: r8: Add AHB gates to the DTSI
  ARM: sun5i: chip: Enable the TV Encoder

 .../devicetree/bindings/drm/sunxi/sun4i-drm.txt    | 122 ++++
 arch/arm/boot/dts/sun5i-a10s.dtsi                  |   9 +-
 arch/arm/boot/dts/sun5i-a13.dtsi                   |   3 +-
 arch/arm/boot/dts/sun5i-r8.dtsi                    |  46 +-
 arch/arm/boot/dts/sun5i.dtsi                       | 137 +++++
 drivers/clk/sunxi/Makefile                         |   4 +
 drivers/clk/sunxi/clk-simple-gates.c               |   4 +
 drivers/clk/sunxi/clk-sun4i-display.c              | 199 +++++++
 drivers/clk/sunxi/clk-sun4i-pll3.c                 |  84 +++
 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c             | 173 ++++++
 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c             | 167 ++++++
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   3 +-
 drivers/gpu/drm/panel/panel-simple.c               |  26 +
 drivers/gpu/drm/sun4i/Kconfig                      |  14 +
 drivers/gpu/drm/sun4i/Makefile                     |  11 +
 drivers/gpu/drm/sun4i/sun4i_backend.c              | 271 +++++++++
 drivers/gpu/drm/sun4i/sun4i_backend.h              | 159 ++++++
 drivers/gpu/drm/sun4i/sun4i_crtc.c                 | 117 ++++
 drivers/gpu/drm/sun4i/sun4i_crtc.h                 |  31 ++
 drivers/gpu/drm/sun4i/sun4i_drv.c                  | 296 ++++++++++
 drivers/gpu/drm/sun4i/sun4i_drv.h                  |  30 +
 drivers/gpu/drm/sun4i/sun4i_framebuffer.c          |  54 ++
 drivers/gpu/drm/sun4i/sun4i_framebuffer.h          |  19 +
 drivers/gpu/drm/sun4i/sun4i_layer.c                | 111 ++++
 drivers/gpu/drm/sun4i/sun4i_layer.h                |  30 +
 drivers/gpu/drm/sun4i/sun4i_rgb.c                  | 243 ++++++++
 drivers/gpu/drm/sun4i/sun4i_rgb.h                  |  18 +
 drivers/gpu/drm/sun4i/sun4i_tcon.c                 | 478 ++++++++++++++++
 drivers/gpu/drm/sun4i/sun4i_tcon.h                 | 182 ++++++
 drivers/gpu/drm/sun4i/sun4i_tv.c                   | 619 +++++++++++++++++++++
 drivers/gpu/drm/sun4i/sun4i_tv.h                   |  18 +
 32 files changed, 3673 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
 create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c
 create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c
 create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
 create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
 create mode 100644 drivers/gpu/drm/sun4i/Kconfig
 create mode 100644 drivers/gpu/drm/sun4i/Makefile
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_backend.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_crtc.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_drv.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_framebuffer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_layer.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.h

-- 
2.6.2

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#1259527 — [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder

The TV encoder is used to drive VGA and composite display.

Enable it on the CHIP

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index d69df3a73cbf..e39c903da864 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -86,4 +86,16 @@
 					     "ahb_mali400";
 		};
 	};
+
+	soc@01c00000 {
+		tve: encoder@01c0a000 {
+			compatible = "allwinner,sun4i-a10-tv-encoder";
+			reg = <0x01c0a000 0x1000>;
+			clocks = <&ahb_gates 34>;
+		};
+	};
+};
+
+&de {
+	allwinner,tv-encoder = <&tve>;
 };
-- 
2.6.2

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#1259580 — Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder

On Fri, Oct 30, 2015 at 10:21 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The TV encoder is used to drive VGA and composite display.
>
> Enable it on the CHIP

The commit message does not match the contents. Missing a patch? :)

ChenYu

>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/boot/dts/sun5i-r8.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
> index d69df3a73cbf..e39c903da864 100644
> --- a/arch/arm/boot/dts/sun5i-r8.dtsi
> +++ b/arch/arm/boot/dts/sun5i-r8.dtsi
> @@ -86,4 +86,16 @@
>                                              "ahb_mali400";
>                 };
>         };
> +
> +       soc@01c00000 {
> +               tve: encoder@01c0a000 {
> +                       compatible = "allwinner,sun4i-a10-tv-encoder";
> +                       reg = <0x01c0a000 0x1000>;
> +                       clocks = <&ahb_gates 34>;
> +               };
> +       };
> +};
> +
> +&de {
> +       allwinner,tv-encoder = <&tve>;
>  };
> --
> 2.6.2
>
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#1264300 — Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder

[Multipart message — attachments visible in raw view] — view raw

Hi Chen-Yu,

On Fri, Oct 30, 2015 at 11:20:41PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 30, 2015 at 10:21 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The TV encoder is used to drive VGA and composite display.
> >
> > Enable it on the CHIP
> 
> The commit message does not match the contents. Missing a patch? :)

No, I changed the commit a bit, and forgot to update the message :)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1259528 — [PATCH 03/19] clk: sunxi: Add TCON channel0 clock

The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.

It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).

Add a driver for the channel 0 clock.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi/Makefile             |   1 +
 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c | 173 +++++++++++++++++++++++++++++++++
 2 files changed, 174 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 40c32ffd912c..7821b2b63d58 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun4i-display.o
 obj-y += clk-sun4i-pll3.o
+obj-y += clk-sun4i-tcon-ch0.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
new file mode 100644
index 000000000000..db10cfb94a1d
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define SUN4I_A10_TCON_CH0_PARENTS	4
+
+#define SUN4I_A10_TCON_CH0_GATE_BIT	31
+#define SUN4I_A10_TCON_CH0_RESET_SHIFT	29
+#define SUN4I_A10_TCON_CH0_MUX_MASK	3
+#define SUN4I_A10_TCON_CH0_MUX_SHIFT	24
+
+struct reset_data {
+	void __iomem			*reg;
+	spinlock_t			*lock;
+	struct reset_controller_dev	rcdev;
+};
+
+static DEFINE_SPINLOCK(sun4i_a10_tcon_ch0_lock);
+
+static int sun4i_a10_tcon_ch0_assert(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	struct reset_data *data = container_of(rcdev,
+					       struct reset_data,
+					       rcdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(data->lock, flags);
+
+	reg = readl(data->reg);
+	writel(reg & ~BIT(SUN4I_A10_TCON_CH0_RESET_SHIFT + id), data->reg);
+
+	spin_unlock_irqrestore(data->lock, flags);
+
+	return 0;
+}
+
+static int sun4i_a10_tcon_ch0_deassert(struct reset_controller_dev *rcdev,
+				       unsigned long id)
+{
+	struct reset_data *data = container_of(rcdev,
+						   struct reset_data,
+						   rcdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(data->lock, flags);
+
+	reg = readl(data->reg);
+	writel(reg | BIT(SUN4I_A10_TCON_CH0_RESET_SHIFT + id), data->reg);
+
+	spin_unlock_irqrestore(data->lock, flags);
+
+	return 0;
+}
+
+static int sun4i_a10_tcon_ch0_status(struct reset_controller_dev *rcdev,
+				     unsigned long id)
+{
+	struct reset_data *data = container_of(rcdev,
+					       struct reset_data,
+					       rcdev);
+
+	return !(readl(data->reg) & BIT(SUN4I_A10_TCON_CH0_RESET_SHIFT + id));
+}
+
+static struct reset_control_ops sun4i_a10_tcon_ch0_reset_ops = {
+	.assert		= sun4i_a10_tcon_ch0_assert,
+	.deassert	= sun4i_a10_tcon_ch0_deassert,
+	.status		= sun4i_a10_tcon_ch0_status,
+};
+
+static void __init sun4i_a10_tcon_ch0_setup(struct device_node *node)
+{
+	const char *parents[SUN4I_A10_TCON_CH0_PARENTS];
+	const char *clk_name = node->name;
+	struct reset_data *reset_data;
+	struct clk_gate *gate;
+	struct clk_mux *mux;
+	void __iomem *reg;
+	struct clk *clk;
+	int i;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("%s: Could not map the clock registers\n", clk_name);
+		return;
+	}
+
+	for (i = 0; i < SUN4I_A10_TCON_CH0_PARENTS; i++)
+		parents[i] = of_clk_get_parent_name(node, i);
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return;
+
+	mux->reg = reg;
+	mux->shift = SUN4I_A10_TCON_CH0_MUX_SHIFT;
+	mux->mask = SUN4I_A10_TCON_CH0_MUX_MASK;
+	mux->lock = &sun4i_a10_tcon_ch0_lock;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		goto free_mux;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_A10_TCON_CH0_GATE_BIT;
+	gate->lock = &sun4i_a10_tcon_ch0_lock;
+
+	clk = clk_register_composite(NULL, clk_name,
+				     parents, SUN4I_A10_TCON_CH0_PARENTS,
+				     &mux->hw, &clk_mux_ops,
+				     NULL, NULL,
+				     &gate->hw, &clk_gate_ops,
+				     0);
+	if (IS_ERR(clk)) {
+		pr_err("%s: Couldn't register the clock\n", clk_name);
+		goto free_gate;
+	}
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+	if (!reset_data)
+		goto free_clk;
+
+	reset_data->reg = reg;
+	reset_data->lock = &sun4i_a10_tcon_ch0_lock;
+	reset_data->rcdev.nr_resets = 2;
+	reset_data->rcdev.ops = &sun4i_a10_tcon_ch0_reset_ops;
+	reset_data->rcdev.of_node = node;
+
+	if (reset_controller_register(&reset_data->rcdev)) {
+		pr_err("%s: Couldn't register the reset controller\n",
+		       clk_name);
+		goto free_reset;
+	}
+
+	return;
+
+free_reset:
+	kfree(reset_data);
+free_clk:
+	clk_unregister(clk);
+free_gate:
+	kfree(gate);
+free_mux:
+	kfree(mux);
+}
+
+CLK_OF_DECLARE(sun4i_a10_tcon_ch0, "allwinner,sun4i-a10-tcon-ch0-clk",
+	       sun4i_a10_tcon_ch0_setup);
-- 
2.6.2

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#1259967 — Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock

Hi,

On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the channel 0 clock.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi/Makefile             |   1 +
>  drivers/clk/sunxi/clk-sun4i-tcon-ch0.c | 173 +++++++++++++++++++++++++++++++++
>  2 files changed, 174 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 40c32ffd912c..7821b2b63d58 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
>  obj-y += clk-sun4i-display.o
>  obj-y += clk-sun4i-pll3.o
> +obj-y += clk-sun4i-tcon-ch0.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> new file mode 100644
> index 000000000000..db10cfb94a1d
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_A10_TCON_CH0_PARENTS     4
> +
> +#define SUN4I_A10_TCON_CH0_GATE_BIT    31
> +#define SUN4I_A10_TCON_CH0_RESET_SHIFT 29

This is sun5i specific.

A10s manual says bit 30 is the LCD reset, while bit 29 is the TV encoder reset.
A13/R8 don't mention TCON_CH0 clock. A10/A20 have no separate TV encoder reset.

Please rename the clock.

ChenYu

> +#define SUN4I_A10_TCON_CH0_MUX_MASK    3
> +#define SUN4I_A10_TCON_CH0_MUX_SHIFT   24
> +
> +struct reset_data {
> +       void __iomem                    *reg;
> +       spinlock_t                      *lock;
> +       struct reset_controller_dev     rcdev;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_tcon_ch0_lock);
> +
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#1264600 — Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Sat, Oct 31, 2015 at 06:19:59PM +0800, Chen-Yu Tsai wrote:
> > +#define SUN4I_A10_TCON_CH0_RESET_SHIFT 29
> 
> This is sun5i specific.
> 
> A10s manual says bit 30 is the LCD reset, while bit 29 is the TV
> encoder reset.  A13/R8 don't mention TCON_CH0 clock. A10/A20 have no
> separate TV encoder reset.
> 
> Please rename the clock.

This thing with the A10s is odd, the channel 0 is only used for the
LCD interface, and not the tv encoder (and both the A13 and R8 do have
a TCON).

But you're right, I've fixed it.

Thanks!
Maxime

-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1259530 — [PATCH 02/19] clk: sunxi: Add PLL3 clock

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi/Makefile         |  3 +-
 drivers/clk/sunxi/clk-sun4i-pll3.c | 84 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun4i-pll3.c

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a9e1a5885846..40c32ffd912c 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -9,8 +9,9 @@ obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
-obj-y += clk-sun4i-display.o
 obj-y += clk-simple-gates.o
+obj-y += clk-sun4i-display.o
+obj-y += clk-sun4i-pll3.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
 obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c b/drivers/clk/sunxi/clk-sun4i-pll3.c
new file mode 100644
index 000000000000..7ea178bf19fa
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-pll3.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define SUN4I_A10_PLL3_GATE_BIT	31
+#define SUN4I_A10_PLL3_DIV_WIDTH	7
+#define SUN4I_A10_PLL3_DIV_SHIFT	0
+
+static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
+
+static void __init sun4i_a10_pll3_setup(struct device_node *node)
+{
+	const char *clk_name = node->name, *parent;
+	struct clk_factor *mult;
+	struct clk_gate *gate;
+	void __iomem *reg;
+	struct clk *clk;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent = of_clk_get_parent_name(node, 0);
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("%s: Could not map the clock registers\n", clk_name);
+		return;
+	}
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return;
+
+	gate->reg = reg;
+	gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
+	gate->lock = &sun4i_a10_pll3_lock;
+
+	mult = kzalloc(sizeof(*mult), GFP_KERNEL);
+	if (!mult)
+		goto free_gate;
+
+	mult->reg = reg;
+	mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
+	mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
+	mult->lock = &sun4i_a10_pll3_lock;
+
+	clk = clk_register_composite(NULL, clk_name,
+				     &parent, 1,
+				     NULL, NULL,
+				     &mult->hw, &clk_factor_ops,
+				     &gate->hw, &clk_gate_ops,
+				     0);
+	if (IS_ERR(clk)) {
+		pr_err("%s: Couldn't register the clock\n", clk_name);
+		goto free_mult;
+	}
+
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+
+free_mult:
+	kfree(mult);
+free_gate:
+	kfree(gate);
+}
+
+CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
+	       sun4i_a10_pll3_setup);
-- 
2.6.2

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#1259803 — Re: [PATCH 02/19] clk: sunxi: Add PLL3 clock

On 10/30, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index a9e1a5885846..40c32ffd912c 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -9,8 +9,9 @@ obj-y += clk-a10-mod1.o
>  obj-y += clk-a10-pll2.o
>  obj-y += clk-a20-gmac.o
>  obj-y += clk-mod0.o
> -obj-y += clk-sun4i-display.o
>  obj-y += clk-simple-gates.o
> +obj-y += clk-sun4i-display.o

Put this in the right place in patch 1 please.

> +obj-y += clk-sun4i-pll3.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-pll3.c b/drivers/clk/sunxi/clk-sun4i-pll3.c
> new file mode 100644
> index 000000000000..7ea178bf19fa
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-pll3.c
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>

#include <linux/of.h> for of_property_read_string()

> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_A10_PLL3_GATE_BIT	31
[...]
> +
> +	clk = clk_register_composite(NULL, clk_name,
> +				     &parent, 1,
> +				     NULL, NULL,
> +				     &mult->hw, &clk_factor_ops,
> +				     &gate->hw, &clk_gate_ops,
> +				     0);
> +	if (IS_ERR(clk)) {
> +		pr_err("%s: Couldn't register the clock\n", clk_name);
> +		goto free_mult;
> +	}
> +
> +	of_clk_add_provider(node, of_clk_src_simple_get, clk);

I hope this doesn't fail.

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a Linux Foundation Collaborative Project
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#1259531 — [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support

The R8 has yet another array of gates for AHB. Let's add it to the list of
compatibles we can deal with.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi/clk-simple-gates.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index 5666c767fa14..e3190a8687a8 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -158,5 +158,7 @@ CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
 	       sun4i_a10_ahb_init);
 CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
 	       sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_r8_ahb, "allwinner,sun5i-r8-ahb-gates-clk",
+	       sun4i_a10_ahb_init);
 CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
 	       sun4i_a10_ahb_init);
-- 
2.6.2

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#1259601 — Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support

On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The R8 has yet another array of gates for AHB. Let's add it to the list of
> compatibles we can deal with.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi/clk-simple-gates.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> index 5666c767fa14..e3190a8687a8 100644
> --- a/drivers/clk/sunxi/clk-simple-gates.c
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -158,5 +158,7 @@ CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
>                sun4i_a10_ahb_init);
>  CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
>                sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun5i_r8_ahb, "allwinner,sun5i-r8-ahb-gates-clk",
> +              sun4i_a10_ahb_init);
>  CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
>                sun4i_a10_ahb_init);
> --
> 2.6.2
>

Please also update Documentation/devicetree/bindings/clock/sunxi.txt

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>
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#1259612 — Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support

Hi,

On 30-10-15 17:01, Chen-Yu Tsai wrote:
> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>> The R8 has yet another array of gates for AHB. Let's add it to the list of
>> compatibles we can deal with.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>>   drivers/clk/sunxi/clk-simple-gates.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> index 5666c767fa14..e3190a8687a8 100644
>> --- a/drivers/clk/sunxi/clk-simple-gates.c
>> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> @@ -158,5 +158,7 @@ CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
>>                 sun4i_a10_ahb_init);
>>   CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
>>                 sun4i_a10_ahb_init);
>> +CLK_OF_DECLARE(sun5i_r8_ahb, "allwinner,sun5i-r8-ahb-gates-clk",
>> +              sun4i_a10_ahb_init);
>>   CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
>>                 sun4i_a10_ahb_init);
>> --
>> 2.6.2
>>
>
> Please also update Documentation/devicetree/bindings/clock/sunxi.txt
>
> Otherwise,
>
> Acked-by: Chen-Yu Tsai <wens@csie.org>

I wonder if this patch really is a good idea. We've confirmation from
Allwinner that all of the sun5i SoCs are using the same die. Sure some
peripherals are not connected to the outside but it is still the same
die. This patch feels to me like it just grows the kernel and dts size
without serving any purpose.

Regards,

Hans
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#1259532 — [PATCH 09/19] drm: sun4i: Add DT bindings documentation

The display pipeline of the Allwinner A10 is involving several loosely
coupled components.

Add a documentation for the bindings.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 .../devicetree/bindings/drm/sunxi/sun4i-drm.txt    | 122 +++++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt

diff --git a/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
new file mode 100644
index 000000000000..dbdccef787b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
@@ -0,0 +1,122 @@
+Allwinner A10 Display Pipeline
+==============================
+
+The Allwinner A10 Display pipeline is composed of several components
+that are going to be documented below:
+
+TV Encoder
+----------
+
+The TV Encoder supports the composite and VGA output. It is one end of
+the pipeline.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
+ - reg: base address and size of memory-mapped region
+ - clocks: the clocks driving the TV encoder
+
+TCON
+----
+
+The TCON acts as a CRTC and encoder for RGB / LVDS interfaces.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tcon".
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the TCON. Three are needed:
+   - 'ahb': the interface clocks
+   - 'tcon-ch0': The clock driving the TCON channel 0
+   - 'tcon-ch1': The clock driving the TCON channel 0
+
+ - clock-names: the clock names mentionned above
+ - clock-output-names: Name of the pixel clock created
+
+
+Display Engine Backend
+----------------------
+
+The display engine backend exposes layers and sprites to the
+system. It's split into two components, the frontend and backend, the
+frontend doing formats conversion, scaling, deinterlacing, while the
+backend actually manages the layers.
+
+Required properties:
+  - compatible: value must be one of:
+    * allwinner,sun5i-a13-display-engine
+
+  - reg: base address and size of the memory-mapped region. Two are needed:
+    * backend0: registers of the display engine backend
+    * frontend0: registers of the display engine frontend
+  - reg_names: the region names mentionned above.
+
+  - interrupts: frontend interrupt phandle
+
+  - clocks: phandles to the clocks feeding the frontend and backend
+    * backend0-bus: the backend interface clock
+    * backend0-mod: the backend module clock
+    * backend0-ram: the backend DRAM clock
+    * frontend0-bus: the frontend interface clock
+    * frontend0-mod: the frontend module clock
+    * frontend0-ram: the frontend DRAM clock
+  - clock-names: the clock names mentionned above
+
+  - resets: phandles to the reset controllers. Two are needed:
+    * backend0: backend reset controller
+    * frontend0: frontend reset controller
+  - reset-names: the reset names mentionned above
+
+  - allwinner,tcon: phandle to the TCON in our pipeline
+
+Optional properties:
+  - allwinner,tv-encoder: phandle to the TV Encoder in our pipeline
+  - allwinner,panel: phandle to the panel used in our RGB interface
+
+Example:
+
+panel: panel {
+	compatible = "olimex,lcd-olinuxino-43-ts";
+};
+
+tve: encoder@01c0a000 {
+	compatible = "allwinner,sun4i-a10-tv-encoder";
+	reg = <0x01c0a000 0x1000>;
+	clocks = <&ahb_gates 34>;
+};
+
+tcon: lcd-controller@01c0c000 {
+	compatible = "allwinner,sun4i-a10-tcon";
+	reg = <0x01c0c000 0x1000>;
+	interrupts = <44>;
+	clocks = <&ahb_gates 36>,
+		 <&tcon_ch0_clk>,
+		 <&tcon_ch1_clk>;
+	clock-names = "ahb",
+		      "tcon-ch0",
+		      "tcon-ch1";
+	clock-output-names = "tcon-pixel-clock";
+};
+
+de: display-engine@01e00000 {
+	compatible = "allwinner,sun5i-a13-display-engine";
+	reg = <0x01e00000 0x20000>,
+	      <0x01e60000 0x10000>;
+	reg-names = "frontend0",
+		    "backend0";
+	interrupts = <47>;
+	interrupt-names = "engine0";
+	clocks = <&ahb_gates 46>, <&de_fe_clk>,
+		 <&dram_gates 25>, <&ahb_gates 44>,
+		 <&de_be_clk>, <&dram_gates 26>;
+	clock-names = "frontend0-bus", "frontend0-mod",
+		      "frontend0-ram", "backend0-bus",
+		      "backend0-mod", "backend0-ram";
+	resets = <&de_fe_clk>,
+		 <&de_be_clk>;
+	reset-names = "frontend0",
+		      "backend0";
+
+	allwinner,tcon = <&tcon>;
+	allwinner,tv-encoder = <&tve>;
+	allwinner,panel = <&panel>;
+};
-- 
2.6.2

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#1259623 — Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation

On Fri, Oct 30, 2015 at 9:20 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The display pipeline of the Allwinner A10 is involving several loosely
> coupled components.
>
> Add a documentation for the bindings.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  .../devicetree/bindings/drm/sunxi/sun4i-drm.txt    | 122 +++++++++++++++++++++

bindings/display/sunxi/ please.

>  1 file changed, 122 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
>
> diff --git a/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
> new file mode 100644
> index 000000000000..dbdccef787b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt
> @@ -0,0 +1,122 @@
> +Allwinner A10 Display Pipeline
> +==============================
> +
> +The Allwinner A10 Display pipeline is composed of several components
> +that are going to be documented below:
> +
> +TV Encoder
> +----------
> +
> +The TV Encoder supports the composite and VGA output. It is one end of
> +the pipeline.
> +
> +Required properties:
> + - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
> + - reg: base address and size of memory-mapped region
> + - clocks: the clocks driving the TV encoder
> +
> +TCON
> +----
> +
> +The TCON acts as a CRTC and encoder for RGB / LVDS interfaces.

Lets not carry DRMs old CRTC name into DT bindings. Just say "display
controller."

> +
> +Required properties:
> + - compatible: value should be "allwinner,sun4i-a10-tcon".
> + - reg: base address and size of memory-mapped region
> + - interrupts: interrupt associated to this IP
> + - clocks: phandles to the clocks feeding the TCON. Three are needed:
> +   - 'ahb': the interface clocks
> +   - 'tcon-ch0': The clock driving the TCON channel 0
> +   - 'tcon-ch1': The clock driving the TCON channel 0
> +
> + - clock-names: the clock names mentionned above

typo

> + - clock-output-names: Name of the pixel clock created
> +
> +
> +Display Engine Backend
> +----------------------
> +
> +The display engine backend exposes layers and sprites to the
> +system. It's split into two components, the frontend and backend, the
> +frontend doing formats conversion, scaling, deinterlacing, while the
> +backend actually manages the layers.
> +
> +Required properties:
> +  - compatible: value must be one of:
> +    * allwinner,sun5i-a13-display-engine
> +
> +  - reg: base address and size of the memory-mapped region. Two are needed:
> +    * backend0: registers of the display engine backend
> +    * frontend0: registers of the display engine frontend

Why the zeros? I think they should be dropped.

> +  - reg_names: the region names mentionned above.

typo

> +
> +  - interrupts: frontend interrupt phandle
> +
> +  - clocks: phandles to the clocks feeding the frontend and backend
> +    * backend0-bus: the backend interface clock
> +    * backend0-mod: the backend module clock
> +    * backend0-ram: the backend DRAM clock
> +    * frontend0-bus: the frontend interface clock
> +    * frontend0-mod: the frontend module clock
> +    * frontend0-ram: the frontend DRAM clock

Same comment on zeros.

> +  - clock-names: the clock names mentionned above

typo

> +
> +  - resets: phandles to the reset controllers. Two are needed:
> +    * backend0: backend reset controller
> +    * frontend0: frontend reset controller
> +  - reset-names: the reset names mentionned above

typo. At least you are consistent (unlike English grammar rules). ;)

> +
> +  - allwinner,tcon: phandle to the TCON in our pipeline

Use of-graph or just let the relationship live in the driver. If there
is only 1 instance of the blocks, the latter is fine.

> +
> +Optional properties:
> +  - allwinner,tv-encoder: phandle to the TV Encoder in our pipeline
> +  - allwinner,panel: phandle to the panel used in our RGB interface

Use of-graph please.

> +
> +Example:
> +
> +panel: panel {
> +       compatible = "olimex,lcd-olinuxino-43-ts";
> +};
> +
> +tve: encoder@01c0a000 {
> +       compatible = "allwinner,sun4i-a10-tv-encoder";
> +       reg = <0x01c0a000 0x1000>;
> +       clocks = <&ahb_gates 34>;
> +};
> +
> +tcon: lcd-controller@01c0c000 {
> +       compatible = "allwinner,sun4i-a10-tcon";
> +       reg = <0x01c0c000 0x1000>;
> +       interrupts = <44>;
> +       clocks = <&ahb_gates 36>,
> +                <&tcon_ch0_clk>,
> +                <&tcon_ch1_clk>;
> +       clock-names = "ahb",
> +                     "tcon-ch0",
> +                     "tcon-ch1";
> +       clock-output-names = "tcon-pixel-clock";
> +};
> +
> +de: display-engine@01e00000 {
> +       compatible = "allwinner,sun5i-a13-display-engine";
> +       reg = <0x01e00000 0x20000>,
> +             <0x01e60000 0x10000>;
> +       reg-names = "frontend0",
> +                   "backend0";
> +       interrupts = <47>;
> +       interrupt-names = "engine0";
> +       clocks = <&ahb_gates 46>, <&de_fe_clk>,
> +                <&dram_gates 25>, <&ahb_gates 44>,
> +                <&de_be_clk>, <&dram_gates 26>;
> +       clock-names = "frontend0-bus", "frontend0-mod",
> +                     "frontend0-ram", "backend0-bus",
> +                     "backend0-mod", "backend0-ram";
> +       resets = <&de_fe_clk>,
> +                <&de_be_clk>;
> +       reset-names = "frontend0",
> +                     "backend0";
> +
> +       allwinner,tcon = <&tcon>;
> +       allwinner,tv-encoder = <&tve>;
> +       allwinner,panel = <&panel>;
> +};
> --
> 2.6.2
>
> --
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#1259664 — Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation

[Multipart message — attachments visible in raw view] — view raw

On Fri, Oct 30, 2015 at 11:40:03AM -0500, Rob Herring wrote:
> On Fri, Oct 30, 2015 at 9:20 AM, Maxime Ripard
[...]
> > +Optional properties:
> > +  - allwinner,tv-encoder: phandle to the TV Encoder in our pipeline
> > +  - allwinner,panel: phandle to the panel used in our RGB interface
> 
> Use of-graph please.

Why? Panels are a really simple resource and a simple phandle is fully
capable of describing the relationship.

Thierry

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#1260171 — Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation

On Fri, Oct 30, 2015 at 12:37 PM, Thierry Reding
<thierry.reding@gmail.com> wrote:
> On Fri, Oct 30, 2015 at 11:40:03AM -0500, Rob Herring wrote:
>> On Fri, Oct 30, 2015 at 9:20 AM, Maxime Ripard
> [...]
>> > +Optional properties:
>> > +  - allwinner,tv-encoder: phandle to the TV Encoder in our pipeline
>> > +  - allwinner,panel: phandle to the panel used in our RGB interface
>>
>> Use of-graph please.
>
> Why? Panels are a really simple resource and a simple phandle is fully
> capable of describing the relationship.

So we can have some consistency in bindings and common parsing code.
It is simple when it is just a panel, but when it can be tv-encoder or
other board level downstream bridge devices it doesn't stay so simple.
Also, we already have a simple way to do panels which is as a child
node. Let's not have a third way.

Rob
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#1264620 — Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation

[Multipart message — attachments visible in raw view] — view raw

Hi Rob,

On Fri, Oct 30, 2015 at 11:40:03AM -0500, Rob Herring wrote:
> > +Display Engine Backend
> > +----------------------
> > +
> > +The display engine backend exposes layers and sprites to the
> > +system. It's split into two components, the frontend and backend, the
> > +frontend doing formats conversion, scaling, deinterlacing, while the
> > +backend actually manages the layers.
> > +
> > +Required properties:
> > +  - compatible: value must be one of:
> > +    * allwinner,sun5i-a13-display-engine
> > +
> > +  - reg: base address and size of the memory-mapped region. Two are needed:
> > +    * backend0: registers of the display engine backend
> > +    * frontend0: registers of the display engine frontend
> 
> Why the zeros? I think they should be dropped.

We have SoCs that have two backends and two frontends, hence why I
added 0. I guess I can also add several devices for them, but then I'd
need to move to the component framework I guess (which was the plan anyway).

> > +
> > +  - allwinner,tcon: phandle to the TCON in our pipeline
> 
> Use of-graph or just let the relationship live in the driver. If there
> is only 1 instance of the blocks, the latter is fine.

We can also have several TCON instances in the SoC, and even though
you can on a theorical point of view use any TCON with any backend,
usually you're tied because of how the pins are routed on the boards.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1259533 — [PATCH 18/19] ARM: sun5i: r8: Add AHB gates to the DTSI

Add the gates definition to the R8 DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 691d3de75b35..d69df3a73cbf 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -57,4 +57,33 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		ahb_gates: clk@01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun5i-r8-ahb-gates-clk";
+			reg = <0x01c20060 0x8>;
+			clocks = <&ahb>;
+			clock-indices = <0>, <1>,
+					<2>, <5>, <6>,
+					<7>, <8>, <9>,
+					<10>, <13>,
+					<14>, <20>,
+					<21>, <22>,
+					<28>, <32>, <34>,
+					<36>, <40>, <44>,
+					<46>, <51>,
+					<52>;
+			clock-output-names = "ahb_usbotg", "ahb_ehci",
+					     "ahb_ohci", "ahb_ss", "ahb_dma",
+					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+					     "ahb_mmc2", "ahb_nand",
+					     "ahb_sdram", "ahb_spi0",
+					     "ahb_spi1", "ahb_spi2",
+					     "ahb_stimer", "ahb_ve", "ahb_tve",
+					     "ahb_lcd", "ahb_csi", "ahb_de_be",
+					     "ahb_de_fe", "ahb_iep",
+					     "ahb_mali400";
+		};
+	};
 };
-- 
2.6.2

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#1259534 — [PATCH 12/19] drm: sun4i: tv: Add PAL output standard

Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_tv.c | 42 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index dc55e340410c..4b95d04ff457 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -175,7 +175,49 @@ struct sun4i_tv {
 	struct sun4i_drv	*drv;
 };
 
+struct video_levels pal_video_levels = {
+	.black = 252,	.blank = 252,
+};
+
+struct burst_levels pal_burst_levels = {
+	.cb = 40,	.cr = 40,
+};
+
+struct color_gains pal_color_gains = {
+	.cb = 224,	.cr = 224,
+};
+
+struct resync_parameters pal_resync_parameters = {
+	.field = true,	.line = 13,	.pixel = 12,
+};
+
 struct tv_mode tv_modes[] = {
+	{
+		.name		= "PAL",
+		.mode		= SUN4I_TVE_CFG0_RES_576i,
+		.chroma_freq	= 0x2a098acb,
+
+		.back_porch	= 138,
+		.front_porch	= 24,
+		.line_number	= 625,
+
+		.hdisplay	= 720,
+		.hfront_porch	= 3,
+		.hsync_len	= 2,
+		.hback_porch	= 139,
+
+		.vdisplay	= 576,
+		.vfront_porch	= 28,
+		.vsync_len	= 2,
+		.vback_porch	= 19,
+
+		.vblank_level	= 252,
+
+		.color_gains	= &pal_color_gains,
+		.burst_levels	= &pal_burst_levels,
+		.video_levels	= &pal_video_levels,
+		.resync_params	= &pal_resync_parameters,
+	},
 };
 
 static inline struct sun4i_tv *
-- 
2.6.2

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#1259535 — [PATCH 10/19] drm: sun4i: Add RGB output

One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/Makefile    |   2 +
 drivers/gpu/drm/sun4i/sun4i_drv.c |   9 +-
 drivers/gpu/drm/sun4i/sun4i_rgb.c | 243 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/sun4i/sun4i_rgb.h |  18 +++
 4 files changed, 271 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_rgb.h

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index bc2df12beb42..4d230b658a05 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -5,4 +5,6 @@ sun4i-drm-y += sun4i_framebuffer.o
 sun4i-drm-y += sun4i_layer.o
 sun4i-drm-y += sun4i_tcon.o
 
+sun4i-drm-y += sun4i_rgb.o
+
 obj-$(CONFIG_DRM_SUN4I)		+= sun4i-drm.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fc26f3903f52..f2c9c8a2eb75 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -20,6 +20,7 @@
 #include "sun4i_drv.h"
 #include "sun4i_framebuffer.h"
 #include "sun4i_layer.h"
+#include "sun4i_rgb.h"
 #include "sun4i_tcon.h"
 
 static void sun4i_drv_preclose(struct drm_device *drm,
@@ -127,13 +128,18 @@ static int sun4i_drv_load(struct drm_device *drm, unsigned long flags)
 	}
 
 	/* Create our outputs */
+	ret = sun4i_rgb_init(drm);
+	if (ret) {
+		dev_err(drm->dev, "Couldn't create our RGB output\n");
+		goto err_free_crtc;
+	}
 
 	/* Create our framebuffer */
 	drv->fbdev = sun4i_framebuffer_init(drm);
 	if (IS_ERR(drv->fbdev)) {
 		dev_err(drm->dev, "Couldn't create our framebuffer\n");
 		ret = PTR_ERR(drv->fbdev);
-		goto err_free_crtc;
+		goto err_free_rgb;
 	}
 
 	/* Enable connectors polling */
@@ -141,6 +147,7 @@ static int sun4i_drv_load(struct drm_device *drm, unsigned long flags)
 
 	return 0;
 
+err_free_rgb:
 err_free_crtc:
 err_free_layers:
 err_free_tcon:
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
new file mode 100644
index 000000000000..426b16b26aec
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+struct sun4i_rgb {
+	struct drm_connector	connector;
+	struct drm_encoder	encoder;
+	struct drm_panel	*panel;
+
+	struct sun4i_drv	*drv;
+
+	bool			enabled;
+};
+
+static inline struct sun4i_rgb *
+drm_connector_to_sun4i_rgb(struct drm_connector *connector)
+{
+	return container_of(connector, struct sun4i_rgb,
+			    connector);
+}
+
+static inline struct sun4i_rgb *
+drm_encoder_to_sun4i_rgb(struct drm_encoder *encoder)
+{
+	return container_of(encoder, struct sun4i_rgb,
+			    encoder);
+}
+
+static int sun4i_rgb_get_modes(struct drm_connector *connector)
+{
+	struct sun4i_rgb *rgb =
+		drm_connector_to_sun4i_rgb(connector);
+
+	return rgb->panel->funcs->get_modes(rgb->panel);
+}
+
+static int sun4i_rgb_mode_valid(struct drm_connector *connector,
+				struct drm_display_mode *mode)
+{
+	DRM_DEBUG_DRIVER("Validating modes...\n");
+
+	if ((mode->hsync_start < 1) || (mode->hsync_start > 0x3ff) ||
+	    (mode->htotal < 1) || (mode->htotal > 0xfff))
+		return MODE_H_ILLEGAL;
+
+	DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
+
+	if ((mode->vsync_start < 1) || (mode->vsync_start > 0x3ff) ||
+	    (mode->vtotal < 1) || (mode->vtotal > 0xfff))
+		return MODE_V_ILLEGAL;
+
+	DRM_DEBUG_DRIVER("Vertical parameters OK\n");
+
+	return MODE_OK;
+}
+
+static struct drm_encoder *
+sun4i_rgb_best_encoder(struct drm_connector *connector)
+{
+	struct sun4i_rgb *rgb =
+		drm_connector_to_sun4i_rgb(connector);
+
+	return &rgb->encoder;
+}
+
+static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
+	.get_modes	= sun4i_rgb_get_modes,
+	.mode_valid	= sun4i_rgb_mode_valid,
+	.best_encoder	= sun4i_rgb_best_encoder,
+};
+
+static enum drm_connector_status
+sun4i_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void
+sun4i_rgb_connector_destroy(struct drm_connector *connector)
+{
+	struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
+
+	drm_panel_detach(rgb->panel);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs sun4i_rgb_con_funcs = {
+	.dpms			= drm_atomic_helper_connector_dpms,
+	.detect			= sun4i_rgb_connector_detect,
+	.fill_modes		= drm_helper_probe_single_connector_modes,
+	.destroy		= sun4i_rgb_connector_destroy,
+	.reset			= drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
+};
+
+static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
+{
+	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
+	struct sun4i_drv *drv = rgb->drv;
+	struct sun4i_tcon *tcon = drv->tcon;
+
+	if (rgb->enabled)
+		return;
+
+	DRM_DEBUG_DRIVER("Enabling RGB output\n");
+
+	drm_panel_enable(rgb->panel);
+	sun4i_tcon_enable_channel(tcon, 0);
+
+	rgb->enabled = true;
+}
+
+static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
+{
+	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
+	struct sun4i_drv *drv = rgb->drv;
+	struct sun4i_tcon *tcon = drv->tcon;
+
+	if (!rgb->enabled)
+		return;
+
+	DRM_DEBUG_DRIVER("Disabling RGB output\n");
+
+	sun4i_tcon_disable_channel(tcon, 0);
+	drm_panel_disable(rgb->panel);
+
+	rgb->enabled = false;
+}
+
+static bool sun4i_rgb_encoder_mode_fixup(struct drm_encoder *encoder,
+					 const struct drm_display_mode *mode,
+					 struct drm_display_mode *adjusted)
+{
+	return true;
+}
+
+static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
+				       struct drm_display_mode *mode,
+				       struct drm_display_mode *adjusted_mode)
+{
+	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
+	struct sun4i_drv *drv = rgb->drv;
+	struct sun4i_tcon *tcon = drv->tcon;
+
+	sun4i_tcon0_mode_set(tcon, mode);
+
+	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+}
+
+static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
+	.mode_fixup	= sun4i_rgb_encoder_mode_fixup,
+	.mode_set	= sun4i_rgb_encoder_mode_set,
+	.disable	= sun4i_rgb_encoder_disable,
+	.enable		= sun4i_rgb_encoder_enable,
+};
+
+static void sun4i_rgb_enc_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs sun4i_rgb_enc_funcs = {
+	.destroy	= sun4i_rgb_enc_destroy,
+};
+
+int sun4i_rgb_init(struct drm_device *drm)
+{
+	struct sun4i_drv *drv = drm->dev_private;
+	struct sun4i_rgb *rgb;
+	struct device_node *np;
+	int ret;
+
+	rgb = devm_kzalloc(drm->dev, sizeof(*rgb), GFP_KERNEL);
+	if (!rgb)
+		return -ENOMEM;
+	rgb->drv = drv;
+
+	np = of_parse_phandle(drm->dev->of_node, "allwinner,panel", 0);
+	if (!np) {
+		dev_err(drm->dev, "Couldn't find our panel DT node\n");
+		return -ENODEV;
+	}
+
+	rgb->panel = of_drm_find_panel(np);
+	if (!rgb->panel) {
+		dev_err(drm->dev, "Couldn't find our panel\n");
+		return -EPROBE_DEFER;
+	}
+
+	drm_encoder_helper_add(&rgb->encoder,
+			       &sun4i_rgb_enc_helper_funcs);
+	ret = drm_encoder_init(drm,
+			       &rgb->encoder,
+			       &sun4i_rgb_enc_funcs,
+			       DRM_MODE_ENCODER_NONE);
+	if (ret) {
+		dev_err(drm->dev, "Couldn't initialise the rgb encoder\n");
+		goto err_out;
+	}
+
+	/* The RGB encoder can only work with the TCON channel 0 */
+	rgb->encoder.possible_crtcs = BIT(0);
+
+	drm_connector_helper_add(&rgb->connector,
+				 &sun4i_rgb_con_helper_funcs);
+	ret = drm_connector_init(drm, &rgb->connector,
+				 &sun4i_rgb_con_funcs,
+				 DRM_MODE_CONNECTOR_Unknown);
+	if (ret) {
+		dev_err(drm->dev, "Couldn't initialise the rgb connector\n");
+		goto err_cleanup_connector;
+	}
+
+	drm_mode_connector_attach_encoder(&rgb->connector, &rgb->encoder);
+
+	drm_panel_attach(rgb->panel, &rgb->connector);
+
+	return 0;
+
+err_cleanup_connector:
+	drm_encoder_cleanup(&rgb->encoder);
+err_out:
+	return ret;
+}
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.h b/drivers/gpu/drm/sun4i/sun4i_rgb.h
new file mode 100644
index 000000000000..7c4da4c8acdd
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _SUN4I_RGB_H_
+#define _SUN4I_RGB_H_
+
+int sun4i_rgb_init(struct drm_device *drm);
+
+#endif /* _SUN4I_RGB_H_ */
-- 
2.6.2

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