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[PATCH 0/3] tip-queue 2015-10-30

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  [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov <bp@alien8.de> - 2015-10-30 13:20 +0100
    [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov <bp@alien8.de> - 2015-10-30 13:20 +0100
    [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov <bp@alien8.de> - 2015-10-30 13:20 +0100

#1259460 — [PATCH 0/3] tip-queue 2015-10-30

From: Borislav Petkov <bp@suse.de>

Hi Ingo,

please queue those non-critical platform enablement patches.

Thanks.

Aravind Gopalakrishnan (1):
  x86/mce: Add a Scalable MCA vendor flags bit

Borislav Petkov (1):
  x86/mce: Add a default case to the switch in
    __mcheck_cpu_ancient_init()

Wan Zongshun (1):
  x86/cpu: Add CLZERO detection

 arch/x86/include/asm/cpufeature.h |  5 ++++-
 arch/x86/include/asm/mce.h        | 34 +++++++++++++++++++++-------------
 arch/x86/kernel/cpu/common.c      |  1 +
 arch/x86/kernel/cpu/mcheck/mce.c  |  4 ++++
 4 files changed, 30 insertions(+), 14 deletions(-)

-- 
2.3.5

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#1259461 — [PATCH 3/3] x86/cpu: Add CLZERO detection

From: Wan Zongshun <Vincent.Wan@amd.com>

AMD Fam17h processors introduce support for the CLZERO instruction. It
zeroes out the 64 byte cache line specified in RAX.

Add the bit here to allow /proc/cpuinfo to list the feature.

Boris: we're adding this as a separate ->x86_capability leaf because
CPUID_80000008_EBX is going to contain more feature bits and it will
fill out with time.

Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1446059010-28010-3-git-send-email-Aravind.Gopalakrishnan@amd.com
[Wrap code in patch form, fix comments. ]
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/include/asm/cpufeature.h | 5 ++++-
 arch/x86/kernel/cpu/common.c      | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 9727b3b48bd1..e4f8010f22e0 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
 #include <asm/disabled-features.h>
 #endif
 
-#define NCAPINTS	13	/* N 32-bit words worth of info */
+#define NCAPINTS	14	/* N 32-bit words worth of info */
 #define NBUGINTS	1	/* N 32-bit bug flags */
 
 /*
@@ -255,6 +255,9 @@
 /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
 #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
 
+/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index de22ea7ff82f..4ddd780aeac9 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 
 		c->x86_virt_bits = (eax >> 8) & 0xff;
 		c->x86_phys_bits = eax & 0xff;
+		c->x86_capability[13] = cpuid_ebx(0x80000008);
 	}
 #ifdef CONFIG_X86_32
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
-- 
2.3.5

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#1259464 — [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init()

From: Borislav Petkov <bp@suse.de>

Caught by building with W= which enable -Wswitch-default also.

Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index c7c59d13e3f4..78c6f8d65d58 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1586,6 +1586,8 @@ static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
 		winchip_mcheck_init(c);
 		return 1;
 		break;
+	default:
+		return 0;
 	}
 
 	return 0;
-- 
2.3.5

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