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Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options

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  Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Linus Walleij <linus.walleij@linaro.org> - 2015-10-27 17:10 +0100

#1256886 — Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options

On Fri, Oct 16, 2015 at 11:24 AM, Jon Hunter <jonathanh@nvidia.com> wrote:

> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
> documentation implies that all functions (pcie, usb3 and sata) can be
> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
> been confirmed that this is not the case and the mux'ing options much more
> limited. Unfortunately, the public documentation has not been updated to
> reflect this and so detail the actual mux'ing options here by function:
>
> Function:               Lanes:
> pcie1 x2:               pcie3, pcie4
> pcie1 x4:               pcie1, pcie2, pcie3, pcie4
> pcie2 x1 (option1):     pcie0
> pcie2 x1 (option2):     pcie2
> usb3 port 0:            pcie0
> usb3 port 1 (option 1): pcie1
> usb3 port 1 (option 2): sata0
> sata:                   sata0
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>

Patch applied with Stephen's ACK.

Yours,
Linus Walleij
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