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| Started by | Jon Hunter <jonathanh@nvidia.com> |
|---|---|
| First post | 2015-10-20 13:30 +0200 |
| Last post | 2015-10-23 09:30 +0200 |
| Articles | 5 — 2 participants |
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Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Jon Hunter <jonathanh@nvidia.com> - 2015-10-20 13:30 +0200
Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Stephen Warren <swarren@wwwdotorg.org> - 2015-10-20 18:10 +0200
Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Jon Hunter <jonathanh@nvidia.com> - 2015-10-20 20:10 +0200
Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Stephen Warren <swarren@wwwdotorg.org> - 2015-10-20 20:40 +0200
Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options Jon Hunter <jonathanh@nvidia.com> - 2015-10-23 09:30 +0200
| From | Jon Hunter <jonathanh@nvidia.com> |
|---|---|
| Date | 2015-10-20 13:30 +0200 |
| Subject | Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options |
| Message-ID | <qlDh8-2gq-1@gated-at.bofh.it> |
On 16/10/15 17:17, Stephen Warren wrote: > On 10/16/2015 03:24 AM, Jon Hunter wrote: >> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the >> Tegra124 >> documentation implies that all functions (pcie, usb3 and sata) can be >> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has >> been confirmed that this is not the case and the mux'ing options much >> more >> limited. Unfortunately, the public documentation has not been updated to >> reflect this and so detail the actual mux'ing options here by function: > > FWIW, there's better documentation of this in the Tegra210 TRM, although > the options have been expanded on that chip, so the docs don't entirely > apply to Tegra124. > >> Function: Lanes: >> pcie1 x2: pcie3, pcie4 >> pcie1 x4: pcie1, pcie2, pcie3, pcie4 >> pcie2 x1 (option1): pcie0 >> pcie2 x1 (option2): pcie2 >> usb3 port 0: pcie0 >> usb3 port 1 (option 1): pcie1 >> usb3 port 1 (option 2): sata0 >> sata: sata0 > > I think this change needs a DT binding change to go along with it. Can > you take a look at: > > http://www.spinics.net/lists/arm-kernel/msg449647.html > [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210 I took a look at the above and it looks fine to me. Do you want me to put the above info into the DT binding doc? I am not sure that we need to update the binding itself. Jon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Stephen Warren <swarren@wwwdotorg.org> |
|---|---|
| Date | 2015-10-20 18:10 +0200 |
| Message-ID | <qlHE5-fg-9@gated-at.bofh.it> |
| In reply to | #1251601 |
On 10/20/2015 05:28 AM, Jon Hunter wrote: > > On 16/10/15 17:17, Stephen Warren wrote: >> On 10/16/2015 03:24 AM, Jon Hunter wrote: >>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the >>> Tegra124 >>> documentation implies that all functions (pcie, usb3 and sata) can be >>> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has >>> been confirmed that this is not the case and the mux'ing options much >>> more >>> limited. Unfortunately, the public documentation has not been updated to >>> reflect this and so detail the actual mux'ing options here by function: >> >> FWIW, there's better documentation of this in the Tegra210 TRM, although >> the options have been expanded on that chip, so the docs don't entirely >> apply to Tegra124. >> >>> Function: Lanes: >>> pcie1 x2: pcie3, pcie4 >>> pcie1 x4: pcie1, pcie2, pcie3, pcie4 >>> pcie2 x1 (option1): pcie0 >>> pcie2 x1 (option2): pcie2 >>> usb3 port 0: pcie0 >>> usb3 port 1 (option 1): pcie1 >>> usb3 port 1 (option 2): sata0 >>> sata: sata0 >> >> I think this change needs a DT binding change to go along with it. Can >> you take a look at: >> >> http://www.spinics.net/lists/arm-kernel/msg449647.html >> [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210 > > I took a look at the above and it looks fine to me. Do you want me to > put the above info into the DT binding doc? I am not sure that we need > to update the binding itself. Hmm. I guess there /should/ be no need for the DT bindings to list out all the valid combinations; it should just say "go read the HW docs". Of course as you mentioned our HW docs aren't quite as complete as they should be in this area, but still solving that in the DT binding doc may not be the best approach. But then again, the DT binding doc already lists which functions are valid for which groups of pins, but perhaps that's more about understanding the structure of the binding than the HW. I guess I'll leave it up to you which way to go. Perhaps let's not pursue adding this to the binding doc until we get the PHY-per-lane changes in place or rejected or the two changes will conflict badly? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Jon Hunter <jonathanh@nvidia.com> |
|---|---|
| Date | 2015-10-20 20:10 +0200 |
| Message-ID | <qlJwe-2Yt-23@gated-at.bofh.it> |
| In reply to | #1251837 |
On 20/10/15 17:08, Stephen Warren wrote:
> On 10/20/2015 05:28 AM, Jon Hunter wrote:
>>
>> On 16/10/15 17:17, Stephen Warren wrote:
>>> On 10/16/2015 03:24 AM, Jon Hunter wrote:
>>>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the
>>>> Tegra124
>>>> documentation implies that all functions (pcie, usb3 and sata) can be
>>>> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However,
>>>> it has
>>>> been confirmed that this is not the case and the mux'ing options much
>>>> more
>>>> limited. Unfortunately, the public documentation has not been
>>>> updated to
>>>> reflect this and so detail the actual mux'ing options here by function:
>>>
>>> FWIW, there's better documentation of this in the Tegra210 TRM, although
>>> the options have been expanded on that chip, so the docs don't entirely
>>> apply to Tegra124.
>>>
>>>> Function: Lanes:
>>>> pcie1 x2: pcie3, pcie4
>>>> pcie1 x4: pcie1, pcie2, pcie3, pcie4
>>>> pcie2 x1 (option1): pcie0
>>>> pcie2 x1 (option2): pcie2
>>>> usb3 port 0: pcie0
>>>> usb3 port 1 (option 1): pcie1
>>>> usb3 port 1 (option 2): sata0
>>>> sata: sata0
>>>
>>> I think this change needs a DT binding change to go along with it. Can
>>> you take a look at:
>>>
>>> http://www.spinics.net/lists/arm-kernel/msg449647.html
>>> [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210
>>
>> I took a look at the above and it looks fine to me. Do you want me to
>> put the above info into the DT binding doc? I am not sure that we need
>> to update the binding itself.
>
> Hmm. I guess there /should/ be no need for the DT bindings to list out
> all the valid combinations; it should just say "go read the HW docs". Of
> course as you mentioned our HW docs aren't quite as complete as they
> should be in this area, but still solving that in the DT binding doc may
> not be the best approach. But then again, the DT binding doc already
> lists which functions are valid for which groups of pins, but perhaps
> that's more about understanding the structure of the binding than the HW.
I had thought about trying to put the options in the tegra124.dtsi, but
I am not sure if there is an easy way to do that without having ...
padctl@0,7009f000 {
...
padctl_option1: pinmux {
usb3 {...};
pcie {...};
sata {...};
};
padctl_option2: pinmux {
usb3 {...};
pcie {...};
sata {...};
};
...
padctl_optionN: pinmux {
usb3 {...};
pcie {...};
sata {...};
};
};
... that would be a long-ish list. Unless there is a better way to do it?
> I guess I'll leave it up to you which way to go. Perhaps let's not
> pursue adding this to the binding doc until we get the PHY-per-lane
> changes in place or rejected or the two changes will conflict badly?
That's fine with me. Are you ok with this patch as-is going upstream for
now?
Jon
--
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| From | Stephen Warren <swarren@wwwdotorg.org> |
|---|---|
| Date | 2015-10-20 20:40 +0200 |
| Message-ID | <qlJZg-3xM-13@gated-at.bofh.it> |
| In reply to | #1251933 |
On 10/20/2015 12:02 PM, Jon Hunter wrote:
>
> On 20/10/15 17:08, Stephen Warren wrote:
>> On 10/20/2015 05:28 AM, Jon Hunter wrote:
>>>
>>> On 16/10/15 17:17, Stephen Warren wrote:
>>>> On 10/16/2015 03:24 AM, Jon Hunter wrote:
>>>>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the
>>>>> Tegra124
>>>>> documentation implies that all functions (pcie, usb3 and sata) can be
>>>>> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However,
>>>>> it has
>>>>> been confirmed that this is not the case and the mux'ing options much
>>>>> more
>>>>> limited. Unfortunately, the public documentation has not been
>>>>> updated to
>>>>> reflect this and so detail the actual mux'ing options here by function:
>>>>
>>>> FWIW, there's better documentation of this in the Tegra210 TRM, although
>>>> the options have been expanded on that chip, so the docs don't entirely
>>>> apply to Tegra124.
>>>>
>>>>> Function: Lanes:
>>>>> pcie1 x2: pcie3, pcie4
>>>>> pcie1 x4: pcie1, pcie2, pcie3, pcie4
>>>>> pcie2 x1 (option1): pcie0
>>>>> pcie2 x1 (option2): pcie2
>>>>> usb3 port 0: pcie0
>>>>> usb3 port 1 (option 1): pcie1
>>>>> usb3 port 1 (option 2): sata0
>>>>> sata: sata0
>>>>
>>>> I think this change needs a DT binding change to go along with it. Can
>>>> you take a look at:
>>>>
>>>> http://www.spinics.net/lists/arm-kernel/msg449647.html
>>>> [PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210
>>>
>>> I took a look at the above and it looks fine to me. Do you want me to
>>> put the above info into the DT binding doc? I am not sure that we need
>>> to update the binding itself.
>>
>> Hmm. I guess there /should/ be no need for the DT bindings to list out
>> all the valid combinations; it should just say "go read the HW docs". Of
>> course as you mentioned our HW docs aren't quite as complete as they
>> should be in this area, but still solving that in the DT binding doc may
>> not be the best approach. But then again, the DT binding doc already
>> lists which functions are valid for which groups of pins, but perhaps
>> that's more about understanding the structure of the binding than the HW.
>
> I had thought about trying to put the options in the tegra124.dtsi, but
> I am not sure if there is an easy way to do that without having ...
>
> padctl@0,7009f000 {
> ...
>
> padctl_option1: pinmux {
> usb3 {...};
> pcie {...};
> sata {...};
> };
> padctl_option2: pinmux {
> usb3 {...};
> pcie {...};
> sata {...};
> };
> ...
> padctl_optionN: pinmux {
> usb3 {...};
> pcie {...};
> sata {...};
> };
> };
>
> ... that would be a long-ish list. Unless there is a better way to do it?
Well, you could break it down to N options per controller type or port
rather than all N global options which might simplify things a bit
(fewer combinatorics to worry about), but I expect it'd still be more
trouble than its worth. People designing HW are who actually care about
the set of valid options, and they're more likely to get that
information via talking to NV systems engineers rather than looking at
the DT binding.
>> I guess I'll leave it up to you which way to go. Perhaps let's not
>> pursue adding this to the binding doc until we get the PHY-per-lane
>> changes in place or rejected or the two changes will conflict badly?
>
> That's fine with me. Are you ok with this patch as-is going upstream for
> now?
Yes, the code change is fine as is.
--
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| From | Jon Hunter <jonathanh@nvidia.com> |
|---|---|
| Date | 2015-10-23 09:30 +0200 |
| Message-ID | <qmEXw-2U2-3@gated-at.bofh.it> |
| In reply to | #1251946 |
On 20/10/15 19:36, Stephen Warren wrote: > On 10/20/2015 12:02 PM, Jon Hunter wrote: >> >> On 20/10/15 17:08, Stephen Warren wrote: >>> On 10/20/2015 05:28 AM, Jon Hunter wrote: >>>> >>>> On 16/10/15 17:17, Stephen Warren wrote: >>>>> On 10/16/2015 03:24 AM, Jon Hunter wrote: >>>>>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the >>>>>> Tegra124 >>>>>> documentation implies that all functions (pcie, usb3 and sata) can be >>>>>> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, >>>>>> it has >>>>>> been confirmed that this is not the case and the mux'ing options much >>>>>> more >>>>>> limited. Unfortunately, the public documentation has not been >>>>>> updated to >>>>>> reflect this and so detail the actual mux'ing options here by >>>>>> function: >>>>> >>>>> FWIW, there's better documentation of this in the Tegra210 TRM, >>>>> although >>>>> the options have been expanded on that chip, so the docs don't >>>>> entirely >>>>> apply to Tegra124. >>>>> >>>>>> Function: Lanes: >>>>>> pcie1 x2: pcie3, pcie4 >>>>>> pcie1 x4: pcie1, pcie2, pcie3, pcie4 >>>>>> pcie2 x1 (option1): pcie0 >>>>>> pcie2 x1 (option2): pcie2 >>>>>> usb3 port 0: pcie0 >>>>>> usb3 port 1 (option 1): pcie1 >>>>>> usb3 port 1 (option 2): sata0 >>>>>> sata: sata0 [snip] >> That's fine with me. Are you ok with this patch as-is going upstream for >> now? > > Yes, the code change is fine as is. Care to ACK this so Linus can pick it up? Cheers Jon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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