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[PATCH v4 0/5] iommu/arm-smmu: add support for non-pci devices

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  [PATCH v4 0/5] iommu/arm-smmu: add support for non-pci devices Zhen Lei <thunder.leizhen@huawei.com> - 2015-10-15 10:50 +0200
    [PATCH v4 1/5] iommu/arm-smmu: to support probe deferral Zhen Lei <thunder.leizhen@huawei.com> - 2015-10-15 10:50 +0200
    [PATCH v4 3/5] iommu/arm-smmu: add support for non-pci devices Zhen Lei <thunder.leizhen@huawei.com> - 2015-10-15 10:50 +0200
    [PATCH v4 5/5] iommu/arm-smmu: describe the limitation of #iommu-cells Zhen Lei <thunder.leizhen@huawei.com> - 2015-10-15 10:50 +0200

#1247573 — [PATCH v4 0/5] iommu/arm-smmu: add support for non-pci devices

Hi, all:

It's been a long time since my patch v3. I don't known when Laurent's
probe-deferral series will be upstreamed? I really have no time to wait. So
I add patch 4/5, to keep both cases(Laurent's series upstreamed or not),
smmu-v3 can always work well.


Changelog:
v3 -> v4:
1. base upon the lastest arm-smmu-v3.c update patchset.
2. add patch 4/5, keep smmu-v3 can still work normally before Laurent's series upstreamed.

   Describe process flow as below:
   All: (A-->B means: function A directly or indirectly call function B)
   [1] of_iommu_init-->arm_smmu_of_iommu_init-->of_iommu_set_ops

   1) without Laurent's series
   [1] of_platform_populate-->of_dma_configure-->of_iommu_configure-->.of_xlate
   	/* time before step [2], so smmu is NULL yet */
   	smmu = platform_get_drvdata(pdev);
	if (!smmu) {
		dev->archdata.iommu = ERR_PTR(-EPROBE_DEFER);

		return -EPROBE_DEFER;
	}
   [2] arm_smmu_device_dt_probe-->platform_set_drvdata
   [3] call .add_device
   	if (dev->archdata.iommu == ERR_PTR(-EPROBE_DEFER)) {
		dev->archdata.iommu = NULL;

		/* scan master's "iommus" property */
		return of_iommu_configure(dev, dev->of_node) ? 0 : -ENODEV;
	}
   [4] call master's probe function

   2) with Laurent's series
   [1] of_platform_populate-->of_dma_configure
   	the call of of_iommu_configure have been putted off, see [4] below
   	so the value of dev->archdata.iommu have no change
   [2] arm_smmu_device_dt_probe-->platform_set_drvdata
   [3] call .add_device
   	if (dev->archdata.iommu == ERR_PTR(-EPROBE_DEFER)) {
		/* see [1], dev->archdata.iommu is NULL, so this branch can not be entered */
	}
   [4] call .of_xlate
   [5] call master's probe function

v2 -> v3:
1. add support for pci device hotplug, which missed in patch v2.
2. only support #iommu-cells = <1>, add corresponding description in arm,smmu-v3.txt.
3. add function find_smmu_by_device which extracted from find_smmu_by_node, to resolve
   the problem mentioned by Robin Murphy in [PATCH v2 7/9].
   Additionally:
   +    platform_set_drvdata(pdev, smmu);       //Patch v2
   +	dev->archdata.iommu = smmu;             //Patch v3, dev = &pdev->dev

v1 -> v2:
update the implementation of patch 1/9 according to Will Deacon's suggestion.
update the comment of patch 3/9 and 4/9.
use arm_smmu_options to skip the execution of command CMD_PREFETCH_CONFIG, see patch 5/9.
patch 6/9 is base on Laurent's series, to support probe deferral.
patch 7/9 according to Robin Murphy's suggestion, remove global variable arm_smmu_devices, thanks.
patch 9/9 add support for a master with multiple stream IDs.

Zhen Lei (5):
  iommu/arm-smmu: to support probe deferral
  iommu/arm-smmu: rename __arm_smmu_get_pci_sid
  iommu/arm-smmu: add support for non-pci devices
  iommu/arm-smmu: to backward compatible with probe non-deferral
  iommu/arm-smmu: describe the limitation of #iommu-cells

 .../devicetree/bindings/iommu/arm,smmu-v3.txt      |   6 +
 drivers/iommu/arm-smmu-v3.c                        | 166 +++++++++++++++++----
 2 files changed, 143 insertions(+), 29 deletions(-)

--
2.5.0


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#1247577 — [PATCH v4 1/5] iommu/arm-smmu: to support probe deferral

For pci devices, only the root nodes have "iommus" property. So we
should traverse all of its sub nodes in of_xlate.

There exists two cases:
Case 1: .add_device(sub node) happened before .of_xlate(root node)
Case 2: .add_device(sub node) happened after  .of_xlate(root node)

(1).add_device
	if (!root->archdata.iommu)
		return -ENODEV;

(2).of_xlate
	root->archdata.iommu = smmu;
	/*
	 * Probe the pci devices deferred in phase (1)
	 */

(3).add_device
	/*
	 * After phase (2), it's not NULL
	 */
	if (!root->archdata.iommu)
		return -ENODEV;

	__arm_smmu_add_pci_device(pdev, root->archdata.iommu);

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/iommu/arm-smmu-v3.c | 110 +++++++++++++++++++++++++++++++++-----------
 1 file changed, 83 insertions(+), 27 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 5a36ef7..3a54af1 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -30,6 +30,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/of_iommu.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>

@@ -1742,29 +1743,15 @@ static void __arm_smmu_release_pci_iommudata(void *data)
 	kfree(data);
 }

-static struct arm_smmu_device *arm_smmu_get_for_pci_dev(struct pci_dev *pdev)
+static struct device *arm_smmu_get_pci_dev_root(struct pci_dev *pdev)
 {
-	struct device_node *of_node;
-	struct platform_device *smmu_pdev;
-	struct arm_smmu_device *smmu = NULL;
 	struct pci_bus *bus = pdev->bus;

 	/* Walk up to the root bus */
 	while (!pci_is_root_bus(bus))
 		bus = bus->parent;

-	/* Follow the "iommus" phandle from the host controller */
-	of_node = of_parse_phandle(bus->bridge->parent->of_node, "iommus", 0);
-	if (!of_node)
-		return NULL;
-
-	/* See if we can find an SMMU corresponding to the phandle */
-	smmu_pdev = of_find_device_by_node(of_node);
-	if (smmu_pdev)
-		smmu = platform_get_drvdata(smmu_pdev);
-
-	of_node_put(of_node);
-	return smmu;
+	return bus->bridge->parent;
 }

 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
@@ -1777,27 +1764,21 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
 	return sid < limit;
 }

-static int arm_smmu_add_device(struct device *dev)
+static int __arm_smmu_add_device(struct device *dev, u32 sid)
 {
 	int i, ret;
-	u32 sid, *sids;
-	struct pci_dev *pdev;
+	u32 *sids;
 	struct iommu_group *group;
 	struct arm_smmu_group *smmu_group;
 	struct arm_smmu_device *smmu;

-	/* We only support PCI, for now */
-	if (!dev_is_pci(dev))
-		return -ENODEV;
-
-	pdev = to_pci_dev(dev);
 	group = iommu_group_get_for_dev(dev);
 	if (IS_ERR(group))
 		return PTR_ERR(group);

 	smmu_group = iommu_group_get_iommudata(group);
 	if (!smmu_group) {
-		smmu = arm_smmu_get_for_pci_dev(pdev);
+		smmu = dev->archdata.iommu;
 		if (!smmu) {
 			ret = -ENOENT;
 			goto out_put_group;
@@ -1817,8 +1798,6 @@ static int arm_smmu_add_device(struct device *dev)
 		smmu = smmu_group->smmu;
 	}

-	/* Assume SID == RID until firmware tells us otherwise */
-	pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
 	for (i = 0; i < smmu_group->num_sids; ++i) {
 		/* If we already know about this SID, then we're done */
 		if (smmu_group->sids[i] == sid)
@@ -1855,11 +1834,43 @@ static int arm_smmu_add_device(struct device *dev)

 out_put_group:
 	iommu_group_put(group);
+	dev_err(dev, "failed to add into SMMU\n");
 	return ret;
 }

+static int __arm_smmu_add_pci_device(struct pci_dev *pdev, void *smmu)
+{
+	u32 sid;
+	struct device *dev = &pdev->dev;
+
+	/* Assume SID == RID until firmware tells us otherwise */
+	pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
+
+	dev->archdata.iommu = smmu;
+
+	return __arm_smmu_add_device(dev, sid);
+}
+
+static int arm_smmu_add_device(struct device *dev)
+{
+	struct pci_dev *pdev;
+	struct device *root;
+
+	/* only support pci devices hotplug */
+	if (!dev_is_pci(dev))
+		return -ENODEV;
+
+	pdev = to_pci_dev(dev);
+	root = arm_smmu_get_pci_dev_root(pdev);
+	if (!root->archdata.iommu)
+		return -ENODEV;
+
+	return __arm_smmu_add_pci_device(pdev, root->archdata.iommu);
+}
+
 static void arm_smmu_remove_device(struct device *dev)
 {
+	dev->archdata.iommu = NULL;
 	iommu_group_remove_device(dev);
 }

@@ -1907,7 +1918,49 @@ out_unlock:
 	return ret;
 }

+static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
+{
+	int ret;
+	struct platform_device *pdev;
+	struct arm_smmu_device *smmu;
+
+	pdev = of_find_device_by_node(args->np);
+	if (!pdev)
+		return -EINVAL;
+
+	smmu = platform_get_drvdata(pdev);
+
+	if (!dev->archdata.iommu)
+		dev->archdata.iommu = smmu;
+
+	if (dev->archdata.iommu != smmu) {
+		dev_err(dev, "behinds more than one smmu\n");
+		return -EINVAL;
+	}
+
+	/* We only support PCI, for now */
+	if (!dev_is_pci(dev)) {
+		return -ENODEV;
+	} else {
+		struct device *root;
+		struct pci_dev *pdev = NULL;
+
+		for_each_pci_dev(pdev) {
+			root = arm_smmu_get_pci_dev_root(pdev);
+			if (root->of_node != dev->of_node)
+				continue;
+
+			ret = __arm_smmu_add_pci_device(pdev, smmu);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
 static struct iommu_ops arm_smmu_ops = {
+	.of_xlate		= arm_smmu_of_xlate,
 	.capable		= arm_smmu_capable,
 	.domain_alloc		= arm_smmu_domain_alloc,
 	.domain_free		= arm_smmu_domain_free,
@@ -2687,6 +2740,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)

 	/* Record our private device structure */
 	platform_set_drvdata(pdev, smmu);
+	of_iommu_set_ops(smmu->dev->of_node, &arm_smmu_ops);

 	/* Reset the device */
 	ret = arm_smmu_device_reset(smmu);
@@ -2750,6 +2804,8 @@ static void __exit arm_smmu_exit(void)
 subsys_initcall(arm_smmu_init);
 module_exit(arm_smmu_exit);

+IOMMU_OF_DECLARE(arm_smmu_v3, "arm,smmu-v3", NULL);
+
 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
 MODULE_LICENSE("GPL v2");
--
2.5.0


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#1247581 — [PATCH v4 3/5] iommu/arm-smmu: add support for non-pci devices

This patch support a master with multiple stream IDs, but doesn't support a
master behinds more than one SMMUs.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/iommu/arm-smmu-v3.c | 40 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index b577d61..021a846 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -31,6 +31,7 @@
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/of_iommu.h>
+#include <linux/amba/bus.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>

@@ -1938,9 +1939,36 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
 		return -EINVAL;
 	}

-	/* We only support PCI, for now */
 	if (!dev_is_pci(dev)) {
-		return -ENODEV;
+		struct iommu_group *group;
+
+		if (args->args_count != 1) {
+			dev_err(dev,
+				"only support #iommu-cells = <1>, please check node: %s\n",
+				dev_name(smmu->dev));
+			return -ENODEV;
+		}
+
+		group = iommu_group_get(dev);
+		if (!group) {
+			group = iommu_group_alloc();
+			if (IS_ERR(group)) {
+				dev_err(dev, "failed to allocate IOMMU group\n");
+				return PTR_ERR(group);
+			}
+
+			ret = iommu_group_add_device(group, dev);
+			if (ret) {
+				iommu_group_put(group);
+				dev_err(dev, "failed to add device into IOMMU group\n");
+				return ret;
+			}
+		}
+		iommu_group_put(group);
+
+		ret = __arm_smmu_add_device(dev, args->args[0]);
+		if (ret)
+			return ret;
 	} else {
 		struct device *root;
 		struct pci_dev *pdev = NULL;
@@ -2793,6 +2821,14 @@ static int __init arm_smmu_init(void)
 	if (ret)
 		return ret;

+	if (!iommu_present(&platform_bus_type))
+		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
+
+#ifdef CONFIG_ARM_AMBA
+	if (!iommu_present(&amba_bustype))
+		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
+#endif
+
 	return bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
 }

--
2.5.0


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#1247583 — [PATCH v4 5/5] iommu/arm-smmu: describe the limitation of #iommu-cells

Only support #iommu-cells = <1>.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
index 947863a..4845d44 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
@@ -5,6 +5,12 @@ revisions, replacing the MMIO register interface with in-memory command
 and event queues and adding support for the ATS and PRI components of
 the PCIe specification.

+Please read ./iommu.txt first, here list something special as below:
+
+** SMMUv3 limited properties:
+- #iommu-cells      : fixed to <1>. The pci root device is a special case,
+                      its IDs can be omitted in dts, seems #iommu-cells = <0>.
+
 ** SMMUv3 required properties:

 - compatible        : Should include:
--
2.5.0


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