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Groups > linux.kernel > #1243130 > unrolled thread

[PATCH v3 0/5] ARM: sunxi: Introduce CHIP support

Started byMaxime Ripard <maxime.ripard@free-electrons.com>
First post2015-10-09 10:50 +0200
Last post2015-10-11 19:10 +0200
Articles 13 — 2 participants

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Contents

  [PATCH v3 0/5] ARM: sunxi: Introduce CHIP support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-09 10:50 +0200
    [PATCH v3 2/5] ARM: sun5i: Add R8 DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-09 10:50 +0200
    [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-09 10:50 +0200
      Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS Chen-Yu Tsai <wens@csie.org> - 2015-10-09 17:30 +0200
        Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-11 19:30 +0200
          Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS Chen-Yu Tsai <wens@csie.org> - 2015-10-12 04:30 +0200
            Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-12 11:40 +0200
    [PATCH v3 1/5] ARM: sunxi: Add R8 support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-09 10:50 +0200
      Re: [PATCH v3 1/5] ARM: sunxi: Add R8 support Chen-Yu Tsai <wens@csie.org> - 2015-10-09 16:30 +0200
        Re: [PATCH v3 1/5] ARM: sunxi: Add R8 support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-11 19:10 +0200
    [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-09 10:50 +0200
      Re: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI Chen-Yu Tsai <wens@csie.org> - 2015-10-09 16:30 +0200
        Re: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common  DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-11 19:10 +0200

#1243130 — [PATCH v3 0/5] ARM: sunxi: Introduce CHIP support

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-09 10:50 +0200
Subject[PATCH v3 0/5] ARM: sunxi: Introduce CHIP support
Message-ID<qhBxg-5rH-3@gated-at.bofh.it>
Hi,

Here is a serie introducing the support for the Allwinner R8 and the
Nextthing's CHIP.

Support is almost complete for the CHIP itself, the only missing part
for now is the WiFi chip that needs to be powered through two combined
regulators (AXP209's LDO3 and LDO4). The audio codec is also missing
since it's not already enabled in the DT.

Both these features will be addressed eventually.

Let me know what you think,
Maxime

Changes from v2:
  - Fixed whitespace issue
  - Changed DTSI include to R8
  - Removed i2c1 to be consitent with the other boards

Changes from v1:
  - Collected tags
  - Removed unused include files
  - Removed ipsout, dram and vcc regulators
  - Added USB power supply

Maxime Ripard (5):
  ARM: sunxi: Add R8 support
  ARM: sun5i: Add R8 DTSI
  ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI
  ARM: sun5i: dt: Add UART3 CTS and RTS pins
  ARM: sun5i: Add C.H.I.P DTS

 Documentation/arm/sunxi/README                  |   2 +-
 Documentation/devicetree/bindings/arm/sunxi.txt |   1 +
 arch/arm/boot/dts/Makefile                      |   3 +-
 arch/arm/boot/dts/sun5i-a10s.dtsi               |   7 -
 arch/arm/boot/dts/sun5i-r8-chip.dts             | 213 ++++++++++++++++++++++++
 arch/arm/boot/dts/sun5i-r8.dtsi                 |  59 +++++++
 arch/arm/boot/dts/sun5i.dtsi                    |  14 ++
 arch/arm/mach-sunxi/sunxi.c                     |   3 +-
 drivers/clk/sunxi/clk-sunxi.c                   |   1 +
 9 files changed, 293 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
 create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi

-- 
2.5.3

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#1243132 — [PATCH v3 2/5] ARM: sun5i: Add R8 DTSI

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-09 10:50 +0200
Subject[PATCH v3 2/5] ARM: sun5i: Add R8 DTSI
Message-ID<qhBxg-5rH-7@gated-at.bofh.it>
In reply to#1243130
The R8 is very close to the A13, but it still has a few differences,
notably a composite output, which the A13 lacks.

Add a DTSI based on the A13's to hold those differences.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
new file mode 100644
index 000000000000..0ef865601ac9
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015 Free Electrons
+ * Copyright 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun5i-a13.dtsi"
+
+/ {
+	chosen {
+		framebuffer@1 {
+			compatible = "allwinner,simple-framebuffer",
+				     "simple-framebuffer";
+			allwinner,pipeline = "de_be0-lcd0-tve0";
+			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
+				 <&ahb_gates 44>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.5.3

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#1243134 — [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-09 10:50 +0200
Subject[PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS
Message-ID<qhBxg-5rH-15@gated-at.bofh.it>
In reply to#1243130
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/boot/dts/Makefile          |   3 +-
 arch/arm/boot/dts/sun5i-r8-chip.dts | 213 ++++++++++++++++++++++++++++++++++++
 2 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 342ab3116feb..bf165ed4e7fa 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
 	sun5i-a13-olinuxino.dtb \
 	sun5i-a13-olinuxino-micro.dtb \
 	sun5i-a13-q8-tablet.dtb \
-	sun5i-a13-utoo-p66.dtb
+	sun5i-a13-utoo-p66.dtb \
+	sun5i-r8-chip.dtb
 dtb-$(CONFIG_MACH_SUN6I) += \
 	sun6i-a31-app4-evb1.dtb \
 	sun6i-a31-colombus.dtb \
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
new file mode 100644
index 000000000000..0d450a828372
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2015 Free Electrons
+ * Copyright 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-r8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "NextThing C.H.I.P.";
+	compatible = "nextthing,chip", "allwinner,sun5i-r8";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c2 = &i2c2;
+		serial0 = &uart1;
+		serial1 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+
+		/*
+		 * The interrupt is routed through the "External Fast
+		 * Interrupt Request" pin (ball G13 of the module)
+		 * directly to the main interrupt controller, without
+		 * any other controller interfering.
+		 */
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	status = "okay";
+
+	xio: gpio@38 {
+		compatible = "nxp,pcf8574a";
+		reg = <0x38>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-parent = <&pio>;
+		interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	chip_vbus_pin: chip_vbus_pin@0 {
+		allwinner,pins = "PB10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	chip_id_det_pin: chip_id_det_pin@0 {
+		allwinner,pins = "PG2";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&reg_dcdc2 {
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "cpuvdd";
+	regulator-always-on;
+};
+
+&reg_dcdc3 {
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "corevdd";
+	regulator-always-on;
+};
+
+&reg_ldo1 {
+	regulator-name = "rtcvdd";
+};
+
+&reg_ldo2 {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+	regulator-always-on;
+};
+
+&reg_ldo5 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vcc-1v8";
+};
+
+&reg_usb0_vbus {
+	pinctrl-0 = <&chip_vbus_pin>;
+	vin-supply = <&reg_vcc5v0>;
+	gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_b>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_a>,
+		    <&uart3_pins_cts_rts_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&chip_id_det_pin>;
+	status = "okay";
+
+	usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb1_vbus-supply = <&reg_vcc5v0>;
+};
-- 
2.5.3

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#1243469 — Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

FromChen-Yu Tsai <wens@csie.org>
Date2015-10-09 17:30 +0200
SubjectRe: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS
Message-ID<qhHMm-63K-23@gated-at.bofh.it>
In reply to#1243134
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
> RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
> and two connectors to plug additional boards on top of it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  arch/arm/boot/dts/Makefile          |   3 +-
>  arch/arm/boot/dts/sun5i-r8-chip.dts | 213 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 215 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 342ab3116feb..bf165ed4e7fa 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
>         sun5i-a13-olinuxino.dtb \
>         sun5i-a13-olinuxino-micro.dtb \
>         sun5i-a13-q8-tablet.dtb \
> -       sun5i-a13-utoo-p66.dtb
> +       sun5i-a13-utoo-p66.dtb \
> +       sun5i-r8-chip.dtb
>  dtb-$(CONFIG_MACH_SUN6I) += \
>         sun6i-a31-app4-evb1.dtb \
>         sun6i-a31-colombus.dtb \
> diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
> new file mode 100644
> index 000000000000..0d450a828372
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts

snip

> +&reg_dcdc2 {
> +       regulator-min-microvolt = <1000000>;
> +       regulator-max-microvolt = <1400000>;
> +       regulator-name = "cpuvdd";

Other boards seem to follow the power pin names on the SoC and call
this "vdd-cpu".

> +       regulator-always-on;
> +};
> +
> +&reg_dcdc3 {
> +       regulator-min-microvolt = <1000000>;
> +       regulator-max-microvolt = <1300000>;
> +       regulator-name = "corevdd";

And this was named "vdd-int" or "vdd-int-dll" (for SoCs with separate
VDD_DLL pins).

> +       regulator-always-on;
> +};
> +
> +&reg_ldo1 {
> +       regulator-name = "rtcvdd";

And this one was "vdd-rtc".

I know you followed the names set in the design doc. Just wondering if there
should be some convention on these.

> +};
> +
> +&reg_ldo2 {
> +       regulator-min-microvolt = <2700000>;
> +       regulator-max-microvolt = <3300000>;
> +       regulator-name = "avcc";
> +       regulator-always-on;
> +};
> +
> +&reg_ldo5 {
> +       regulator-min-microvolt = <1800000>;
> +       regulator-max-microvolt = <1800000>;
> +       regulator-name = "vcc-1v8";
> +};
> +
> +&reg_usb0_vbus {
> +       pinctrl-0 = <&chip_vbus_pin>;
> +       vin-supply = <&reg_vcc5v0>;
> +       gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */

          status = "okay"; ?

The rest looks good.

Regards
ChenYu

> +};
> +
> +&uart1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&uart1_pins_b>;
> +       status = "okay";
> +};
> +
> +&uart3 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&uart3_pins_a>,
> +                   <&uart3_pins_cts_rts_a>;
> +       status = "okay";
> +};
> +
> +&usb_otg {
> +       dr_mode = "otg";
> +       status = "okay";
> +};
> +
> +&usb_power_supply {
> +       status = "okay";
> +};
> +
> +&usbphy {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&chip_id_det_pin>;
> +       status = "okay";
> +
> +       usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
> +       usb0_vbus_power-supply = <&usb_power_supply>;
> +       usb0_vbus-supply = <&reg_usb0_vbus>;
> +       usb1_vbus-supply = <&reg_vcc5v0>;
> +};
> --
> 2.5.3
>
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#1244165 — Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-11 19:30 +0200
SubjectRe: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS
Message-ID<qisBA-6Ef-1@gated-at.bofh.it>
In reply to#1243469

[Multipart message — attachments visible in raw view] — view raw

On Fri, Oct 09, 2015 at 11:22:23PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
> > RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
> > and two connectors to plug additional boards on top of it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> > ---
> >  arch/arm/boot/dts/Makefile          |   3 +-
> >  arch/arm/boot/dts/sun5i-r8-chip.dts | 213 ++++++++++++++++++++++++++++++++++++
> >  2 files changed, 215 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 342ab3116feb..bf165ed4e7fa 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
> >         sun5i-a13-olinuxino.dtb \
> >         sun5i-a13-olinuxino-micro.dtb \
> >         sun5i-a13-q8-tablet.dtb \
> > -       sun5i-a13-utoo-p66.dtb
> > +       sun5i-a13-utoo-p66.dtb \
> > +       sun5i-r8-chip.dtb
> >  dtb-$(CONFIG_MACH_SUN6I) += \
> >         sun6i-a31-app4-evb1.dtb \
> >         sun6i-a31-colombus.dtb \
> > diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
> > new file mode 100644
> > index 000000000000..0d450a828372
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
> 
> snip
> 
> > +&reg_dcdc2 {
> > +       regulator-min-microvolt = <1000000>;
> > +       regulator-max-microvolt = <1400000>;
> > +       regulator-name = "cpuvdd";
> 
> Other boards seem to follow the power pin names on the SoC and call
> this "vdd-cpu".
> 
> > +       regulator-always-on;
> > +};
> > +
> > +&reg_dcdc3 {
> > +       regulator-min-microvolt = <1000000>;
> > +       regulator-max-microvolt = <1300000>;
> > +       regulator-name = "corevdd";
> 
> And this was named "vdd-int" or "vdd-int-dll" (for SoCs with separate
> VDD_DLL pins).
> 
> > +       regulator-always-on;
> > +};
> > +
> > +&reg_ldo1 {
> > +       regulator-name = "rtcvdd";
> 
> And this one was "vdd-rtc".
> 
> I know you followed the names set in the design doc. Just wondering if there
> should be some convention on these.

I think if we have a document that clearly reference them with some
other name, we should just stick with the name used there, especially
if it's only cosmetic, which is the case here.

> > +};
> > +
> > +&reg_ldo2 {
> > +       regulator-min-microvolt = <2700000>;
> > +       regulator-max-microvolt = <3300000>;
> > +       regulator-name = "avcc";
> > +       regulator-always-on;
> > +};
> > +
> > +&reg_ldo5 {
> > +       regulator-min-microvolt = <1800000>;
> > +       regulator-max-microvolt = <1800000>;
> > +       regulator-name = "vcc-1v8";
> > +};
> > +
> > +&reg_usb0_vbus {
> > +       pinctrl-0 = <&chip_vbus_pin>;
> > +       vin-supply = <&reg_vcc5v0>;
> > +       gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
> 
>           status = "okay"; ?

Ah, yes, indeed.

> The rest looks good.

Is that an Ack from you if I add the status ?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1244343 — Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

FromChen-Yu Tsai <wens@csie.org>
Date2015-10-12 04:30 +0200
SubjectRe: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS
Message-ID<qiB2a-25v-7@gated-at.bofh.it>
In reply to#1244165
On Mon, Oct 12, 2015 at 1:20 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Fri, Oct 09, 2015 at 11:22:23PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
>> > RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
>> > and two connectors to plug additional boards on top of it.
>> >
>> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> > Reviewed-by: Hans de Goede <hdegoede@redhat.com>
>> > ---
>> >  arch/arm/boot/dts/Makefile          |   3 +-
>> >  arch/arm/boot/dts/sun5i-r8-chip.dts | 213 ++++++++++++++++++++++++++++++++++++
>> >  2 files changed, 215 insertions(+), 1 deletion(-)
>> >  create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
>> >
>> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> > index 342ab3116feb..bf165ed4e7fa 100644
>> > --- a/arch/arm/boot/dts/Makefile
>> > +++ b/arch/arm/boot/dts/Makefile
>> > @@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
>> >         sun5i-a13-olinuxino.dtb \
>> >         sun5i-a13-olinuxino-micro.dtb \
>> >         sun5i-a13-q8-tablet.dtb \
>> > -       sun5i-a13-utoo-p66.dtb
>> > +       sun5i-a13-utoo-p66.dtb \
>> > +       sun5i-r8-chip.dtb
>> >  dtb-$(CONFIG_MACH_SUN6I) += \
>> >         sun6i-a31-app4-evb1.dtb \
>> >         sun6i-a31-colombus.dtb \
>> > diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
>> > new file mode 100644
>> > index 000000000000..0d450a828372
>> > --- /dev/null
>> > +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
>>
>> snip
>>
>> > +&reg_dcdc2 {
>> > +       regulator-min-microvolt = <1000000>;
>> > +       regulator-max-microvolt = <1400000>;
>> > +       regulator-name = "cpuvdd";
>>
>> Other boards seem to follow the power pin names on the SoC and call
>> this "vdd-cpu".
>>
>> > +       regulator-always-on;
>> > +};
>> > +
>> > +&reg_dcdc3 {
>> > +       regulator-min-microvolt = <1000000>;
>> > +       regulator-max-microvolt = <1300000>;
>> > +       regulator-name = "corevdd";
>>
>> And this was named "vdd-int" or "vdd-int-dll" (for SoCs with separate
>> VDD_DLL pins).
>>
>> > +       regulator-always-on;
>> > +};
>> > +
>> > +&reg_ldo1 {
>> > +       regulator-name = "rtcvdd";
>>
>> And this one was "vdd-rtc".
>>
>> I know you followed the names set in the design doc. Just wondering if there
>> should be some convention on these.
>
> I think if we have a document that clearly reference them with some
> other name, we should just stick with the name used there, especially
> if it's only cosmetic, which is the case here.

That's a good rule to follow. :)

>> > +};
>> > +
>> > +&reg_ldo2 {
>> > +       regulator-min-microvolt = <2700000>;
>> > +       regulator-max-microvolt = <3300000>;
>> > +       regulator-name = "avcc";
>> > +       regulator-always-on;
>> > +};
>> > +
>> > +&reg_ldo5 {
>> > +       regulator-min-microvolt = <1800000>;
>> > +       regulator-max-microvolt = <1800000>;
>> > +       regulator-name = "vcc-1v8";
>> > +};
>> > +
>> > +&reg_usb0_vbus {
>> > +       pinctrl-0 = <&chip_vbus_pin>;
>> > +       vin-supply = <&reg_vcc5v0>;
>> > +       gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
>>
>>           status = "okay"; ?
>
> Ah, yes, indeed.
>
>> The rest looks good.
>
> Is that an Ack from you if I add the status ?

Yes. Thanks!

ChenYu
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#1244538 — Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-12 11:40 +0200
SubjectRe: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS
Message-ID<qiHKj-3k0-27@gated-at.bofh.it>
In reply to#1244343

[Multipart message — attachments visible in raw view] — view raw

On Mon, Oct 12, 2015 at 10:20:37AM +0800, Chen-Yu Tsai wrote:
> >> > +};
> >> > +
> >> > +&reg_ldo2 {
> >> > +       regulator-min-microvolt = <2700000>;
> >> > +       regulator-max-microvolt = <3300000>;
> >> > +       regulator-name = "avcc";
> >> > +       regulator-always-on;
> >> > +};
> >> > +
> >> > +&reg_ldo5 {
> >> > +       regulator-min-microvolt = <1800000>;
> >> > +       regulator-max-microvolt = <1800000>;
> >> > +       regulator-name = "vcc-1v8";
> >> > +};
> >> > +
> >> > +&reg_usb0_vbus {
> >> > +       pinctrl-0 = <&chip_vbus_pin>;
> >> > +       vin-supply = <&reg_vcc5v0>;
> >> > +       gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
> >>
> >>           status = "okay"; ?
> >
> > Ah, yes, indeed.
> >
> >> The rest looks good.
> >
> > Is that an Ack from you if I add the status ?
> 
> Yes. Thanks!

Great :)

Applied with the extra status and your Ack.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1243137 — [PATCH v3 1/5] ARM: sunxi: Add R8 support

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-09 10:50 +0200
Subject[PATCH v3 1/5] ARM: sunxi: Add R8 support
Message-ID<qhBxh-5rH-31@gated-at.bofh.it>
In reply to#1243130
The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.

In order to have a consistent naming, instead of mentionning the allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
---
 Documentation/arm/sunxi/README                  | 2 +-
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c                     | 3 ++-
 drivers/clk/sunxi/clk-sunxi.c                   | 1 +
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 5e38e1582f95..430d279a8df3 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -25,7 +25,7 @@ SunXi family
         + Datasheet
           http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
 
-      - Allwinner A13 (sun5i)
+      - Allwinner A13 / R8 (sun5i)
         + Datasheet
 	  http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
         + User Manual
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 67da20539540..bb9b0faa919d 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -6,6 +6,7 @@ using one of the following compatible strings:
   allwinner,sun4i-a10
   allwinner,sun5i-a10s
   allwinner,sun5i-a13
+  allwinner,sun5i-r8
   allwinner,sun6i-a31
   allwinner,sun7i-a20
   allwinner,sun8i-a23
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 65bab2876343..8583a9ca86bd 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,10 +26,11 @@ static const char * const sunxi_board_dt_compat[] = {
 	"allwinner,sun4i-a10",
 	"allwinner,sun5i-a10s",
 	"allwinner,sun5i-a13",
+	"allwinner,sun5i-r8",
 	NULL,
 };
 
-DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+DT_MACHINE_START(SUNXI_DT, "Allwinner sun4i/sun5i Families")
 	.dt_compat	= sunxi_board_dt_compat,
 	.init_late	= sunxi_dt_cpufreq_init,
 MACHINE_END
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 413070d07b3f..9c79af0c03b2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1196,6 +1196,7 @@ static void __init sun5i_init_clocks(struct device_node *node)
 }
 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
+CLK_OF_DECLARE(sun5i_r8_clk_init, "allwinner,sun5i-r8", sun5i_init_clocks);
 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
 
 static const char *sun6i_critical_clocks[] __initdata = {
-- 
2.5.3

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#1243419 — Re: [PATCH v3 1/5] ARM: sunxi: Add R8 support

FromChen-Yu Tsai <wens@csie.org>
Date2015-10-09 16:30 +0200
SubjectRe: [PATCH v3 1/5] ARM: sunxi: Add R8 support
Message-ID<qhGQj-4IM-25@gated-at.bofh.it>
In reply to#1243137
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The R8 is a new Allwinner SoC based on the A13. While both are very
> similar, there's still a few differences. Introduce a new compatible to
> deal with them.
>
> In order to have a consistent naming, instead of mentionning the allwinner
                                                   ^               ^
nit:                                               mentioning      Allwinner

Fix when you apply?

> A series as the machine name, switch to sun4i/sun5i like what is done for
> the other families.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Thanks
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#1244160 — Re: [PATCH v3 1/5] ARM: sunxi: Add R8 support

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-11 19:10 +0200
SubjectRe: [PATCH v3 1/5] ARM: sunxi: Add R8 support
Message-ID<qisie-6hb-13@gated-at.bofh.it>
In reply to#1243419

[Multipart message — attachments visible in raw view] — view raw

On Fri, Oct 09, 2015 at 10:20:29PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The R8 is a new Allwinner SoC based on the A13. While both are very
> > similar, there's still a few differences. Introduce a new compatible to
> > deal with them.
> >
> > In order to have a consistent naming, instead of mentionning the allwinner
>                                                    ^               ^
> nit:                                               mentioning      Allwinner
> 
> Fix when you apply?
> 
> > A series as the machine name, switch to sun4i/sun5i like what is done for
> > the other families.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> 
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Fixed the typos and applied, thanks!
Maxime

-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1243144 — [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-09 10:50 +0200
Subject[PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI
Message-ID<qhBxi-5rH-51@gated-at.bofh.it>
In reply to#1243130
The uart3 pins are shared between the A10s and A13, move the pinctrl node
to the common DTSI to avoid duplication.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 7 -------
 arch/arm/boot/dts/sun5i.dtsi      | 7 +++++++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0fdabe8eb9e8..2ebd32f5bc6e 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -204,13 +204,6 @@
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
-	uart3_pins_a: uart3@0 {
-		allwinner,pins = "PG9", "PG10";
-		allwinner,function = "uart3";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
-
 	emac_pins_a: emac0@0 {
 		allwinner,pins = "PA0", "PA1", "PA2",
 				"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 78b993abbaa3..433c83a321ca 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -529,6 +529,13 @@
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
+
+			uart3_pins_a: uart3@0 {
+				allwinner,pins = "PG9", "PG10";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		timer@01c20c00 {
-- 
2.5.3

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#1243421 — Re: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI

FromChen-Yu Tsai <wens@csie.org>
Date2015-10-09 16:30 +0200
SubjectRe: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI
Message-ID<qhGQj-4IM-29@gated-at.bofh.it>
In reply to#1243144
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The uart3 pins are shared between the A10s and A13, move the pinctrl node
> to the common DTSI to avoid duplication.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Thanks
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#1244159 — Re: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2015-10-11 19:10 +0200
SubjectRe: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI
Message-ID<qisie-6hb-11@gated-at.bofh.it>
In reply to#1243421

[Multipart message — attachments visible in raw view] — view raw

On Fri, Oct 09, 2015 at 10:22:40PM +0800, Chen-Yu Tsai wrote:
> On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The uart3 pins are shared between the A10s and A13, move the pinctrl node
> > to the common DTSI to avoid duplication.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> 
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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