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[PATCH 1/2] devicetree: add binding for generic mmio clocksource

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  [PATCH 1/2] devicetree: add binding for generic mmio clocksource Mans Rullgard <mans@mansr.com> - 2015-10-03 16:30 +0200
    [PATCH 2/2] clocksource: mmio: add devicetree support Mans Rullgard <mans@mansr.com> - 2015-10-03 16:30 +0200

#1238897 — [PATCH 1/2] devicetree: add binding for generic mmio clocksource

This adds a DT binding for a generic mmio clocksource as implemented
by clocksource_mmio_init().

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 .../devicetree/bindings/timer/clocksource-mmio.txt | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/clocksource-mmio.txt

diff --git a/Documentation/devicetree/bindings/timer/clocksource-mmio.txt b/Documentation/devicetree/bindings/timer/clocksource-mmio.txt
new file mode 100644
index 0000000..d8e93f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/clocksource-mmio.txt
@@ -0,0 +1,26 @@
+Generic MMIO clocksource
+
+Required properties:
+
+- compatible: should be "clocksource-mmio"
+- reg: the physical address of the counter register
+- reg-io-width: size of counter register in bytes, should be 2 or 4
+- clocks: phandle to the source clock
+- clocksource-bits: number of valid bits
+- clocksource-rating: rating of the clocksource
+
+Optional properties:
+
+- clocksource-counts-down: indicates that counter counts down
+- label: name of the clocksource
+
+Example:
+
+clocksource {
+	compatible = "clocksource-mmio";
+        reg = <0x10000 4>;
+        reg-io-width = <4>;
+        clocksource-bits = <32>;
+        clocksource-rating = <300>;
+        clocks = <&clk>;
+}
-- 
2.5.3

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#1238899 — [PATCH 2/2] clocksource: mmio: add devicetree support

This implements the "clocksource-mmio" devicetree binding.  It is
useful for devices that have a free-running counter requiring no
setup.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 drivers/clocksource/mmio.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
index 1593ade..a903720 100644
--- a/drivers/clocksource/mmio.c
+++ b/drivers/clocksource/mmio.c
@@ -5,9 +5,11 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/clk.h>
 #include <linux/clocksource.h>
 #include <linux/errno.h>
 #include <linux/init.h>
+#include <linux/of_address.h>
 #include <linux/slab.h>
 
 struct clocksource_mmio {
@@ -71,3 +73,84 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
 
 	return clocksource_register_hz(&cs->clksrc, hz);
 }
+
+#ifdef CONFIG_OF
+static void __init clocksource_mmio_of_setup(struct device_node *node)
+{
+	cycle_t (*read_fn)(struct clocksource *);
+	void __iomem *reg;
+	struct clk *clk;
+	const char *name;
+	unsigned long rate;
+	bool count_down;
+	u32 rating;
+	u32 width;
+	u32 bits;
+	int err;
+
+	if (of_property_read_u32(node, "reg-io-width", &width)) {
+		pr_err("clocksource-mmio: register width not specified\n");
+		return;
+	}
+
+	if (of_property_read_u32(node, "clocksource-bits", &bits)) {
+		pr_err("clocksource-mmio: bits not specified\n");
+		return;
+	}
+
+	if (of_property_read_u32(node, "clocksource-rating", &rating)) {
+		pr_err("clocksource-mmio: rating not specified\n");
+		return;
+	}
+
+	count_down = of_property_read_bool(node, "clocksource-counts-down");
+
+	if (width == 2) {
+		read_fn = count_down ? clocksource_mmio_readw_down :
+			clocksource_mmio_readw_up;
+	} else if (width == 4) {
+		read_fn = count_down ? clocksource_mmio_readl_down :
+			clocksource_mmio_readl_up;
+	} else {
+		pr_err("clocksource-mmio: reg-io-width must be 2 or 4\n");
+		return;
+	}
+
+	clk = of_clk_get(node, 0);
+	if (IS_ERR(clk)) {
+		pr_err("clocksource-mmio: failed to get clock\n");
+		return;
+	}
+
+	if (clk_prepare_enable(clk)) {
+		pr_err("clocksource-mmio: failed to enable clock\n");
+		return;
+	}
+
+	rate = clk_get_rate(clk);
+	if (!rate) {
+		pr_err("clocksource-mmio: clock rate is zero\n");
+		clk_disable_unprepare(clk);
+		return;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("clocksource-mmio: iomap failed\n");
+		clk_disable_unprepare(clk);
+		return;
+	}
+
+	if (of_property_read_string(node, "label", &name))
+		name = node->name;
+
+	err = clocksource_mmio_init(reg, name, rate, rating, bits, read_fn);
+	if (err) {
+		pr_err("clocksource-mmio: failed to register clock source\n");
+		clk_disable_unprepare(clk);
+		iounmap(reg);
+	}
+}
+CLOCKSOURCE_OF_DECLARE(clocksource_mmio, "clocksource-mmio",
+		       clocksource_mmio_of_setup);
+#endif
-- 
2.5.3

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