Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1238401 > unrolled thread

[PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode

Back to article view | Back to linux.kernel

Contents

  [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode Marc Zyngier <marc.zyngier@arm.com> - 2015-10-02 18:40 +0200
    [PATCH 5/5] arm64: Update booting requirements for GICv3 in GICv2 mode Marc Zyngier <marc.zyngier@arm.com> - 2015-10-02 18:40 +0200

#1238401 — [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode

Recent evolutions of the ARM Trusted Firmware have outlined issues
when the system is equipped with a GICv3 interrupt controller, but the
firmware has decided to restrict it to GICv2 compatibility mode.

In this mode, system registers cannot be enabled, and the firmware is
expected to pass a GICv2 description (DT or ACPI tables).

This series makes sure that system register access is checked at EL2
setup time and when the feature detection is performed. Additionally,
the GICv2 driver checks that system registers are disabled, and warns
if they are enabled.

The booting requirements are also updated to make the above explicit.

Marc Zyngier (5):
  arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3
    sysregs
  irqchip/gic-v3: Make gic_enable_sre an inline function
  arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling
    ARM64_HAS_SYSREG_GIC_CPUIF
  irqchip/gic: Warn if GICv3 system registers are enabled
  arm64: Update booting requirements for GICv3 in GICv2 mode

 Documentation/arm64/booting.txt    | 11 ++++++++++-
 arch/arm64/kernel/cpufeature.c     | 19 ++++++++++++++++++-
 arch/arm64/kernel/head.S           |  2 ++
 drivers/irqchip/irq-gic-v3.c       | 32 +++++++++-----------------------
 drivers/irqchip/irq-gic.c          | 15 +++++++++++++++
 include/linux/irqchip/arm-gic-v3.h | 16 ++++++++++++++++
 6 files changed, 70 insertions(+), 25 deletions(-)

-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [next] | [standalone]

#1238403 — [PATCH 5/5] arm64: Update booting requirements for GICv3 in GICv2 mode

The current requirements do not describe the case where a GICv3
system gets booted with system register access disabled, and
expect the kernel to drive GICv3 in GICv2 mode.

Describe the expected settings for that particular case.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 Documentation/arm64/booting.txt | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt
index 7d9d3c2..369a4f4 100644
--- a/Documentation/arm64/booting.txt
+++ b/Documentation/arm64/booting.txt
@@ -173,13 +173,22 @@ Before jumping into the kernel, the following conditions must be met:
   the kernel image will be entered must be initialised by software at a
   higher exception level to prevent execution in an UNKNOWN state.
 
-  For systems with a GICv3 interrupt controller:
+  For systems with a GICv3 interrupt controller to be used in v3 mode:
   - If EL3 is present:
     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
   - If the kernel is entered at EL1:
     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
+  - The DT or ACPI tables must describe a GICv3 interrupt controller.
+
+  For systems with a GICv3 interrupt controller to be used in
+  compatibility (v2) mode:
+  - If EL3 is present:
+    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
+  - If the kernel is entered at EL1:
+    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
+  - The DT or ACPI tables must describe a GICv2 interrupt controller.
 
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web