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Groups > linux.kernel > #1231074 > unrolled thread

[PATCH] net: mdio-octeon: Add PCI driver binding.

Started byDavid Daney <ddaney.cavm@gmail.com>
First post2015-09-23 02:50 +0200
Last post2015-09-25 01:10 +0200
Articles 7 — 3 participants

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  [PATCH] net: mdio-octeon: Add PCI driver binding. David Daney <ddaney.cavm@gmail.com> - 2015-09-23 02:50 +0200
    Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Miller <davem@davemloft.net> - 2015-09-25 00:00 +0200
      Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Daney <ddaney@caviumnetworks.com> - 2015-09-25 00:10 +0200
        Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Miller <davem@davemloft.net> - 2015-09-25 00:20 +0200
        Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Miller <davem@davemloft.net> - 2015-09-25 00:20 +0200
          Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Miller <davem@davemloft.net> - 2015-09-25 01:00 +0200
            Re: [PATCH] net: mdio-octeon: Add PCI driver binding. David Miller <davem@davemloft.net> - 2015-09-25 01:10 +0200

#1231074 — [PATCH] net: mdio-octeon: Add PCI driver binding.

FromDavid Daney <ddaney.cavm@gmail.com>
Date2015-09-23 02:50 +0200
Subject[PATCH] net: mdio-octeon: Add PCI driver binding.
Message-ID<qbGpX-4YD-7@gated-at.bofh.it>
From: David Daney <david.daney@cavium.com>

When the Cavium mdio-octeon devices appear in the Thunder family of
arm64 based SoCs, they show up as PCI devices.  Add PCI driver
wrapping so the driver is bound in the standard PCI device scan.

When in this form, a single PCI device may have more than a single
bus, we call this a "nexus" of buses.  The standard firmware
device_for_each_child_node() iterator is used to find the individual
buses underneath the "nexus".

Update the device tree binding documentation for the new PCI driver
binding.

Signed-off-by: David Daney <david.daney@cavium.com>
---
 .../devicetree/bindings/net/cavium-mdio.txt        |  61 +++++++-
 drivers/net/phy/mdio-octeon.c                      | 159 +++++++++++++++++++--
 2 files changed, 209 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt
index 04cb749..020df08 100644
--- a/Documentation/devicetree/bindings/net/cavium-mdio.txt
+++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt
@@ -1,9 +1,12 @@
 * System Management Interface (SMI) / MDIO
 
 Properties:
-- compatible: "cavium,octeon-3860-mdio"
+- compatible: One of:
 
-  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+   "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
+                       and cn6XXX SOCs.
+
+   "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
 
 - reg: The base address of the MDIO bus controller register bank.
 
@@ -25,3 +28,57 @@ Example:
 			reg = <0>;
 		};
 	};
+
+
+* System Management Interface (SMI) / MDIO Nexus
+
+  Several mdio buses may be gathered as children of a single PCI
+  device, this PCI device is the nexus of the buses.
+
+Properties:
+
+- compatible: "cavium,thunder-8890-mdio-nexus";
+
+- reg: The PCI device and function numbers of the nexus device.
+
+- #address-cells: Must be <2>.
+
+- #size-cells: Must be <2>.
+
+- ranges: As needed for mapping of the MDIO bus device registers.
+
+- assigned-addresses: As needed for mapping of the MDIO bus device registers.
+
+Example:
+
+        mdio-nexus@1,3 {
+                compatible = "cavium,thunder-8890-mdio-nexus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
+                assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
+                ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
+
+                mdio0@87e0,05003800 {
+                        compatible = "cavium,thunder-8890-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x87e0 0x05003800 0x0 0x30>;
+
+                        ethernet-phy@0 {
+                                ...
+                                reg = <0>;
+                        };
+                };
+                mdio0@87e0,05003880 {
+                        compatible = "cavium,thunder-8890-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x87e0 0x05003880 0x0 0x30>;
+
+                        ethernet-phy@0 {
+                                ...
+                                reg = <0>;
+                        };
+                };
+        };
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index fcf4e4d..21eca35 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2009-2012 Cavium, Inc.
+ * Copyright (C) 2009-2015 Cavium, Inc.
  */
 
 #include <linux/platform_device.h>
@@ -14,6 +14,7 @@
 #include <linux/gfp.h>
 #include <linux/phy.h>
 #include <linux/io.h>
+#include <linux/pci.h>
 
 #ifdef CONFIG_CAVIUM_OCTEON_SOC
 #include <asm/octeon/octeon.h>
@@ -110,8 +111,6 @@ enum octeon_mdiobus_mode {
 struct octeon_mdiobus {
 	struct mii_bus *mii_bus;
 	u64 register_base;
-	resource_size_t mdio_phys;
-	resource_size_t regsize;
 	enum octeon_mdiobus_mode mode;
 	int phy_irq[PHY_MAX_ADDR];
 };
@@ -269,6 +268,8 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
 {
 	struct octeon_mdiobus *bus;
 	struct resource *res_mem;
+	resource_size_t mdio_phys;
+	resource_size_t regsize;
 	union cvmx_smix_en smi_en;
 	int err = -ENOENT;
 
@@ -282,17 +283,17 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
-	bus->mdio_phys = res_mem->start;
-	bus->regsize = resource_size(res_mem);
+	mdio_phys = res_mem->start;
+	regsize = resource_size(res_mem);
 
-	if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
+	if (!devm_request_mem_region(&pdev->dev, mdio_phys, regsize,
 				     res_mem->name)) {
 		dev_err(&pdev->dev, "request_mem_region failed\n");
 		return -ENXIO;
 	}
 
 	bus->register_base =
-		(u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
+		(u64)devm_ioremap(&pdev->dev, mdio_phys, regsize);
 	if (!bus->register_base) {
 		dev_err(&pdev->dev, "dev_ioremap failed\n");
 		return -ENOMEM;
@@ -308,7 +309,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
 
 	bus->mii_bus->priv = bus;
 	bus->mii_bus->irq = bus->phy_irq;
-	bus->mii_bus->name = "mdio-octeon";
+	bus->mii_bus->name = KBUILD_MODNAME;
 	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
 	bus->mii_bus->parent = &pdev->dev;
 
@@ -356,7 +357,7 @@ MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
 
 static struct platform_driver octeon_mdiobus_driver = {
 	.driver = {
-		.name		= "mdio-octeon",
+		.name		= KBUILD_MODNAME,
 		.of_match_table = octeon_mdiobus_match,
 	},
 	.probe		= octeon_mdiobus_probe,
@@ -371,6 +372,146 @@ EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
 
 module_platform_driver(octeon_mdiobus_driver);
 
+#ifdef CONFIG_PCI
+
+struct thunder_mdiobus_nexus {
+	void __iomem *bar0;
+	struct octeon_mdiobus *buses[4];
+};
+
+static int thunder_mdiobus_pci_probe(struct pci_dev *pdev,
+				     const struct pci_device_id *ent)
+{
+	struct device_node *node;
+	struct fwnode_handle *fwn;
+	struct thunder_mdiobus_nexus *nexus;
+	int err;
+	int i;
+
+	nexus = devm_kzalloc(&pdev->dev, sizeof(*nexus), GFP_KERNEL);
+	if (!nexus)
+		return -ENOMEM;
+
+	pci_set_drvdata(pdev, nexus);
+
+	err = pcim_enable_device(pdev);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to enable PCI device\n");
+		pci_set_drvdata(pdev, NULL);
+		return err;
+	}
+
+	err = pci_request_regions(pdev, KBUILD_MODNAME);
+	if (err) {
+		dev_err(&pdev->dev, "pci_request_regions failed\n");
+		goto err_disable_device;
+	}
+
+	nexus->bar0 = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
+	if (!nexus->bar0) {
+		err = -ENOMEM;
+		goto err_release_regions;
+	}
+
+	i = 0;
+	device_for_each_child_node(&pdev->dev, fwn) {
+		struct resource r;
+		struct octeon_mdiobus *bus;
+		union cvmx_smix_en smi_en;
+
+		/* If it is not an OF node we cannot handle it yet, so
+		 * exit the loop.
+		 */
+		node = to_of_node(fwn);
+		if (!node)
+			break;
+
+		err = of_address_to_resource(node, 0, &r);
+		if (err) {
+			dev_err(&pdev->dev,
+				"Couldn't translate address for \"%s\"\n",
+				node->name);
+			break;
+		}
+		bus = devm_kzalloc(&pdev->dev, sizeof(struct octeon_mdiobus),
+				   GFP_KERNEL);
+
+		if (!bus)
+			break;
+
+		nexus->buses[i] = bus;
+		i++;
+
+		bus->register_base = (u64)nexus->bar0 +
+			r.start - pci_resource_start(pdev, 0);
+
+		bus->mii_bus = mdiobus_alloc();
+		if (!bus->mii_bus)
+			break;
+
+		smi_en.u64 = 0;
+		smi_en.s.en = 1;
+		oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
+		bus->mii_bus->priv = bus;
+		bus->mii_bus->irq = bus->phy_irq;
+		bus->mii_bus->name = KBUILD_MODNAME;
+		snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", r.start);
+		bus->mii_bus->parent = &pdev->dev;
+		bus->mii_bus->read = octeon_mdiobus_read;
+		bus->mii_bus->write = octeon_mdiobus_write;
+
+		err = of_mdiobus_register(bus->mii_bus, node);
+		if (err)
+			dev_err(&pdev->dev, "of_mdiobus_register failed\n");
+
+		dev_info(&pdev->dev, "Added bus at %llx\n", r.start);
+		if (i >= ARRAY_SIZE(nexus->buses))
+			break;
+	}
+	return 0;
+
+err_release_regions:
+	pci_release_regions(pdev);
+
+err_disable_device:
+	pci_set_drvdata(pdev, NULL);
+	return err;
+}
+
+static void thunder_mdiobus_pci_remove(struct pci_dev *pdev)
+{
+	int i;
+	union cvmx_smix_en smi_en;
+	struct thunder_mdiobus_nexus *nexus = pci_get_drvdata(pdev);
+
+	for (i = 0; i < ARRAY_SIZE(nexus->buses); i++) {
+		struct octeon_mdiobus *bus = nexus->buses[i];
+
+		if (!bus)
+			continue;
+
+		mdiobus_unregister(bus->mii_bus);
+		mdiobus_free(bus->mii_bus);
+		smi_en.u64 = 0;
+		oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
+	}
+	pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id thunder_mdiobus_id_table[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa02b) },
+	{ 0, } /* End of table. */
+};
+MODULE_DEVICE_TABLE(pci, thunder_mdiobus_id_table);
+
+static struct pci_driver thunder_mdiobus_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = thunder_mdiobus_id_table,
+	.probe = thunder_mdiobus_pci_probe,
+	.remove = thunder_mdiobus_pci_remove,
+};
+module_pci_driver(thunder_mdiobus_driver);
+#endif /* CONFIG_PCI */
 MODULE_DESCRIPTION(DRV_DESCRIPTION);
 MODULE_VERSION(DRV_VERSION);
 MODULE_AUTHOR("David Daney");
-- 
1.9.1

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#1232452

FromDavid Miller <davem@davemloft.net>
Date2015-09-25 00:00 +0200
Message-ID<qcmIx-7cc-3@gated-at.bofh.it>
In reply to#1231074
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#1232458

FromDavid Daney <ddaney@caviumnetworks.com>
Date2015-09-25 00:10 +0200
Message-ID<qcmSe-7CQ-11@gated-at.bofh.it>
In reply to#1232452
On 09/24/2015 02:52 PM, David Miller wrote:
> From: David Daney <ddaney.cavm@gmail.com>
> Date: Tue, 22 Sep 2015 17:41:36 -0700
>
>> From: David Daney <david.daney@cavium.com>
>>
>> When the Cavium mdio-octeon devices appear in the Thunder family of
>> arm64 based SoCs, they show up as PCI devices.  Add PCI driver
>> wrapping so the driver is bound in the standard PCI device scan.
>>
>> When in this form, a single PCI device may have more than a single
>> bus, we call this a "nexus" of buses.  The standard firmware
>> device_for_each_child_node() iterator is used to find the individual
>> buses underneath the "nexus".
>>
>> Update the device tree binding documentation for the new PCI driver
>> binding.
>>
>> Signed-off-by: David Daney <david.daney@cavium.com>
>
> This patch breaks the build:

For which architecture?

I tested it on mips and arm64.  I will try x86, as I guess that is where 
you tried your test build.


>
>    CC [M]  drivers/net/phy/mdio-octeon.o
> In file included from drivers/net/phy/mdio-octeon.c:13:0:
> include/linux/module.h:128:27: error: redefinition of ‘__inittest’
>    static inline initcall_t __inittest(void)  \
>                             ^
[...]

>
> And frankly I'm not sure I like this change anyways.  If the OF nodes
> are there, simply add code to match on those OF nodes.
>
> This is better than assuming what sits underneath a PCI node, without
> any checks for the 'name' or 'compatible' properties at all.  That's
> what they are there for afterall.

There is, somewhat of, a method behind the madness here.

In order to use MSI-X interrupts, we need a corresponding PCI device. 
Now, this driver doesn't currently use interrupts, but other devices in 
the SoC do, so they must be PCI devices.

The idea is to have the type of all drivers uniformly be PCI, rather 
than a random mix of PCI and platform, and then switch them back and 
forth as PCI features are/are-not used in the driver.

Also we need to consider ACPI firmware in addition to OF device tree.

David Daney

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#1232461

FromDavid Miller <davem@davemloft.net>
Date2015-09-25 00:20 +0200
Message-ID<qcn1T-7O4-1@gated-at.bofh.it>
In reply to#1232458
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 24 Sep 2015 15:12:03 -0700

> Sorry for the breakage, I will fix it and resubmit.

Don't bother, I told you that using PCI probing is unacceptable.
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#1232467

FromDavid Miller <davem@davemloft.net>
Date2015-09-25 00:20 +0200
Message-ID<qcn1U-7O4-17@gated-at.bofh.it>
In reply to#1232458
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 24 Sep 2015 15:04:23 -0700

> On 09/24/2015 02:52 PM, David Miller wrote:
>> From: David Daney <ddaney.cavm@gmail.com>
>> Date: Tue, 22 Sep 2015 17:41:36 -0700
>>
>>> From: David Daney <david.daney@cavium.com>
>>>
>>> When the Cavium mdio-octeon devices appear in the Thunder family of
>>> arm64 based SoCs, they show up as PCI devices.  Add PCI driver
>>> wrapping so the driver is bound in the standard PCI device scan.
>>>
>>> When in this form, a single PCI device may have more than a single
>>> bus, we call this a "nexus" of buses.  The standard firmware
>>> device_for_each_child_node() iterator is used to find the individual
>>> buses underneath the "nexus".
>>>
>>> Update the device tree binding documentation for the new PCI driver
>>> binding.
>>>
>>> Signed-off-by: David Daney <david.daney@cavium.com>
>>
>> This patch breaks the build:
> 
> For which architecture?
> 
> I tested it on mips and arm64.  I will try x86, as I guess that is
> where you tried your test build.

x86-64.

> There is, somewhat of, a method behind the madness here.
> 
> In order to use MSI-X interrupts, we need a corresponding PCI
> device. Now, this driver doesn't currently use interrupts, but other
> devices in the SoC do, so they must be PCI devices.

"I need this thing, which isn't needed, therefore I'm making this
change."

Sorry, that's not a good argument.

ACPI nodes have names and whatnot as well.

So I haven't heard a compelling argument so far.

So why not just implement this cleanly and using the existing
framework now, and then when you have a legitimate reason for making a
major change to the probing scheme you can do it then.
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#1232483

FromDavid Miller <davem@davemloft.net>
Date2015-09-25 01:00 +0200
Message-ID<qcnEB-5s-9@gated-at.bofh.it>
In reply to#1232467
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 24 Sep 2015 15:45:41 -0700

> 2) The OF device tree nodes for PCI devices do not result in the
> creation of a platform device.

But they are created for the children right?  And that's the one
you need them for probing.

I'm still not convinced, sorry.
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#1232486

FromDavid Miller <davem@davemloft.net>
Date2015-09-25 01:10 +0200
Message-ID<qcnOi-wm-9@gated-at.bofh.it>
In reply to#1232483
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 24 Sep 2015 15:54:30 -0700

> On 09/24/2015 03:50 PM, David Miller wrote:
>> From: David Daney <ddaney@caviumnetworks.com>
>> Date: Thu, 24 Sep 2015 15:45:41 -0700
>>
>>> 2) The OF device tree nodes for PCI devices do not result in the
>>> creation of a platform device.
>>
>> But they are created for the children right?  And that's the one
>> you need them for probing.
>>
>> I'm still not convinced, sorry.
>>
> 
> Let's let this topic rest for a few days.  My original patch was
> defective, so it cannot be merged.  I will sleep on this, try a few
> things and perhaps revisit it if I still think it is advisable.

Ok.
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