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Groups > linux.kernel > #1230749 > unrolled thread

[PATCH 0/6] Support RIXI without fill bits

Started byPaul Burton <paul.burton@imgtec.com>
First post2015-09-22 20:50 +0200
Last post2015-09-22 20:50 +0200
Articles 3 — 1 participant

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  [PATCH 0/6] Support RIXI without fill bits Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:50 +0200
    [PATCH 2/6] MIPS: tlbex: remove some RIXI redundancy Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:50 +0200
    [PATCH 4/6] MIPS: tidy EntryLo bit definitions, add PFN Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:50 +0200

#1230749 — [PATCH 0/6] Support RIXI without fill bits

FromPaul Burton <paul.burton@imgtec.com>
Date2015-09-22 20:50 +0200
Subject[PATCH 0/6] Support RIXI without fill bits
Message-ID<qbANA-5hQ-3@gated-at.bofh.it>
This series fixes up the generated TLB exception handlers to take into
account cases where there are less fill bits in the Entry{Lo,Hi}
registers than there are software defined bits in a PTE. The most
notable case of this is when running a MIPS32 kernel on a MIPS64 system,
and given that RIXI is required on MIPSr6 support for it is required in
order to run MIPS32 kernels on MIPS64r6 CPUs.

Paul Burton (6):
  MIPS: tlbex: stop open-coding build_convert_pte_to_entrylo
  MIPS: tlbex: remove some RIXI redundancy
  MIPS: tlbex: share MIPS32 32 bit phys & MIPS64 64 bit phys code
  MIPS: tidy EntryLo bit definitions, add PFN
  MIPS: tlbex: avoid placing software PTE bits in Entry* PFN fields
  MIPS: allow RIXI for 32-bit kernels on MIPS64

 arch/mips/include/asm/cpu-features.h |  6 +--
 arch/mips/include/asm/mipsregs.h     | 12 ++---
 arch/mips/mm/tlbex.c                 | 89 ++++++++++++++++++++++--------------
 3 files changed, 59 insertions(+), 48 deletions(-)

-- 
2.5.3

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#1230750 — [PATCH 2/6] MIPS: tlbex: remove some RIXI redundancy

FromPaul Burton <paul.burton@imgtec.com>
Date2015-09-22 20:50 +0200
Subject[PATCH 2/6] MIPS: tlbex: remove some RIXI redundancy
Message-ID<qbANC-5hQ-59@gated-at.bofh.it>
In reply to#1230749
The cpu_has_rixi cases in build_update_entries are now identical to the
non-RIXI cases with the one exception of the r45k_bvahwbug case which is
hardcoded as never happening anyway & presumably was either missed from
the RIXI path or would never happen on a CPU with RIXI support. Remove
the redundant checks & duplication.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/mm/tlbex.c | 34 ++++++++++------------------------
 1 file changed, 10 insertions(+), 24 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0dd24b0..ce5a0ec 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1009,15 +1009,9 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
 	if (cpu_has_64bits) {
 		uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
 		uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
-		if (cpu_has_rixi) {
-			build_convert_pte_to_entrylo(p, tmp);
-			UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
-			build_convert_pte_to_entrylo(p, ptep);
-		} else {
-			build_convert_pte_to_entrylo(p, tmp);
-			UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
-			build_convert_pte_to_entrylo(p, ptep);
-		}
+		build_convert_pte_to_entrylo(p, tmp);
+		UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+		build_convert_pte_to_entrylo(p, ptep);
 		UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
 	} else {
 		int pte_off_even = sizeof(pte_t) / 2;
@@ -1049,21 +1043,13 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
 	UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
 	if (r45k_bvahwbug())
 		build_tlb_probe_entry(p);
-	if (cpu_has_rixi) {
-		build_convert_pte_to_entrylo(p, tmp);
-		if (r4k_250MHZhwbug())
-			UASM_i_MTC0(p, 0, C0_ENTRYLO0);
-		UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
-		build_convert_pte_to_entrylo(p, ptep);
-	} else {
-		build_convert_pte_to_entrylo(p, tmp);
-		if (r4k_250MHZhwbug())
-			UASM_i_MTC0(p, 0, C0_ENTRYLO0);
-		UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
-		build_convert_pte_to_entrylo(p, ptep);
-		if (r45k_bvahwbug())
-			uasm_i_mfc0(p, tmp, C0_INDEX);
-	}
+	build_convert_pte_to_entrylo(p, tmp);
+	if (r4k_250MHZhwbug())
+		UASM_i_MTC0(p, 0, C0_ENTRYLO0);
+	UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+	build_convert_pte_to_entrylo(p, ptep);
+	if (r45k_bvahwbug())
+		uasm_i_mfc0(p, tmp, C0_INDEX);
 	if (r4k_250MHZhwbug())
 		UASM_i_MTC0(p, 0, C0_ENTRYLO1);
 	UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
-- 
2.5.3

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#1230757 — [PATCH 4/6] MIPS: tidy EntryLo bit definitions, add PFN

FromPaul Burton <paul.burton@imgtec.com>
Date2015-09-22 20:50 +0200
Subject[PATCH 4/6] MIPS: tidy EntryLo bit definitions, add PFN
Message-ID<qbAND-5hQ-83@gated-at.bofh.it>
In reply to#1230749
Tidy up the definition of the EntryLo RI & XI bits using BITS_PER_LONG
rather than #ifdef'ing on CONFIG_64BIT, and add a definition for the
offset to the PFN field for use by a later patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/mipsregs.h | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index d3cd8ea..76dbb38 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -126,15 +126,9 @@
 #define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
 
 /* MIPS32/64 EntryLo bit definitions */
-#ifdef CONFIG_64BIT
-/* as read by dmfc0 */
-#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 62)
-#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 63)
-#else
-/* as read by mfc0 */
-#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << 30)
-#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << 31)
-#endif
+#define MIPS_ENTRYLO_PFN_SHIFT	6
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
 
 /*
  * Values for PageMask register
-- 
2.5.3

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