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[PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions

Started bySrinivas Kandagatla <srinivas.kandagatla@linaro.org>
First post2015-09-18 14:40 +0200
Last post2015-09-20 05:00 +0200
Articles 4 — 2 participants

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  [PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2015-09-18 14:40 +0200
    [PATCH 01/14] ARM: dts: apq8064: remove redundant i2c pinctrl properties Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2015-09-18 14:40 +0200
    [PATCH 04/14] devicetree: Add hardware rng entry to qcom-apq8064.dtsi Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - 2015-09-18 14:40 +0200
    Re: [PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions Andy Gross <agross@codeaurora.org> - 2015-09-20 05:00 +0200

#1227825 — [PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions

FromSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date2015-09-18 14:40 +0200
Subject[PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions
Message-ID<qa37j-2Hb-3@gated-at.bofh.it>
Hi Andy, 

Here are few cleanup and additions to the existing APQ8064 device tree.

Some of the patches are to do with princtrl cleanup which was always not
in the right place and some of the pinctrls were missing.
Other set of patches is to do with adding more devices like rtc rng
and pwr key for pmic 8921.
Last set of patches are related to pwrseq and SD card detect taking Stephens
comments into consideration.

Am resending John Stultz patch which was forgotten in the mailing list.

I have tested these patches on IFC6410.

Thanks,
srini

John Stultz (1):
  devicetree: Add hardware rng entry to qcom-apq8064.dtsi

Srinivas Kandagatla (13):
  ARM: dts: apq8064: remove redundant i2c pinctrl properties
  ARM: dts: ifc6410: remove unnecessary eeprom label
  ARM: dts: qs600: remove unnecessary eeprom label
  ARM: dts: apq8064: add pm8921 rtc
  ARM: dts: apq8064: add pm8921 pwrkey support
  ARM: dts: apq8064: Prefix the gsbi6 uart pins correctly
  ARM: dts: apq8064: add missing gsbi7 uart pinctrl
  ARM: dts: ifc6410: Add missing pinctrl to gsbi7 uart
  ARM: dts: qs600: Add missing pinctrl property for gsbi7 uart
  ARM: dts: ifc6410: Add pwrseq support for WLAN
  ARM: dts: qs600: add pwrseq support to WLAN
  ARM: dts: apq8064-ifc6410: add notify led support.
  ARM: dts: qs600: Add SD card detect support.

 arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 48 ++++++++++++++++++++---
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts  | 60 +++++++++++++++++++++++++----
 arch/arm/boot/dts/qcom-apq8064.dtsi         | 50 +++++++++++++++++++++++-
 3 files changed, 144 insertions(+), 14 deletions(-)

-- 
1.9.1

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#1227826 — [PATCH 01/14] ARM: dts: apq8064: remove redundant i2c pinctrl properties

FromSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date2015-09-18 14:40 +0200
Subject[PATCH 01/14] ARM: dts: apq8064: remove redundant i2c pinctrl properties
Message-ID<qa37k-2Hb-33@gated-at.bofh.it>
In reply to#1227825
This patch removes i2c pinctrl properties from board which which are now
mentioned in the SOC specific file. This will avoid redundant properties
across multiple board fiiles.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 11 -----------
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts  |  5 -----
 arch/arm/boot/dts/qcom-apq8064.dtsi         |  4 ++++
 3 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index 47c0282..80ab5b8 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -13,15 +13,6 @@
 	};
 
 	soc {
-		pinctrl@800000 {
-			i2c1_pins: i2c1 {
-				mux {
-					pins = "gpio20", "gpio21";
-					function = "gsbi1";
-				};
-			};
-		};
-
 		rpm@108000 {
 			regulators {
 				vin_lvs1_3_6-supply = <&pm8921_s4>;
@@ -96,8 +87,6 @@
 			i2c@12460000 {
 				status = "okay";
 				clock-frequency = <200000>;
-				pinctrl-0 = <&i2c1_pins>;
-				pinctrl-names = "default";
 
 				eeprom: eeprom@50 {
 					compatible = "24c02";
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index f3100da..b701f33 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -119,8 +119,6 @@
 			qcom,mode = <GSBI_PROT_I2C>;
 			i2c3: i2c@16280000 {
 				status = "okay";
-				pinctrl-0 = <&i2c3_pins>;
-				pinctrl-names = "default";
 			};
 		};
 
@@ -131,8 +129,6 @@
 			i2c@12460000 {
 				status = "okay";
 				clock-frequency = <200000>;
-				pinctrl-0 = <&i2c1_pins>;
-				pinctrl-names = "default";
 
 				eeprom: eeprom@52 {
 					compatible = "atmel,24c128";
@@ -148,7 +144,6 @@
 
 			serial@16540000 {
 				status = "ok";
-
 				pinctrl-names = "default";
 				pinctrl-0 = <&uart_pins>;
 			};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d2e94d6..53d5311 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -213,6 +213,8 @@
 
 			i2c1: i2c@12460000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-names = "default";
 				reg = <0x12460000 0x1000>;
 				interrupts = <0 194 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
@@ -258,6 +260,8 @@
 			ranges;
 			i2c3: i2c@16280000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
+				pinctrl-0 = <&i2c3_pins>;
+				pinctrl-names = "default";
 				reg = <0x16280000 0x1000>;
 				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI3_QUP_CLK>,
-- 
1.9.1

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#1227828 — [PATCH 04/14] devicetree: Add hardware rng entry to qcom-apq8064.dtsi

FromSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date2015-09-18 14:40 +0200
Subject[PATCH 04/14] devicetree: Add hardware rng entry to qcom-apq8064.dtsi
Message-ID<qa37l-2Hb-51@gated-at.bofh.it>
In reply to#1227825
From: John Stultz <john.stultz@linaro.org>

Add devicetree data to add support for hw_rng support
to the apq8064 dts.

Tested on the Nexus7 (2013).

Cc: Kumar Gala <galak@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: devicetree@vger.kernel.org
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 53d5311..d973832 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -315,6 +315,13 @@
 			};
 		};
 
+		rng@1a500000 {
+			compatible = "qcom,prng";
+			reg = <0x1a500000 0x200>;
+			clocks = <&gcc PRNG_CLK>;
+			clock-names = "core";
+		};
+
 		qcom,ssbi@500000 {
 			compatible = "qcom,ssbi";
 			reg = <0x00500000 0x1000>;
-- 
1.9.1

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#1228812

FromAndy Gross <agross@codeaurora.org>
Date2015-09-20 05:00 +0200
Message-ID<qaD18-3RA-1@gated-at.bofh.it>
In reply to#1227825
On Fri, Sep 18, 2015 at 01:29:31PM +0100, Srinivas Kandagatla wrote:
> Hi Andy, 
> 
> Here are few cleanup and additions to the existing APQ8064 device tree.
> 
> Some of the patches are to do with princtrl cleanup which was always not
> in the right place and some of the pinctrls were missing.
> Other set of patches is to do with adding more devices like rtc rng
> and pwr key for pmic 8921.
> Last set of patches are related to pwrseq and SD card detect taking Stephens
> comments into consideration.

These all look fine.  I tested in ifc6410 as well.  I'll test on qs600 to be
sure.

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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