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Groups > linux.kernel > #1323352 > unrolled thread
| Started by | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| First post | 2016-02-01 18:40 +0100 |
| Last post | 2016-02-02 09:40 +0100 |
| Articles | 20 on this page of 58 — 17 participants |
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[PATCH 00/11] arm64: Introduce Allwinner A64 and Pine64 support Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:40 +0100
[PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver Jean-Francois Moine <moinejf@free.fr> - 2016-02-01 19:50 +0100
Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver André Przywara <andre.przywara@arm.com> - 2016-02-02 00:10 +0100
[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Karsten Merker <merker@debian.org> - 2016-02-01 20:10 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi André Przywara <andre.przywara@arm.com> - 2016-02-02 00:10 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Jens Kuske <jenskuske@gmail.com> - 2016-02-02 17:30 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Andre Przywara <andre.przywara@arm.com> - 2016-02-02 17:50 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Jens Kuske <jenskuske@gmail.com> - 2016-02-02 18:50 +0100
Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Chen-Yu Tsai <wens@csie.org> - 2016-02-05 10:00 +0100
Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 10:00 +0100
Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi Andre Przywara <andre.przywara@arm.com> - 2016-02-08 10:50 +0100
[PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
[tip:irq/urgent] irqchip/sun4i: Fix compilation outside of arch/ arm tip-bot for Andre Przywara <tipbot@zytor.com> - 2016-02-02 16:00 +0100
Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm Matthias Brugger <matthias.bgg@gmail.com> - 2016-02-02 16:20 +0100
Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm Andre Przywara <andre.przywara@arm.com> - 2016-02-02 16:40 +0100
Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm Matthias Brugger <matthias.bgg@gmail.com> - 2016-02-02 18:00 +0100
[PATCH 08/11] clk: sunxi: improve error reporting for the mux clock Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 08/11] clk: sunxi: improve error reporting for the mux clock Andre Przywara <andre.przywara@arm.com> - 2016-02-02 19:10 +0100
Re: [PATCH 08/11] clk: sunxi: improve error reporting for the mux clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 19:10 +0100
[PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name Rob Herring <robh@kernel.org> - 2016-02-08 17:00 +0100
Re: [PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name Andre Przywara <andre.przywara@arm.com> - 2016-02-08 17:10 +0100
[PATCH 11/11] arm64: dts: add Pine64 support Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [linux-sunxi] [PATCH 11/11] arm64: dts: add Pine64 support Karsten Merker <merker@debian.org> - 2016-02-01 20:30 +0100
Re: [linux-sunxi] [PATCH 11/11] arm64: dts: add Pine64 support André Przywara <andre.przywara@arm.com> - 2016-02-02 00:10 +0100
Re: [PATCH 11/11] arm64: dts: add Pine64 support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-05 10:10 +0100
Re: [PATCH 11/11] arm64: dts: add Pine64 support Andre Przywara <andre.przywara@arm.com> - 2016-02-05 11:10 +0100
Re: [linux-sunxi] Re: [PATCH 11/11] arm64: dts: add Pine64 support Julian Calaby <julian.calaby@gmail.com> - 2016-02-08 02:00 +0100
[PATCH 04/11] arm64: Introduce Allwinner SoC config option Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 04/11] arm64: Introduce Allwinner SoC config option Matthias Brugger <matthias.bgg@gmail.com> - 2016-02-02 16:30 +0100
Re: [PATCH 04/11] arm64: Introduce Allwinner SoC config option Andre Przywara <andre.przywara@arm.com> - 2016-02-02 16:40 +0100
Re: [PATCH 04/11] arm64: Introduce Allwinner SoC config option Arnd Bergmann <arnd@arndb.de> - 2016-02-02 17:10 +0100
[PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Karsten Merker <merker@debian.org> - 2016-02-01 19:30 +0100
Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Karsten Merker <merker@debian.org> - 2016-02-01 19:50 +0100
Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC André Przywara <andre.przywara@arm.com> - 2016-02-02 00:10 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC André Przywara <andre.przywara@arm.com> - 2016-02-02 00:00 +0100
Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Siarhei Siamashka <siarhei.siamashka@gmail.com> - 2016-02-02 03:00 +0100
Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Andre Przywara <andre.przywara@arm.com> - 2016-02-02 15:30 +0100
Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 18:40 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 11:10 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Chen-Yu Tsai <wens@csie.org> - 2016-02-02 11:20 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Andre Przywara <andre.przywara@arm.com> - 2016-02-02 18:00 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-04 20:00 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Andre Przywara <andre.przywara@arm.com> - 2016-02-08 17:00 +0100
Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC Rob Herring <robh@kernel.org> - 2016-02-08 17:00 +0100
[PATCH 02/11] crypto: sunxi-ss: prevent compilation on 64-bit Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 02/11] crypto: sunxi-ss: prevent compilation on 64-bit Herbert Xu <herbert@gondor.apana.org.au> - 2016-02-02 04:20 +0100
Re: [linux-sunxi] [PATCH 02/11] crypto: sunxi-ss: prevent compilation on 64-bit LABBE Corentin <clabbe.montjoie@gmail.com> - 2016-02-02 09:50 +0100
Re: [PATCH 02/11] crypto: sunxi-ss: prevent compilation on 64-bit Herbert Xu <herbert@gondor.apana.org.au> - 2016-02-06 08:50 +0100
[PATCH 03/11] drivers: rtc: allow compilation of sun6i RTC for all sunxi SoCs Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 03/11] drivers: rtc: allow compilation of sun6i RTC for all sunxi SoCs Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 10:50 +0100
Re: [PATCH 03/11] drivers: rtc: allow compilation of sun6i RTC for all sunxi SoCs Alexandre Belloni <alexandre.belloni@free-electrons.com> - 2016-02-05 00:00 +0100
[PATCH 09/11] clk: sunxi: add critical-clocks property to mux clocks Andre Przywara <andre.przywara@arm.com> - 2016-02-01 18:50 +0100
Re: [PATCH 00/11] arm64: Introduce Allwinner A64 and Pine64 support André Przywara <andre.przywara@arm.com> - 2016-02-02 09:20 +0100
Re: [PATCH 00/11] arm64: Introduce Allwinner A64 and Pine64 support lists.nick.betteridge@gmail.com - 2016-02-02 09:40 +0100
Page 1 of 3 [1] 2 3 Next page →
| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-01 18:40 +0100 |
| Subject | [PATCH 00/11] arm64: Introduce Allwinner A64 and Pine64 support |
| Message-ID | <qXqCd-6ht-1@gated-at.bofh.it> |
Hi, this series provides initial support for the Allwinner A64 SoC, which is based on four ARM Cortex-A53 cores implementing the ARMv8 64-bit architecture. On top of this there is also initial support for the Pine64 board, for which you can find more information and links in the linux-sunxi Wiki [1]. The resulting kernel boots fine on my development samples I have here, though the actual boot process is a bit involved at the moment. You can find more information and a ready-to-flash image here [2]. The first three patches fix warnings that appear when compiling some existing Allwinner drivers for arm64. Patch 4/11 enables the Allwinner/sunxi platform for the arm64 architecture, so one can select the required drivers during configuration. Patch 5/11 adds the (currently) inevitable pinctrl driver, this addresses the comments I got from an earlier post and also fixes the IRQ banking which I got wrong before. Patch 6-9 pimp the sunxi clocks drivers to deal with the A64. It adds a new generic driver for the bus clock gates which relies on DT for providing the parent relationship. That makes adding new SoCs much easier, since there should be no more kernel code changes necessary. Also the sunxi mux clocks learns about the critical-clocks property, again this moves a previously hard-coded information into the DT. The final two patches eventually add the A64 .dtsi and the actual dts files for the two Pine64 board variants. In the moment we support the basic peripherals like GIC, timer, clocks, GPIO and UART. The MMC support seems to fail to find the regulator at the moment, I will send a follow up patch once this is fixed. Meanwhile you can use an initrd to get to a prompt. Please have a look and comment on the patches. We might want to split the series if some patches seem too controversial for being merged soonish, please let me know if this is the case and I am happy to rearrange the series. The patches are based on mripard/sunxi/for-next[3] as of yesterday and can be found in the repo over here[4]. Cheers, Andre [1] http://linux-sunxi.org/Pine64 [2] https://github.com/apritzel/pine64 [3] https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/log/?h=sunxi/for-next [4] https://github.com/apritzel/linux/commits/a64-v1 Andre Przywara (11): irqchip: sun4i: fix compilation outside of arch/arm crypto: sunxi-ss: prevent compilation on 64-bit drivers: rtc: allow compilation of sun6i RTC for all sunxi SoCs arm64: Introduce Allwinner SoC config option drivers: pinctrl: add driver for Allwinner A64 SoC clk: sunxi: add generic multi-parent bus clock gates driver clk: sunxi: add generic allwinner,sunxi name clk: sunxi: improve error reporting for the mux clock clk: sunxi: add critical-clocks property to mux clocks arm64: dts: add Allwinner A64 SoC .dtsi arm64: dts: add Pine64 support Documentation/devicetree/bindings/arm/sunxi.txt | 5 + Documentation/devicetree/bindings/clock/sunxi.txt | 1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm64/Kconfig.platforms | 7 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 + arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++ arch/arm64/boot/dts/allwinner/pine64.dts | 58 ++ arch/arm64/boot/dts/allwinner/pine64_common.dtsi | 76 +++ arch/arm64/boot/dts/allwinner/pine64_plus.dts | 59 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-multi-gates.c | 105 ++++ drivers/clk/sunxi/clk-sunxi.c | 43 +- drivers/crypto/Kconfig | 2 +- drivers/irqchip/irq-sun4i.c | 1 - drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-a64.c | 606 +++++++++++++++++++++ drivers/rtc/Kconfig | 7 +- 20 files changed, 1550 insertions(+), 17 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts create mode 100644 drivers/clk/sunxi/clk-multi-gates.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c -- 2.6.4
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-01 18:50 +0100 |
| Subject | [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver |
| Message-ID | <qXqLU-6lT-3@gated-at.bofh.it> |
| In reply to | #1323352 |
The Allwinner H3 SoC introduced bus clock gates with potentially
different parents per clock gate. The H3 driver chose to hardcode the
actual parent clock relation in the code.
Add a new driver (which has the potential to drive the H3 and also
the simple clock gates as well) which uses the power of DT to describe
this relationship in an elegant and flexible way.
Using one subnode for every parent clock we get away with a single
DT compatible match, which can be used as a fallback value in the
actual DTs without the need to add specific compatible strings to the
code. This avoids adding a new driver or function for every new SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
Changelog RFC .. v1:
- fix IRQ muxes to cover the three banks of the SoC
- amend naming of PCM pins
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++
2 files changed, 106 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-multi-gates.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3fd7901..3a9dc31 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += clk-a10-ve.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
obj-y += clk-simple-gates.o
+obj-y += clk-multi-gates.o
obj-y += clk-sun8i-bus-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
diff --git a/drivers/clk/sunxi/clk-multi-gates.c b/drivers/clk/sunxi/clk-multi-gates.c
new file mode 100644
index 0000000..76e715a
--- /dev/null
+++ b/drivers/clk/sunxi/clk-multi-gates.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * Based on clk-sun8i-bus-gates.c, which is:
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ * Based on clk-simple-gates.c, which is:
+ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_parse_parent(struct device_node *node,
+ struct clk_onecell_data *clk_data,
+ void __iomem *reg)
+{
+ const char *parent = of_clk_get_parent_name(node, 0);
+ const char *clk_name;
+ struct property *prop;
+ struct clk *clk;
+ const __be32 *p;
+ int index, i = 0;
+
+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+ of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+
+ clk = clk_register_gate(NULL, clk_name, parent, 0,
+ reg + 4 * (index / 32), index % 32,
+ 0, &gates_lock);
+ i++;
+ if (IS_ERR(clk)) {
+ pr_warn("could not register gate clock \"%s\"\n",
+ clk_name);
+ continue;
+ }
+ if (clk_data->clks[index])
+ pr_warn("bus-gate clock %s: index #%d already registered as %s\n",
+ clk_name, index, "?");
+ else
+ clk_data->clks[index] = clk;
+ }
+}
+
+static void __init sunxi_multi_bus_gates_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *child;
+ struct property *prop;
+ struct resource res;
+ void __iomem *reg;
+ const __be32 *p;
+ int number = 0;
+ int index;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err_unmap;
+
+ for_each_child_of_node(node, child)
+ of_property_for_each_u32(child, "clock-indices", prop, p, index)
+ number = max(number, index);
+
+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_free_data;
+
+ for_each_child_of_node(node, child)
+ sunxi_parse_parent(child, clk_data, reg);
+
+ clk_data->clk_num = number + 1;
+ if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data))
+ pr_err("registering bus-gate clock %s failed\n", node->name);
+
+ return;
+
+err_free_data:
+ kfree(clk_data);
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+
+CLK_OF_DECLARE(sunxi_multi_bus_gates, "allwinner,sunxi-multi-bus-gates-clk",
+ sunxi_multi_bus_gates_init);
--
2.6.4
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| From | Jean-Francois Moine <moinejf@free.fr> |
|---|---|
| Date | 2016-02-01 19:50 +0100 |
| Subject | Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver |
| Message-ID | <qXrHY-6ZT-13@gated-at.bofh.it> |
| In reply to | #1323358 |
On Mon, 1 Feb 2016 17:39:25 +0000 Andre Przywara <andre.przywara@arm.com> wrote: > The Allwinner H3 SoC introduced bus clock gates with potentially > different parents per clock gate. The H3 driver chose to hardcode the > actual parent clock relation in the code. > Add a new driver (which has the potential to drive the H3 and also > the simple clock gates as well) which uses the power of DT to describe > this relationship in an elegant and flexible way. > Using one subnode for every parent clock we get away with a single > DT compatible match, which can be used as a fallback value in the > actual DTs without the need to add specific compatible strings to the > code. This avoids adding a new driver or function for every new SoC. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > Changelog RFC .. v1: > - fix IRQ muxes to cover the three banks of the SoC > - amend naming of PCM pins > > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 106 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-multi-gates.c [snip] Glad to see that things are moving to the right way. Thanks. Acked-by: Jean-Francois Moine <moinejf@free.fr> -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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| From | André Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-02 00:10 +0100 |
| Subject | Re: [PATCH 06/11] clk: sunxi: add generic multi-parent bus clock gates driver |
| Message-ID | <qXvLA-1Cx-7@gated-at.bofh.it> |
| In reply to | #1323405 |
On 01/02/16 18:40, Jean-Francois Moine wrote: > On Mon, 1 Feb 2016 17:39:25 +0000 > Andre Przywara <andre.przywara@arm.com> wrote: > >> The Allwinner H3 SoC introduced bus clock gates with potentially >> different parents per clock gate. The H3 driver chose to hardcode the >> actual parent clock relation in the code. >> Add a new driver (which has the potential to drive the H3 and also >> the simple clock gates as well) which uses the power of DT to describe >> this relationship in an elegant and flexible way. >> Using one subnode for every parent clock we get away with a single >> DT compatible match, which can be used as a fallback value in the >> actual DTs without the need to add specific compatible strings to the >> code. This avoids adding a new driver or function for every new SoC. >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >> --- >> Changelog RFC .. v1: >> - fix IRQ muxes to cover the three banks of the SoC >> - amend naming of PCM pins Just got embarrassed with seeing that this changelog here actually belongs into the previous patch :$ >> >> drivers/clk/sunxi/Makefile | 1 + >> drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++ >> 2 files changed, 106 insertions(+) >> create mode 100644 drivers/clk/sunxi/clk-multi-gates.c > [snip] > > Glad to see that things are moving to the right way. Thanks. > Acked-by: Jean-Francois Moine <moinejf@free.fr> Thanks! I am relived to hear that (and hope that others agree as well ;-) If people are Ok with that approach I can do patches to move all existing clock gates into one driver, but I guess this would be part of a later series. Cheers, Andre.
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-01 18:50 +0100 |
| Subject | [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXqLU-6lT-11@gated-at.bofh.it> |
| In reply to | #1323352 |
The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
and the typical tablet / TV box peripherals.
The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
the peripherals and the memory map.
Although the cores are proper 64-bit ones, the whole SoC is actually
limited to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
3 files changed, 585 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 980e065..4a83853 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
+ allwinner,a64
For Allwinner SoCs without any specific needs the generic fallback value of:
allwinner,sunxi
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..44b0c6c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -77,6 +77,7 @@ Required properties:
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
+ "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
Required properties for all clocks:
- reg : shall be the control register address for the clock.
diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
new file mode 100644
index 0000000..8dce10f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ compatible = "allwinner,a64", "allwinner,sunxi";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2";
+ };
+
+ pll6d2: pll6d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll6 0>;
+ clock-output-names = "pll6d2";
+ };
+
+ /* dummy clock until pll6 can be reused */
+ pll8: pll8_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+ clock-output-names = "pll8";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ critical-clocks = <0>;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: ahb2_clk@01c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&pll6d2>;
+ clock-output-names = "ahb2";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: apb2_clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
+ clock-output-names = "apb2";
+ };
+
+ bus_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,a64-bus-gates-clk",
+ "allwinner,sunxi-multi-bus-gates-clk";
+ reg = <0x01c20060 0x14>;
+ ahb1_parent {
+ clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>,
+ <9>, <10>,
+ <13>, <14>,
+ <18>, <19>,
+ <20>, <21>,
+ <23>, <24>,
+ <25>, <28>,
+ <32>, <35>,
+ <36>, <37>,
+ <40>, <43>,
+ <44>, <52>,
+ <53>, <54>,
+ <135>;
+ clock-output-names = "bus_mipidsi", "bus_ce",
+ "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2",
+ "bus_nand", "bus_sdram",
+ "bus_ts", "bus_hstimer",
+ "bus_spi0", "bus_spi1",
+ "bus_otg", "bus_otg_ehci0",
+ "bus_ehci0", "bus_otg_ohci0",
+ "bus_ve", "bus_lcd0",
+ "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_hdmi",
+ "bus_de", "bus_gpu",
+ "bus_msgbox", "bus_spinlock",
+ "bus_dbg";
+ };
+ ahb2_parent {
+ clocks = <&ahb2>;
+ clock-indices = <17>, <29>;
+ clock-output-names = "bus_gmac", "bus_ohci0";
+ };
+ apb1_parent {
+ clocks = <&apb1>;
+ clock-indices = <64>, <65>,
+ <69>, <72>,
+ <76>, <77>,
+ <78>;
+ clock-output-names = "bus_codec", "bus_spdif",
+ "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1",
+ "bus_i2s2";
+ };
+ abp2_parent {
+ clocks = <&apb2>;
+ clock-indices = <96>, <97>,
+ <98>, <101>,
+ <112>, <113>,
+ <114>, <115>,
+ <116>;
+ clock-output-names = "bus_i2c0", "bus_i2c1",
+ "bus_i2c2", "bus_scr",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_uart4";
+ };
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+ };
+
+ regulators {
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,a64-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 69>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB8", "PB9";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PF2", "PF3";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins: uart1@0 {
+ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins: uart2@0 {
+ allwinner,pins = "PB0", "PB1", "PB2", "PB3";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PD0", "PD1";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_b: uart3@1 {
+ allwinner,pins = "PH4", "PH5", "PH6", "PH7";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_pins: uart4@0 {
+ allwinner,pins = "PD2", "PD3", "PD4", "PD5";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_default_cd_pin: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins: mmc2@0 {
+ allwinner,pins = "PC1", "PC5", "PC6", "PC8",
+ "PC9", "PC10";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 112>;
+ resets = <&apb2_rst 16>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 113>;
+ resets = <&apb2_rst 17>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 114>;
+ resets = <&apb2_rst 18>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 115>;
+ resets = <&apb2_rst 19>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 116>;
+ resets = <&apb2_rst 20>;
+ reset-names = "apb2";
+ status = "disabled";
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gic: interrupt-controller@{
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x01C81000 0x1000>,
+ <0x01C82000 0x2000>,
+ <0x01C84000 0x2000>,
+ <0x01C86000 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+};
--
2.6.4
[toc] | [prev] | [next] | [standalone]
| From | Karsten Merker <merker@debian.org> |
|---|---|
| Date | 2016-02-01 20:10 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXs1k-7oi-13@gated-at.bofh.it> |
| In reply to | #1323359 |
Hello,
a few tiny spelling nitpicks in case you should do a V2:
On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
s/is low-cost SoC/is a low-cost SoC/
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
s/Soc/SoC/
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
> 3 files changed, 585 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> allwinner,sun9i-a80
> + allwinner,a64
Please see my followup to patch No. 5 in this series.
s/allwinner,a64/allwinner,sun50i-a64/ ?
>
> For Allwinner SoCs without any specific needs the generic fallback value of:
> allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
see above
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
see above - the dts and dtsi names for the other Allwinner SoCs contain
the SoC family.
> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + compatible = "allwinner,a64", "allwinner,sunxi";
see above
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2", "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6", "pll6x2";
> + };
> +
> + pll6d2: pll6d2_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&pll6 0>;
> + clock-output-names = "pll6d2";
> + };
> +
> + /* dummy clock until pll6 can be reused */
> + pll8: pll8_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <1>;
> + clock-output-names = "pll8";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + critical-clocks = <0>;
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1: ahb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> + clock-output-names = "ahb1";
> + };
> +
> + ahb2: ahb2_clk@01c2005c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-h3-ahb2-clk";
> + reg = <0x01c2005c 0x4>;
> + clocks = <&ahb1>, <&pll6d2>;
> + clock-output-names = "ahb2";
> + };
> +
> + apb1: apb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + apb2: apb2_clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> + clock-output-names = "apb2";
> + };
> +
> + bus_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,a64-bus-gates-clk",
see above
> + "allwinner,sunxi-multi-bus-gates-clk";
> + reg = <0x01c20060 0x14>;
> + ahb1_parent {
> + clocks = <&ahb1>;
> + clock-indices = <1>, <5>,
> + <6>, <8>,
> + <9>, <10>,
> + <13>, <14>,
> + <18>, <19>,
> + <20>, <21>,
> + <23>, <24>,
> + <25>, <28>,
> + <32>, <35>,
> + <36>, <37>,
> + <40>, <43>,
> + <44>, <52>,
> + <53>, <54>,
> + <135>;
> + clock-output-names = "bus_mipidsi", "bus_ce",
> + "bus_dma", "bus_mmc0",
> + "bus_mmc1", "bus_mmc2",
> + "bus_nand", "bus_sdram",
> + "bus_ts", "bus_hstimer",
> + "bus_spi0", "bus_spi1",
> + "bus_otg", "bus_otg_ehci0",
> + "bus_ehci0", "bus_otg_ohci0",
> + "bus_ve", "bus_lcd0",
> + "bus_lcd1", "bus_deint",
> + "bus_csi", "bus_hdmi",
> + "bus_de", "bus_gpu",
> + "bus_msgbox", "bus_spinlock",
> + "bus_dbg";
> + };
> + ahb2_parent {
> + clocks = <&ahb2>;
> + clock-indices = <17>, <29>;
> + clock-output-names = "bus_gmac", "bus_ohci0";
> + };
> + apb1_parent {
> + clocks = <&apb1>;
> + clock-indices = <64>, <65>,
> + <69>, <72>,
> + <76>, <77>,
> + <78>;
> + clock-output-names = "bus_codec", "bus_spdif",
> + "bus_pio", "bus_ths",
> + "bus_i2s0", "bus_i2s1",
> + "bus_i2s2";
> + };
> + abp2_parent {
> + clocks = <&apb2>;
> + clock-indices = <96>, <97>,
> + <98>, <101>,
> + <112>, <113>,
> + <114>, <115>,
> + <116>;
> + clock-output-names = "bus_i2c0", "bus_i2c1",
> + "bus_i2c2", "bus_scr",
> + "bus_uart0", "bus_uart1",
> + "bus_uart2", "bus_uart3",
> + "bus_uart4";
> + };
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> + };
> +
> + regulators {
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&bus_gates 8>,
> + <&mmc0_clk 0>,
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 8>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&bus_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 9>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&bus_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 10>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "allwinner,a64-pinctrl";
see above
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&bus_gates 69>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart0_pins_a: uart0@0 {
> + allwinner,pins = "PB8", "PB9";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart0_pins_b: uart0@1 {
> + allwinner,pins = "PF2", "PF3";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart1_pins: uart1@0 {
> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart2_pins: uart2@0 {
> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> + allwinner,function = "uart2";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_a: uart3@0 {
> + allwinner,pins = "PD0", "PD1";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_b: uart3@1 {
> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart4_pins: uart4@0 {
> + allwinner,pins = "PD2", "PD3", "PD4", "PD5";
> + allwinner,function = "uart4";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc0_pins: mmc0@0 {
> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc0_default_cd_pin: mmc0_cd_pin@0 {
> + allwinner,pins = "PF6";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> + };
> +
> + mmc1_pins: mmc1@0 {
> + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
> + "PG4", "PG5";
> + allwinner,function = "mmc1";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc2_pins: mmc2@0 {
> + allwinner,pins = "PC1", "PC5", "PC6", "PC8",
> + "PC9", "PC10";
> + allwinner,function = "mmc2";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> +
> + ahb_rst: reset@01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset@01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset@01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + uart0: serial@01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 112>;
> + resets = <&apb2_rst 16>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 113>;
> + resets = <&apb2_rst 17>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 114>;
> + resets = <&apb2_rst 18>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart3: serial@01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 115>;
> + resets = <&apb2_rst 19>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart4: serial@01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 116>;
> + resets = <&apb2_rst 20>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + rtc: rtc@01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gic: interrupt-controller@{
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> +
> + reg = <0x01C81000 0x1000>,
> + <0x01C82000 0x2000>,
> + <0x01C84000 0x2000>,
> + <0x01C86000 0x2000>;
> + interrupts = <GIC_PPI 9
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +};
> --
> 2.6.4
Regards,
Karsten
--
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.
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| From | André Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-02 00:10 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXvLA-1Cx-11@gated-at.bofh.it> |
| In reply to | #1323416 |
On 01/02/16 19:05, Karsten Merker wrote:
> Hello,
>
> a few tiny spelling nitpicks in case you should do a V2:
Definitely! ;-)
>
> On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
>
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>
> s/is low-cost SoC/is a low-cost SoC/
>
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>
> s/Soc/SoC/
Thanks for catching those!
>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
>> 3 files changed, 585 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>> allwinner,sun8i-a83t
>> allwinner,sun8i-h3
>> allwinner,sun9i-a80
>> + allwinner,a64
>
> Please see my followup to patch No. 5 in this series.
> s/allwinner,a64/allwinner,sun50i-a64/ ?
As explained in the first email, rather not, especially if it is about
DT namings.
>>
>> For Allwinner SoCs without any specific needs the generic fallback value of:
>> allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>
> see above
>
>>
>> Required properties for all clocks:
>> - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>
> see above - the dts and dtsi names for the other Allwinner SoCs contain
> the SoC family.
... mostly because the arm DTs are all in one directory, and just some
a<xx>.dtsi is then indeed not very specific. But arm64 fortunately has
per-vendor directories, so things are pretty well separated. If a64.dtsi
is deemed too short, I could call it allwinner_a64.dtsi or maybe
sunxi_a64.dtsi, but I'd rather avoid sun50i-a64.dtsi.
Also looking at the other arm64 DTs I see a lot of short names, just
using the (marketing) chip name as the stub.
Similar reasoning for the other occurrences below.
Cheers,
Andre.
>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + compatible = "allwinner,a64", "allwinner,sunxi";
>
> see above
>
>> + interrupt-parent = <&gic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <1>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <2>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <3>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-0.2", "arm,psci";
>> + method = "smc";
>> + cpu_suspend = <0xc4000001>;
>> + cpu_off = <0x84000002>;
>> + cpu_on = <0xc4000003>;
>> + };
>> +
>> + memory {
>> + device_type = "memory";
>> + reg = <0x40000000 0>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: osc32k_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6", "pll6x2";
>> + };
>> +
>> + pll6d2: pll6d2_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-factor-clock";
>> + clock-div = <2>;
>> + clock-mult = <1>;
>> + clocks = <&pll6 0>;
>> + clock-output-names = "pll6d2";
>> + };
>> +
>> + /* dummy clock until pll6 can be reused */
>> + pll8: pll8_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <1>;
>> + clock-output-names = "pll8";
>> + };
>> +
>> + cpu: cpu_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + critical-clocks = <0>;
>> + };
>> +
>> + axi: axi_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1: ahb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb2: ahb2_clk@01c2005c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-h3-ahb2-clk";
>> + reg = <0x01c2005c 0x4>;
>> + clocks = <&ahb1>, <&pll6d2>;
>> + clock-output-names = "ahb2";
>> + };
>> +
>> + apb1: apb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb2: apb2_clk@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + bus_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,a64-bus-gates-clk",
>
> see above
>
>> + "allwinner,sunxi-multi-bus-gates-clk";
>> + reg = <0x01c20060 0x14>;
>> + ahb1_parent {
>> + clocks = <&ahb1>;
>> + clock-indices = <1>, <5>,
>> + <6>, <8>,
>> + <9>, <10>,
>> + <13>, <14>,
>> + <18>, <19>,
>> + <20>, <21>,
>> + <23>, <24>,
>> + <25>, <28>,
>> + <32>, <35>,
>> + <36>, <37>,
>> + <40>, <43>,
>> + <44>, <52>,
>> + <53>, <54>,
>> + <135>;
>> + clock-output-names = "bus_mipidsi", "bus_ce",
>> + "bus_dma", "bus_mmc0",
>> + "bus_mmc1", "bus_mmc2",
>> + "bus_nand", "bus_sdram",
>> + "bus_ts", "bus_hstimer",
>> + "bus_spi0", "bus_spi1",
>> + "bus_otg", "bus_otg_ehci0",
>> + "bus_ehci0", "bus_otg_ohci0",
>> + "bus_ve", "bus_lcd0",
>> + "bus_lcd1", "bus_deint",
>> + "bus_csi", "bus_hdmi",
>> + "bus_de", "bus_gpu",
>> + "bus_msgbox", "bus_spinlock",
>> + "bus_dbg";
>> + };
>> + ahb2_parent {
>> + clocks = <&ahb2>;
>> + clock-indices = <17>, <29>;
>> + clock-output-names = "bus_gmac", "bus_ohci0";
>> + };
>> + apb1_parent {
>> + clocks = <&apb1>;
>> + clock-indices = <64>, <65>,
>> + <69>, <72>,
>> + <76>, <77>,
>> + <78>;
>> + clock-output-names = "bus_codec", "bus_spdif",
>> + "bus_pio", "bus_ths",
>> + "bus_i2s0", "bus_i2s1",
>> + "bus_i2s2";
>> + };
>> + abp2_parent {
>> + clocks = <&apb2>;
>> + clock-indices = <96>, <97>,
>> + <98>, <101>,
>> + <112>, <113>,
>> + <114>, <115>,
>> + <116>;
>> + clock-output-names = "bus_i2c0", "bus_i2c1",
>> + "bus_i2c2", "bus_scr",
>> + "bus_uart0", "bus_uart1",
>> + "bus_uart2", "bus_uart3",
>> + "bus_uart4";
>> + };
>> + };
>> +
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc0",
>> + "mmc0_output",
>> + "mmc0_sample";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc1",
>> + "mmc1_output",
>> + "mmc1_sample";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc2",
>> + "mmc2_output",
>> + "mmc2_sample";
>> + };
>> + };
>> +
>> + regulators {
>> + reg_vcc3v3: vcc3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&bus_gates 8>,
>> + <&mmc0_clk 0>,
>> + <&mmc0_clk 1>,
>> + <&mmc0_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&bus_gates 9>,
>> + <&mmc1_clk 0>,
>> + <&mmc1_clk 1>,
>> + <&mmc1_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&bus_gates 10>,
>> + <&mmc2_clk 0>,
>> + <&mmc2_clk 1>,
>> + <&mmc2_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,a64-pinctrl";
>
> see above
>
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bus_gates 69>;
>> + gpio-controller;
>> + #gpio-cells = <3>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PB8", "PB9";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart0_pins_b: uart0@1 {
>> + allwinner,pins = "PF2", "PF3";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart1_pins: uart1@0 {
>> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> + allwinner,function = "uart1";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart2_pins: uart2@0 {
>> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> + allwinner,function = "uart2";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_a: uart3@0 {
>> + allwinner,pins = "PD0", "PD1";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_b: uart3@1 {
>> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart4_pins: uart4@0 {
>> + allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>> + allwinner,function = "uart4";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc0_pins: mmc0@0 {
>> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>> + "PF4", "PF5";
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc0_default_cd_pin: mmc0_cd_pin@0 {
>> + allwinner,pins = "PF6";
>> + allwinner,function = "gpio_in";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>> + };
>> +
>> + mmc1_pins: mmc1@0 {
>> + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>> + "PG4", "PG5";
>> + allwinner,function = "mmc1";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc2_pins: mmc2@0 {
>> + allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>> + "PC9", "PC10";
>> + allwinner,function = "mmc2";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> + };
>> +
>> + ahb_rst: reset@01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset@01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset@01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 112>;
>> + resets = <&apb2_rst 16>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 113>;
>> + resets = <&apb2_rst 17>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 114>;
>> + resets = <&apb2_rst 18>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 115>;
>> + resets = <&apb2_rst 19>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 116>;
>> + resets = <&apb2_rst 20>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + rtc: rtc@01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>> + gic: interrupt-controller@{
>> + compatible = "arm,gic-400";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> +
>> + reg = <0x01C81000 0x1000>,
>> + <0x01C82000 0x2000>,
>> + <0x01C84000 0x2000>,
>> + <0x01C86000 0x2000>;
>> + interrupts = <GIC_PPI 9
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +};
>> --
>> 2.6.4
>
> Regards,
> Karsten
>
[toc] | [prev] | [next] | [standalone]
| From | Jens Kuske <jenskuske@gmail.com> |
|---|---|
| Date | 2016-02-02 17:30 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXM03-5FW-25@gated-at.bofh.it> |
| In reply to | #1323359 |
Hi,
On 01/02/16 18:39, Andre Przywara wrote:
> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
> 3 files changed, 585 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> allwinner,sun9i-a80
> + allwinner,a64
>
> For Allwinner SoCs without any specific needs the generic fallback value of:
> allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + compatible = "allwinner,a64", "allwinner,sunxi";
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2", "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6", "pll6x2";
> + };
> +
> + pll6d2: pll6d2_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&pll6 0>;
> + clock-output-names = "pll6d2";
> + };
> +
> + /* dummy clock until pll6 can be reused */
> + pll8: pll8_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <1>;
> + clock-output-names = "pll8";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + critical-clocks = <0>;
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1: ahb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> + clock-output-names = "ahb1";
> + };
> +
> + ahb2: ahb2_clk@01c2005c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-h3-ahb2-clk";
> + reg = <0x01c2005c 0x4>;
> + clocks = <&ahb1>, <&pll6d2>;
> + clock-output-names = "ahb2";
> + };
> +
> + apb1: apb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + apb2: apb2_clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> + clock-output-names = "apb2";
> + };
> +
> + bus_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,a64-bus-gates-clk",
> + "allwinner,sunxi-multi-bus-gates-clk";
> + reg = <0x01c20060 0x14>;
> + ahb1_parent {
> + clocks = <&ahb1>;
> + clock-indices = <1>, <5>,
> + <6>, <8>,
> + <9>, <10>,
> + <13>, <14>,
> + <18>, <19>,
> + <20>, <21>,
> + <23>, <24>,
> + <25>, <28>,
> + <32>, <35>,
> + <36>, <37>,
> + <40>, <43>,
> + <44>, <52>,
> + <53>, <54>,
> + <135>;
> + clock-output-names = "bus_mipidsi", "bus_ce",
> + "bus_dma", "bus_mmc0",
> + "bus_mmc1", "bus_mmc2",
> + "bus_nand", "bus_sdram",
> + "bus_ts", "bus_hstimer",
> + "bus_spi0", "bus_spi1",
> + "bus_otg", "bus_otg_ehci0",
> + "bus_ehci0", "bus_otg_ohci0",
> + "bus_ve", "bus_lcd0",
> + "bus_lcd1", "bus_deint",
> + "bus_csi", "bus_hdmi",
> + "bus_de", "bus_gpu",
> + "bus_msgbox", "bus_spinlock",
> + "bus_dbg";
> + };
> + ahb2_parent {
> + clocks = <&ahb2>;
> + clock-indices = <17>, <29>;
> + clock-output-names = "bus_gmac", "bus_ohci0";
> + };
> + apb1_parent {
> + clocks = <&apb1>;
> + clock-indices = <64>, <65>,
> + <69>, <72>,
> + <76>, <77>,
> + <78>;
> + clock-output-names = "bus_codec", "bus_spdif",
> + "bus_pio", "bus_ths",
> + "bus_i2s0", "bus_i2s1",
> + "bus_i2s2";
> + };
> + abp2_parent {
> + clocks = <&apb2>;
> + clock-indices = <96>, <97>,
> + <98>, <101>,
> + <112>, <113>,
> + <114>, <115>,
> + <116>;
> + clock-output-names = "bus_i2c0", "bus_i2c1",
> + "bus_i2c2", "bus_scr",
> + "bus_uart0", "bus_uart1",
> + "bus_uart2", "bus_uart3",
> + "bus_uart4";
> + };
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
The A64 MMC clocks don't seem to be fully compatible to A10. The output
and sample phase control has been moved to the MMC module itself.
The dividers are the same, but the additional special "outputs" are gone.
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
Parents are PLL6(2x) and PLL8(2x) according to manual.
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> + };
> +
> + regulators {
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&bus_gates 8>,
> + <&mmc0_clk 0>,
Consequently, the MMC driver now has to control the output/sample phase
with registers 0x140-0x148 instead of
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
And there seems to be some new clock divider somewhere which I haven't
found in the manual yet. The clock measured at the CLK pin is always
half the expected rate (even with 24MHz as MMC clock parent, so no
PLL6*2 problem).
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 8>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&bus_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 9>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&bus_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 10>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "allwinner,a64-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&bus_gates 69>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart0_pins_a: uart0@0 {
> + allwinner,pins = "PB8", "PB9";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart0_pins_b: uart0@1 {
> + allwinner,pins = "PF2", "PF3";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart1_pins: uart1@0 {
> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart2_pins: uart2@0 {
> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> + allwinner,function = "uart2";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_a: uart3@0 {
> + allwinner,pins = "PD0", "PD1";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_b: uart3@1 {
> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart4_pins: uart4@0 {
> + allwinner,pins = "PD2", "PD3", "PD4", "PD5";
> + allwinner,function = "uart4";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc0_pins: mmc0@0 {
> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc0_default_cd_pin: mmc0_cd_pin@0 {
> + allwinner,pins = "PF6";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> + };
> +
> + mmc1_pins: mmc1@0 {
> + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
> + "PG4", "PG5";
> + allwinner,function = "mmc1";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc2_pins: mmc2@0 {
> + allwinner,pins = "PC1", "PC5", "PC6", "PC8",
> + "PC9", "PC10";
> + allwinner,function = "mmc2";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> +
> + ahb_rst: reset@01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-ahb1-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset@01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset@01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + uart0: serial@01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 112>;
> + resets = <&apb2_rst 16>;
> + reset-names = "apb2";
Do we need reset-names here (and below)?
> + status = "disabled";
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 113>;
> + resets = <&apb2_rst 17>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 114>;
> + resets = <&apb2_rst 18>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart3: serial@01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 115>;
> + resets = <&apb2_rst 19>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + uart4: serial@01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&bus_gates 116>;
> + resets = <&apb2_rst 20>;
> + reset-names = "apb2";
> + status = "disabled";
> + };
> +
> + rtc: rtc@01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gic: interrupt-controller@{
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> +
> + reg = <0x01C81000 0x1000>,
> + <0x01C82000 0x2000>,
> + <0x01C84000 0x2000>,
> + <0x01C86000 0x2000>;
Maybe lowercase hex here too.
> + interrupts = <GIC_PPI 9
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +};
>
Regards,
Jens
[toc] | [prev] | [next] | [standalone]
| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-02 17:50 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXMjn-5NR-7@gated-at.bofh.it> |
| In reply to | #1324256 |
Hi Jens,
thanks for having such an elaborate look!
On 02/02/16 16:24, Jens Kuske wrote:
> Hi,
>
> On 01/02/16 18:39, Andre Przywara wrote:
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
>> 3 files changed, 585 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>> allwinner,sun8i-a83t
>> allwinner,sun8i-h3
>> allwinner,sun9i-a80
>> + allwinner,a64
>>
>> For Allwinner SoCs without any specific needs the generic fallback value of:
>> allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>
>> Required properties for all clocks:
>> - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + compatible = "allwinner,a64", "allwinner,sunxi";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <1>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <2>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <3>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-0.2", "arm,psci";
>> + method = "smc";
>> + cpu_suspend = <0xc4000001>;
>> + cpu_off = <0x84000002>;
>> + cpu_on = <0xc4000003>;
>> + };
>> +
>> + memory {
>> + device_type = "memory";
>> + reg = <0x40000000 0>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: osc32k_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6", "pll6x2";
>> + };
>> +
>> + pll6d2: pll6d2_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-factor-clock";
>> + clock-div = <2>;
>> + clock-mult = <1>;
>> + clocks = <&pll6 0>;
>> + clock-output-names = "pll6d2";
>> + };
>> +
>> + /* dummy clock until pll6 can be reused */
>> + pll8: pll8_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <1>;
>> + clock-output-names = "pll8";
>> + };
Since I have you (as the original author ;-) in the loop: What was again
the reason for this dummy clock? Can't it be modelled with the existing
clock drivers in Linux?
>> +
>> + cpu: cpu_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + critical-clocks = <0>;
>> + };
>> +
>> + axi: axi_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1: ahb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb2: ahb2_clk@01c2005c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-h3-ahb2-clk";
>> + reg = <0x01c2005c 0x4>;
>> + clocks = <&ahb1>, <&pll6d2>;
>> + clock-output-names = "ahb2";
>> + };
>> +
>> + apb1: apb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb2: apb2_clk@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + bus_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,a64-bus-gates-clk",
>> + "allwinner,sunxi-multi-bus-gates-clk";
>> + reg = <0x01c20060 0x14>;
>> + ahb1_parent {
>> + clocks = <&ahb1>;
>> + clock-indices = <1>, <5>,
>> + <6>, <8>,
>> + <9>, <10>,
>> + <13>, <14>,
>> + <18>, <19>,
>> + <20>, <21>,
>> + <23>, <24>,
>> + <25>, <28>,
>> + <32>, <35>,
>> + <36>, <37>,
>> + <40>, <43>,
>> + <44>, <52>,
>> + <53>, <54>,
>> + <135>;
>> + clock-output-names = "bus_mipidsi", "bus_ce",
>> + "bus_dma", "bus_mmc0",
>> + "bus_mmc1", "bus_mmc2",
>> + "bus_nand", "bus_sdram",
>> + "bus_ts", "bus_hstimer",
>> + "bus_spi0", "bus_spi1",
>> + "bus_otg", "bus_otg_ehci0",
>> + "bus_ehci0", "bus_otg_ohci0",
>> + "bus_ve", "bus_lcd0",
>> + "bus_lcd1", "bus_deint",
>> + "bus_csi", "bus_hdmi",
>> + "bus_de", "bus_gpu",
>> + "bus_msgbox", "bus_spinlock",
>> + "bus_dbg";
>> + };
>> + ahb2_parent {
>> + clocks = <&ahb2>;
>> + clock-indices = <17>, <29>;
>> + clock-output-names = "bus_gmac", "bus_ohci0";
>> + };
>> + apb1_parent {
>> + clocks = <&apb1>;
>> + clock-indices = <64>, <65>,
>> + <69>, <72>,
>> + <76>, <77>,
>> + <78>;
>> + clock-output-names = "bus_codec", "bus_spdif",
>> + "bus_pio", "bus_ths",
>> + "bus_i2s0", "bus_i2s1",
>> + "bus_i2s2";
>> + };
>> + abp2_parent {
>> + clocks = <&apb2>;
>> + clock-indices = <96>, <97>,
>> + <98>, <101>,
>> + <112>, <113>,
>> + <114>, <115>,
>> + <116>;
>> + clock-output-names = "bus_i2c0", "bus_i2c1",
>> + "bus_i2c2", "bus_scr",
>> + "bus_uart0", "bus_uart1",
>> + "bus_uart2", "bus_uart3",
>> + "bus_uart4";
>> + };
>> + };
>> +
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>
> The A64 MMC clocks don't seem to be fully compatible to A10. The output
> and sample phase control has been moved to the MMC module itself.
> The dividers are the same, but the additional special "outputs" are gone.
So from comparing the H3 and the A64 datasheet I see that this is one of
the rare deviations of the A64 from the H3?
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>
> Parents are PLL6(2x) and PLL8(2x) according to manual.
Indeed, thanks for pointing this out! So do we need a proper pll8 clock?
>
>> + clock-output-names = "mmc0",
>> + "mmc0_output",
>> + "mmc0_sample";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc1",
>> + "mmc1_output",
>> + "mmc1_sample";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc2",
>> + "mmc2_output",
>> + "mmc2_sample";
>> + };
>> + };
>> +
>> + regulators {
>> + reg_vcc3v3: vcc3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&bus_gates 8>,
>> + <&mmc0_clk 0>,
>
> Consequently, the MMC driver now has to control the output/sample phase
> with registers 0x140-0x148 instead of
>> + <&mmc0_clk 1>,
>> + <&mmc0_clk 2>;
OK, good point. I was just briefly browsing over the register
descriptions and missed that.
So it looks like I need to change the driver. Interestingly it seems to
work anyways ...
> And there seems to be some new clock divider somewhere which I haven't
> found in the manual yet. The clock measured at the CLK pin is always
> half the expected rate (even with 24MHz as MMC clock parent, so no
> PLL6*2 problem).
Mmh, I heard about that mysterious clock doubling / halving already. Was
that actually causing any issues?
>
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&bus_gates 9>,
>> + <&mmc1_clk 0>,
>> + <&mmc1_clk 1>,
>> + <&mmc1_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&bus_gates 10>,
>> + <&mmc2_clk 0>,
>> + <&mmc2_clk 1>,
>> + <&mmc2_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,a64-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bus_gates 69>;
>> + gpio-controller;
>> + #gpio-cells = <3>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PB8", "PB9";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart0_pins_b: uart0@1 {
>> + allwinner,pins = "PF2", "PF3";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart1_pins: uart1@0 {
>> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> + allwinner,function = "uart1";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart2_pins: uart2@0 {
>> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> + allwinner,function = "uart2";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_a: uart3@0 {
>> + allwinner,pins = "PD0", "PD1";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_b: uart3@1 {
>> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart4_pins: uart4@0 {
>> + allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>> + allwinner,function = "uart4";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc0_pins: mmc0@0 {
>> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>> + "PF4", "PF5";
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc0_default_cd_pin: mmc0_cd_pin@0 {
>> + allwinner,pins = "PF6";
>> + allwinner,function = "gpio_in";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>> + };
>> +
>> + mmc1_pins: mmc1@0 {
>> + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>> + "PG4", "PG5";
>> + allwinner,function = "mmc1";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc2_pins: mmc2@0 {
>> + allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>> + "PC9", "PC10";
>> + allwinner,function = "mmc2";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> + };
>> +
>> + ahb_rst: reset@01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset@01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset@01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 112>;
>> + resets = <&apb2_rst 16>;
>> + reset-names = "apb2";
>
> Do we need reset-names here (and below)?
Probably not, in fact I was wondering about that already. Actually I
just copied them from some other DT ;-)
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 113>;
>> + resets = <&apb2_rst 17>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 114>;
>> + resets = <&apb2_rst 18>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 115>;
>> + resets = <&apb2_rst 19>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&bus_gates 116>;
>> + resets = <&apb2_rst 20>;
>> + reset-names = "apb2";
>> + status = "disabled";
>> + };
>> +
>> + rtc: rtc@01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>> + gic: interrupt-controller@{
>> + compatible = "arm,gic-400";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> +
>> + reg = <0x01C81000 0x1000>,
>> + <0x01C82000 0x2000>,
>> + <0x01C84000 0x2000>,
>> + <0x01C86000 0x2000>;
>
> Maybe lowercase hex here too.
Yes.
Thanks for actually going through this!
Cheers,
Andre.
>> + interrupts = <GIC_PPI 9
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +};
>>
>
> Regards,
> Jens
>
[toc] | [prev] | [next] | [standalone]
| From | Jens Kuske <jenskuske@gmail.com> |
|---|---|
| Date | 2016-02-02 18:50 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qXNfs-6ut-5@gated-at.bofh.it> |
| In reply to | #1324266 |
Hi,
On 02/02/16 17:46, Andre Przywara wrote:
> Hi Jens,
>
> thanks for having such an elaborate look!
>
> On 02/02/16 16:24, Jens Kuske wrote:
>> Hi,
>>
>> On 01/02/16 18:39, Andre Przywara wrote:
[..]
>>> +
>>> + /* dummy clock until pll6 can be reused */
>>> + pll8: pll8_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <1>;
>>> + clock-output-names = "pll8";
>>> + };
>
> Since I have you (as the original author ;-) in the loop: What was again
> the reason for this dummy clock? Can't it be modelled with the existing
> clock drivers in Linux?
PLL6 driver had the output name "pll6" hardcoded, so we couldn't reuse
it for "pll8". Maxime has reworked the pll6 code in the meantime, now
pll8 can use compatible = "allwinner,sun6i-a31-pll6-clk" too:
http://www.spinics.net/lists/linux-clk/msg06242.html
>
>>> +
>>> + cpu: cpu_clk@01c20050 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>>> + reg = <0x01c20050 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>>> + clock-output-names = "cpu";
>>> + critical-clocks = <0>;
>>> + };
>>> +
>>> + axi: axi_clk@01c20050 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-axi-clk";
>>> + reg = <0x01c20050 0x4>;
>>> + clocks = <&cpu>;
>>> + clock-output-names = "axi";
>>> + };
>>> +
>>> + ahb1: ahb1_clk@01c20054 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>>> + reg = <0x01c20054 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>>> + clock-output-names = "ahb1";
>>> + };
>>> +
>>> + ahb2: ahb2_clk@01c2005c {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun8i-h3-ahb2-clk";
>>> + reg = <0x01c2005c 0x4>;
>>> + clocks = <&ahb1>, <&pll6d2>;
>>> + clock-output-names = "ahb2";
>>> + };
>>> +
>>> + apb1: apb1_clk@01c20054 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>>> + reg = <0x01c20054 0x4>;
>>> + clocks = <&ahb1>;
>>> + clock-output-names = "apb1";
>>> + };
>>> +
>>> + apb2: apb2_clk@01c20058 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>>> + reg = <0x01c20058 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>>> + clock-output-names = "apb2";
>>> + };
>>> +
>>> + bus_gates: clk@01c20060 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,a64-bus-gates-clk",
>>> + "allwinner,sunxi-multi-bus-gates-clk";
>>> + reg = <0x01c20060 0x14>;
>>> + ahb1_parent {
>>> + clocks = <&ahb1>;
>>> + clock-indices = <1>, <5>,
>>> + <6>, <8>,
>>> + <9>, <10>,
>>> + <13>, <14>,
>>> + <18>, <19>,
>>> + <20>, <21>,
>>> + <23>, <24>,
>>> + <25>, <28>,
>>> + <32>, <35>,
>>> + <36>, <37>,
>>> + <40>, <43>,
>>> + <44>, <52>,
>>> + <53>, <54>,
>>> + <135>;
>>> + clock-output-names = "bus_mipidsi", "bus_ce",
>>> + "bus_dma", "bus_mmc0",
>>> + "bus_mmc1", "bus_mmc2",
>>> + "bus_nand", "bus_sdram",
>>> + "bus_ts", "bus_hstimer",
>>> + "bus_spi0", "bus_spi1",
>>> + "bus_otg", "bus_otg_ehci0",
>>> + "bus_ehci0", "bus_otg_ohci0",
>>> + "bus_ve", "bus_lcd0",
>>> + "bus_lcd1", "bus_deint",
>>> + "bus_csi", "bus_hdmi",
>>> + "bus_de", "bus_gpu",
>>> + "bus_msgbox", "bus_spinlock",
>>> + "bus_dbg";
>>> + };
>>> + ahb2_parent {
>>> + clocks = <&ahb2>;
>>> + clock-indices = <17>, <29>;
>>> + clock-output-names = "bus_gmac", "bus_ohci0";
>>> + };
>>> + apb1_parent {
>>> + clocks = <&apb1>;
>>> + clock-indices = <64>, <65>,
>>> + <69>, <72>,
>>> + <76>, <77>,
>>> + <78>;
>>> + clock-output-names = "bus_codec", "bus_spdif",
>>> + "bus_pio", "bus_ths",
>>> + "bus_i2s0", "bus_i2s1",
>>> + "bus_i2s2";
>>> + };
>>> + abp2_parent {
>>> + clocks = <&apb2>;
>>> + clock-indices = <96>, <97>,
>>> + <98>, <101>,
>>> + <112>, <113>,
>>> + <114>, <115>,
>>> + <116>;
>>> + clock-output-names = "bus_i2c0", "bus_i2c1",
>>> + "bus_i2c2", "bus_scr",
>>> + "bus_uart0", "bus_uart1",
>>> + "bus_uart2", "bus_uart3",
>>> + "bus_uart4";
>>> + };
>>> + };
>>> +
>>> + mmc0_clk: clk@01c20088 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>
>> The A64 MMC clocks don't seem to be fully compatible to A10. The output
>> and sample phase control has been moved to the MMC module itself.
>> The dividers are the same, but the additional special "outputs" are gone.
>
> So from comparing the H3 and the A64 datasheet I see that this is one of
> the rare deviations of the A64 from the H3?
Yeah, looks like this is new in A64, probably because it supports even
higher card speeds now.
>
>>> + reg = <0x01c20088 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>
>> Parents are PLL6(2x) and PLL8(2x) according to manual.
>
> Indeed, thanks for pointing this out! So do we need a proper pll8 clock?
The dummy would still work, but it is easy to add a real pll8 now with
Maximes work.
>
>>
>>> + clock-output-names = "mmc0",
>>> + "mmc0_output",
>>> + "mmc0_sample";
>>> + };
>>> +
>>> + mmc1_clk: clk@01c2008c {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>> + reg = <0x01c2008c 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> + clock-output-names = "mmc1",
>>> + "mmc1_output",
>>> + "mmc1_sample";
>>> + };
>>> +
>>> + mmc2_clk: clk@01c20090 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>> + reg = <0x01c20090 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> + clock-output-names = "mmc2",
>>> + "mmc2_output",
>>> + "mmc2_sample";
>>> + };
>>> + };
>>> +
>>> + regulators {
>>> + reg_vcc3v3: vcc3v3 {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "vcc3v3";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + };
>>> + };
>>> +
>>> + soc {
>>> + compatible = "simple-bus";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> +
>>> + mmc0: mmc@01c0f000 {
>>> + compatible = "allwinner,sun5i-a13-mmc";
>>> + reg = <0x01c0f000 0x1000>;
>>> + clocks = <&bus_gates 8>,
>>> + <&mmc0_clk 0>,
>>
>> Consequently, the MMC driver now has to control the output/sample phase
>> with registers 0x140-0x148 instead of
>>> + <&mmc0_clk 1>,
>>> + <&mmc0_clk 2>;
>
> OK, good point. I was just briefly browsing over the register
> descriptions and missed that.
> So it looks like I need to change the driver. Interestingly it seems to
> work anyways ...
I don't know, maybe it has sane defaults or is only relevant at higher
clock speeds. Or Allwinners u-boot already set it.
>
>> And there seems to be some new clock divider somewhere which I haven't
>> found in the manual yet. The clock measured at the CLK pin is always
>> half the expected rate (even with 24MHz as MMC clock parent, so no
>> PLL6*2 problem).
>
> Mmh, I heard about that mysterious clock doubling / halving already. Was
> that actually causing any issues?
Since it uses PLL6 * 2 now and seems to divide that by 2 somewhere
nothing has changed in the end. One could argue that pll6 * 2 is wrong,
but by testing with osc24MHz parent (in u-boot) it can be seen that the
clockrate is only half of what is expected.
Disclaimer: I don't know much about mmc, so maybe I've missed something
obvious. I only did some frequency measurements on H3 vs A64 hardware
when Siarhei asked about that in irc and now I wonder about the results.
Jens
[toc] | [prev] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-02-05 10:00 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qYKpc-6kL-17@gated-at.bofh.it> |
| In reply to | #1324266 |
On Wed, Feb 3, 2016 at 12:46 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi Jens,
>
> thanks for having such an elaborate look!
>
> On 02/02/16 16:24, Jens Kuske wrote:
>> Hi,
>>
>> On 01/02/16 18:39, Andre Przywara wrote:
>>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>>> and the typical tablet / TV box peripherals.
>>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>>> the peripherals and the memory map.
>>> Although the cores are proper 64-bit ones, the whole SoC is actually
>>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>>> address and size cells. This has the nice feature of us being able to
>>> reuse the DT for 32-bit kernels as well.
>>> This .dtsi lists the hardware that we support so far.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
>>> 3 files changed, 585 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>>> index 980e065..4a83853 100644
>>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>>> allwinner,sun8i-a83t
>>> allwinner,sun8i-h3
>>> allwinner,sun9i-a80
>>> + allwinner,a64
>>>
>>> For Allwinner SoCs without any specific needs the generic fallback value of:
>>> allwinner,sunxi
>>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>>> index e59f57b..44b0c6c 100644
>>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>>> @@ -77,6 +77,7 @@ Required properties:
>>> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>>> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>>> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>>> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>>
>>> Required properties for all clocks:
>>> - reg : shall be the control register address for the clock.
>>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>>> new file mode 100644
>>> index 0000000..8dce10f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>>> @@ -0,0 +1,583 @@
>>> +/*
>>> + * Copyright (C) 2016 ARM Ltd.
>>> + * based on the Allwinner H3 dtsi:
>>> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + * a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + * b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>>> +
>>> +/ {
>>> + compatible = "allwinner,a64", "allwinner,sunxi";
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + aliases {
>>> + serial0 = &uart0;
>>> + serial1 = &uart1;
>>> + serial2 = &uart2;
>>> + serial3 = &uart3;
>>> + serial4 = &uart4;
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu@0 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
>>> + device_type = "cpu";
>>> + reg = <0>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu@1 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
>>> + device_type = "cpu";
>>> + reg = <1>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu@2 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
>>> + device_type = "cpu";
>>> + reg = <2>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu@3 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
>>> + device_type = "cpu";
>>> + reg = <3>;
>>> + enable-method = "psci";
>>> + };
>>> + };
>>> +
>>> + psci {
>>> + compatible = "arm,psci-0.2", "arm,psci";
>>> + method = "smc";
>>> + cpu_suspend = <0xc4000001>;
>>> + cpu_off = <0x84000002>;
>>> + cpu_on = <0xc4000003>;
>>> + };
>>> +
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <0x40000000 0>;
>>> + };
>>> +
>>> + timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupts = <GIC_PPI 13
>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> + <GIC_PPI 14
>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> + <GIC_PPI 11
>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> + <GIC_PPI 10
>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> + };
>>> +
>>> + clocks {
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> +
>>> + osc24M: osc24M_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <24000000>;
>>> + clock-output-names = "osc24M";
>>> + };
>>> +
>>> + osc32k: osc32k_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <32768>;
>>> + clock-output-names = "osc32k";
>>> + };
>>> +
>>> + pll1: clk@01c20000 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>>> + reg = <0x01c20000 0x4>;
>>> + clocks = <&osc24M>;
>>> + clock-output-names = "pll1";
>>> + };
>>> +
>>> + pll6: clk@01c20028 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>>> + reg = <0x01c20028 0x4>;
>>> + clocks = <&osc24M>;
>>> + clock-output-names = "pll6", "pll6x2";
>>> + };
>>> +
>>> + pll6d2: pll6d2_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-factor-clock";
>>> + clock-div = <2>;
>>> + clock-mult = <1>;
>>> + clocks = <&pll6 0>;
>>> + clock-output-names = "pll6d2";
>>> + };
>>> +
>>> + /* dummy clock until pll6 can be reused */
>>> + pll8: pll8_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <1>;
>>> + clock-output-names = "pll8";
>>> + };
>
> Since I have you (as the original author ;-) in the loop: What was again
> the reason for this dummy clock? Can't it be modelled with the existing
> clock drivers in Linux?
The driver for "allwinner,sun6i-a31-pll6-clk" has it's name hard coded,
which means it's not reusable for other clocks. The placeholder is there
to provide a proper representation of the clock tree. It works because
nothing is clocked from pll8 by default.
>>> +
>>> + cpu: cpu_clk@01c20050 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>>> + reg = <0x01c20050 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>>> + clock-output-names = "cpu";
>>> + critical-clocks = <0>;
>>> + };
>>> +
>>> + axi: axi_clk@01c20050 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-axi-clk";
>>> + reg = <0x01c20050 0x4>;
>>> + clocks = <&cpu>;
>>> + clock-output-names = "axi";
>>> + };
>>> +
>>> + ahb1: ahb1_clk@01c20054 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>>> + reg = <0x01c20054 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>>> + clock-output-names = "ahb1";
>>> + };
>>> +
>>> + ahb2: ahb2_clk@01c2005c {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun8i-h3-ahb2-clk";
>>> + reg = <0x01c2005c 0x4>;
>>> + clocks = <&ahb1>, <&pll6d2>;
>>> + clock-output-names = "ahb2";
>>> + };
>>> +
>>> + apb1: apb1_clk@01c20054 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>>> + reg = <0x01c20054 0x4>;
>>> + clocks = <&ahb1>;
>>> + clock-output-names = "apb1";
>>> + };
>>> +
>>> + apb2: apb2_clk@01c20058 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>>> + reg = <0x01c20058 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>>> + clock-output-names = "apb2";
>>> + };
>>> +
>>> + bus_gates: clk@01c20060 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,a64-bus-gates-clk",
>>> + "allwinner,sunxi-multi-bus-gates-clk";
>>> + reg = <0x01c20060 0x14>;
>>> + ahb1_parent {
>>> + clocks = <&ahb1>;
>>> + clock-indices = <1>, <5>,
>>> + <6>, <8>,
>>> + <9>, <10>,
>>> + <13>, <14>,
>>> + <18>, <19>,
>>> + <20>, <21>,
>>> + <23>, <24>,
>>> + <25>, <28>,
>>> + <32>, <35>,
>>> + <36>, <37>,
>>> + <40>, <43>,
>>> + <44>, <52>,
>>> + <53>, <54>,
>>> + <135>;
>>> + clock-output-names = "bus_mipidsi", "bus_ce",
>>> + "bus_dma", "bus_mmc0",
>>> + "bus_mmc1", "bus_mmc2",
>>> + "bus_nand", "bus_sdram",
>>> + "bus_ts", "bus_hstimer",
>>> + "bus_spi0", "bus_spi1",
>>> + "bus_otg", "bus_otg_ehci0",
>>> + "bus_ehci0", "bus_otg_ohci0",
>>> + "bus_ve", "bus_lcd0",
>>> + "bus_lcd1", "bus_deint",
>>> + "bus_csi", "bus_hdmi",
>>> + "bus_de", "bus_gpu",
>>> + "bus_msgbox", "bus_spinlock",
>>> + "bus_dbg";
>>> + };
>>> + ahb2_parent {
>>> + clocks = <&ahb2>;
>>> + clock-indices = <17>, <29>;
>>> + clock-output-names = "bus_gmac", "bus_ohci0";
>>> + };
>>> + apb1_parent {
>>> + clocks = <&apb1>;
>>> + clock-indices = <64>, <65>,
>>> + <69>, <72>,
>>> + <76>, <77>,
>>> + <78>;
>>> + clock-output-names = "bus_codec", "bus_spdif",
>>> + "bus_pio", "bus_ths",
>>> + "bus_i2s0", "bus_i2s1",
>>> + "bus_i2s2";
>>> + };
>>> + abp2_parent {
>>> + clocks = <&apb2>;
>>> + clock-indices = <96>, <97>,
>>> + <98>, <101>,
>>> + <112>, <113>,
>>> + <114>, <115>,
>>> + <116>;
>>> + clock-output-names = "bus_i2c0", "bus_i2c1",
>>> + "bus_i2c2", "bus_scr",
>>> + "bus_uart0", "bus_uart1",
>>> + "bus_uart2", "bus_uart3",
>>> + "bus_uart4";
>>> + };
>>> + };
>>> +
>>> + mmc0_clk: clk@01c20088 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>
>> The A64 MMC clocks don't seem to be fully compatible to A10. The output
>> and sample phase control has been moved to the MMC module itself.
>> The dividers are the same, but the additional special "outputs" are gone.
>
> So from comparing the H3 and the A64 datasheet I see that this is one of
> the rare deviations of the A64 from the H3?
Without the extra phase delay clocks, this is now just a mod0 clock.
>>> + reg = <0x01c20088 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>
>> Parents are PLL6(2x) and PLL8(2x) according to manual.
>
> Indeed, thanks for pointing this out! So do we need a proper pll8 clock?
You could add a pll8x2 fixed-factor-clk for now, until Maxime's clk series
is worked out.
>
>>
>>> + clock-output-names = "mmc0",
>>> + "mmc0_output",
>>> + "mmc0_sample";
>>> + };
>>> +
>>> + mmc1_clk: clk@01c2008c {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>> + reg = <0x01c2008c 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> + clock-output-names = "mmc1",
>>> + "mmc1_output",
>>> + "mmc1_sample";
>>> + };
>>> +
>>> + mmc2_clk: clk@01c20090 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>>> + reg = <0x01c20090 0x4>;
>>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> + clock-output-names = "mmc2",
>>> + "mmc2_output",
>>> + "mmc2_sample";
>>> + };
>>> + };
>>> +
>>> + regulators {
>>> + reg_vcc3v3: vcc3v3 {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "vcc3v3";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + };
Why is this in the .dtsi?
>>> + };
>>> +
>>> + soc {
>>> + compatible = "simple-bus";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> +
>>> + mmc0: mmc@01c0f000 {
>>> + compatible = "allwinner,sun5i-a13-mmc";
>>> + reg = <0x01c0f000 0x1000>;
>>> + clocks = <&bus_gates 8>,
>>> + <&mmc0_clk 0>,
>>
>> Consequently, the MMC driver now has to control the output/sample phase
>> with registers 0x140-0x148 instead of
>>> + <&mmc0_clk 1>,
>>> + <&mmc0_clk 2>;
>
> OK, good point. I was just briefly browsing over the register
> descriptions and missed that.
> So it looks like I need to change the driver. Interestingly it seems to
> work anyways ...
The default delay values probably are good enough. Or they included routing
tolerances in the design notes. :)
You should still check Allwinner's kernel for new delay values though.
>> And there seems to be some new clock divider somewhere which I haven't
>> found in the manual yet. The clock measured at the CLK pin is always
>> half the expected rate (even with 24MHz as MMC clock parent, so no
>> PLL6*2 problem).
>
> Mmh, I heard about that mysterious clock doubling / halving already. Was
> that actually causing any issues?
On the A83T there was this "new timing mode" feature in the mmc clocks and
controller, which halved the card clock. I don't see any mention of it on
A64 though.
>>
>>> + clock-names = "ahb",
>>> + "mmc",
>>> + "output",
>>> + "sample";
>>> + resets = <&ahb_rst 8>;
>>> + reset-names = "ahb";
>>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + };
>>> +
>>> + mmc1: mmc@01c10000 {
>>> + compatible = "allwinner,sun5i-a13-mmc";
>>> + reg = <0x01c10000 0x1000>;
>>> + clocks = <&bus_gates 9>,
>>> + <&mmc1_clk 0>,
>>> + <&mmc1_clk 1>,
>>> + <&mmc1_clk 2>;
>>> + clock-names = "ahb",
>>> + "mmc",
>>> + "output",
>>> + "sample";
>>> + resets = <&ahb_rst 9>;
>>> + reset-names = "ahb";
>>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + };
>>> +
>>> + mmc2: mmc@01c11000 {
>>> + compatible = "allwinner,sun5i-a13-mmc";
>>> + reg = <0x01c11000 0x1000>;
>>> + clocks = <&bus_gates 10>,
>>> + <&mmc2_clk 0>,
>>> + <&mmc2_clk 1>,
>>> + <&mmc2_clk 2>;
>>> + clock-names = "ahb",
>>> + "mmc",
>>> + "output",
>>> + "sample";
>>> + resets = <&ahb_rst 10>;
>>> + reset-names = "ahb";
>>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>>> + status = "disabled";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + };
>>> +
>>> + pio: pinctrl@01c20800 {
>>> + compatible = "allwinner,a64-pinctrl";
>>> + reg = <0x01c20800 0x400>;
>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&bus_gates 69>;
>>> + gpio-controller;
>>> + #gpio-cells = <3>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <2>;
>>> +
>>> + uart0_pins_a: uart0@0 {
>>> + allwinner,pins = "PB8", "PB9";
>>> + allwinner,function = "uart0";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart0_pins_b: uart0@1 {
>>> + allwinner,pins = "PF2", "PF3";
>>> + allwinner,function = "uart0";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart1_pins: uart1@0 {
>>> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>>> + allwinner,function = "uart1";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart2_pins: uart2@0 {
>>> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>>> + allwinner,function = "uart2";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart3_pins_a: uart3@0 {
>>> + allwinner,pins = "PD0", "PD1";
>>> + allwinner,function = "uart3";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart3_pins_b: uart3@1 {
>>> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>>> + allwinner,function = "uart3";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + uart4_pins: uart4@0 {
>>> + allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>>> + allwinner,function = "uart4";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
We normally don't add these until someone uses them.
And one could choose to use 2 pins instead of 4. :|
>>> +
>>> + mmc0_pins: mmc0@0 {
>>> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>>> + "PF4", "PF5";
>>> + allwinner,function = "mmc0";
>>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + mmc0_default_cd_pin: mmc0_cd_pin@0 {
>>> + allwinner,pins = "PF6";
>>> + allwinner,function = "gpio_in";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>>> + };
>>> +
>>> + mmc1_pins: mmc1@0 {
>>> + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>>> + "PG4", "PG5";
>>> + allwinner,function = "mmc1";
>>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + mmc2_pins: mmc2@0 {
>>> + allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>>> + "PC9", "PC10";
>>> + allwinner,function = "mmc2";
>>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> + };
>>> +
>>> + ahb_rst: reset@01c202c0 {
>>> + #reset-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-ahb1-reset";
>>> + reg = <0x01c202c0 0xc>;
>>> + };
>>> +
>>> + apb1_rst: reset@01c202d0 {
>>> + #reset-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-clock-reset";
>>> + reg = <0x01c202d0 0x4>;
>>> + };
>>> +
>>> + apb2_rst: reset@01c202d8 {
>>> + #reset-cells = <1>;
>>> + compatible = "allwinner,sun6i-a31-clock-reset";
>>> + reg = <0x01c202d8 0x4>;
>>> + };
>>> +
>>> + uart0: serial@01c28000 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c28000 0x400>;
>>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&bus_gates 112>;
>>> + resets = <&apb2_rst 16>;
>>> + reset-names = "apb2";
>>
>> Do we need reset-names here (and below)?
>
> Probably not, in fact I was wondering about that already. Actually I
> just copied them from some other DT ;-)
Nope. Not needed.
Regards
ChenYu
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart1: serial@01c28400 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c28400 0x400>;
>>> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&bus_gates 113>;
>>> + resets = <&apb2_rst 17>;
>>> + reset-names = "apb2";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart2: serial@01c28800 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c28800 0x400>;
>>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&bus_gates 114>;
>>> + resets = <&apb2_rst 18>;
>>> + reset-names = "apb2";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart3: serial@01c28c00 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c28c00 0x400>;
>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&bus_gates 115>;
>>> + resets = <&apb2_rst 19>;
>>> + reset-names = "apb2";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart4: serial@01c29000 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c29000 0x400>;
>>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&bus_gates 116>;
>>> + resets = <&apb2_rst 20>;
>>> + reset-names = "apb2";
>>> + status = "disabled";
>>> + };
>>> +
>>> + rtc: rtc@01f00000 {
>>> + compatible = "allwinner,sun6i-a31-rtc";
>>> + reg = <0x01f00000 0x54>;
>>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>>> + };
>>> + };
>>> +
>>> + gic: interrupt-controller@{
>>> + compatible = "arm,gic-400";
>>> + interrupt-controller;
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <0>;
>>> +
>>> + reg = <0x01C81000 0x1000>,
>>> + <0x01C82000 0x2000>,
>>> + <0x01C84000 0x2000>,
>>> + <0x01C86000 0x2000>;
>>
>> Maybe lowercase hex here too.
>
> Yes.
>
>
> Thanks for actually going through this!
>
> Cheers,
> Andre.
>
>>> + interrupts = <GIC_PPI 9
>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> + };
>>> +};
>>>
>>
>> Regards,
>> Jens
>>
>
> --
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[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-02-05 10:00 +0100 |
| Subject | Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qYKpc-6kL-9@gated-at.bofh.it> |
| In reply to | #1323359 |
[Multipart message — attachments visible in raw view] — view raw
Hi Andre,
On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
> 3 files changed, 585 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> allwinner,sun9i-a80
> + allwinner,a64
>
> For Allwinner SoCs without any specific needs the generic fallback value of:
> allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>
> Required properties for all clocks:
> - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + compatible = "allwinner,a64", "allwinner,sunxi";
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + };
The aliases are usually per-board, as it will vary depending on what
the board enables.
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a53", "arm,armv8";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2", "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + };
I thought that the function IDs were not needed anymore with PSCI 0.2?
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0>;
> + };
I'm guessing u-boot fixes that, can we just remove it entirely?
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6", "pll6x2";
The output names have changed, and it doesn't take an argument
anymore.
> + };
> +
> + pll6d2: pll6d2_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-div = <2>;
> + clock-mult = <1>;
> + clocks = <&pll6 0>;
> + clock-output-names = "pll6d2";
> + };
> +
> + /* dummy clock until pll6 can be reused */
> + pll8: pll8_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <1>;
> + clock-output-names = "pll8";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + critical-clocks = <0>;
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1: ahb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> + clock-output-names = "ahb1";
> + };
> +
> + ahb2: ahb2_clk@01c2005c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-h3-ahb2-clk";
> + reg = <0x01c2005c 0x4>;
> + clocks = <&ahb1>, <&pll6d2>;
> + clock-output-names = "ahb2";
> + };
> +
> + apb1: apb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + apb2: apb2_clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> + clock-output-names = "apb2";
> + };
> +
> + bus_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,a64-bus-gates-clk",
> + "allwinner,sunxi-multi-bus-gates-clk";
> + reg = <0x01c20060 0x14>;
> + ahb1_parent {
> + clocks = <&ahb1>;
> + clock-indices = <1>, <5>,
> + <6>, <8>,
> + <9>, <10>,
> + <13>, <14>,
> + <18>, <19>,
> + <20>, <21>,
> + <23>, <24>,
> + <25>, <28>,
> + <32>, <35>,
> + <36>, <37>,
> + <40>, <43>,
> + <44>, <52>,
> + <53>, <54>,
> + <135>;
> + clock-output-names = "bus_mipidsi", "bus_ce",
> + "bus_dma", "bus_mmc0",
> + "bus_mmc1", "bus_mmc2",
> + "bus_nand", "bus_sdram",
> + "bus_ts", "bus_hstimer",
> + "bus_spi0", "bus_spi1",
> + "bus_otg", "bus_otg_ehci0",
> + "bus_ehci0", "bus_otg_ohci0",
> + "bus_ve", "bus_lcd0",
> + "bus_lcd1", "bus_deint",
> + "bus_csi", "bus_hdmi",
> + "bus_de", "bus_gpu",
> + "bus_msgbox", "bus_spinlock",
> + "bus_dbg";
> + };
> + ahb2_parent {
> + clocks = <&ahb2>;
> + clock-indices = <17>, <29>;
> + clock-output-names = "bus_gmac", "bus_ohci0";
> + };
> + apb1_parent {
> + clocks = <&apb1>;
> + clock-indices = <64>, <65>,
> + <69>, <72>,
> + <76>, <77>,
> + <78>;
> + clock-output-names = "bus_codec", "bus_spdif",
> + "bus_pio", "bus_ths",
> + "bus_i2s0", "bus_i2s1",
> + "bus_i2s2";
> + };
> + abp2_parent {
> + clocks = <&apb2>;
> + clock-indices = <96>, <97>,
> + <98>, <101>,
> + <112>, <113>,
> + <114>, <115>,
> + <116>;
> + clock-output-names = "bus_i2c0", "bus_i2c1",
> + "bus_i2c2", "bus_scr",
> + "bus_uart0", "bus_uart1",
> + "bus_uart2", "bus_uart3",
> + "bus_uart4";
> + };
> + };
As I've already told you I'm not really fond of this one, for two main
topics.
The first one is about the DT bindings itself which is quite exotic,
especially the fact that you define clocks using clocks, clock-indices
and clock-output-names in nodes that are not the one referred to by
consumer, which goes against both the clock bindings documentation and
the usage.
The second one is pretty much the same one than for the discussion we
had about pinctrl. There is SoCs where we simply don't have that
information, or at least are not really sure about what to put where
(namely, the A83t). In such a case, we would knowingly put invalid
information in the DT, which is already quite bad in itself. The worst
part is, when we will identify issues and fix them (hopefully), there
will be no way to fix the current DT users. And it just became a pain
to maintain in the long run.
On the opposite side, having something like the H3 bus gates driver
address all these concerns and is easily extensible, which is why we
ended up merging it.
So please use it.
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> + };
> +
> + regulators {
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&bus_gates 8>,
> + <&mmc0_clk 0>,
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 8>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&bus_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 9>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&bus_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb_rst 10>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "allwinner,a64-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&bus_gates 69>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart0_pins_a: uart0@0 {
> + allwinner,pins = "PB8", "PB9";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart0_pins_b: uart0@1 {
> + allwinner,pins = "PF2", "PF3";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart1_pins: uart1@0 {
> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart2_pins: uart2@0 {
> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> + allwinner,function = "uart2";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_a: uart3@0 {
> + allwinner,pins = "PD0", "PD1";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart3_pins_b: uart3@1 {
> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> + allwinner,function = "uart3";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
You have several options for all these controllers, which is why we
have the _a or _b suffices.
Usually, the uart pins we had were only using RX and TX, I guess you
could add a separate node for the RTS / CTS pins if some board want to
use them.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-08 10:50 +0100 |
| Subject | Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi |
| Message-ID | <qZQCe-3pM-9@gated-at.bofh.it> |
| In reply to | #1327539 |
Hi,
On 05/02/16 08:50, Maxime Ripard wrote:
> Hi Andre,
>
> On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> arch/arm64/boot/dts/allwinner/a64.dtsi | 583 ++++++++++++++++++++++
>> 3 files changed, 585 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>> allwinner,sun8i-a83t
>> allwinner,sun8i-h3
>> allwinner,sun9i-a80
>> + allwinner,a64
>>
>> For Allwinner SoCs without any specific needs the generic fallback value of:
>> allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>> "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>> "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>> "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> + "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>
>> Required properties for all clocks:
>> - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + compatible = "allwinner,a64", "allwinner,sunxi";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &uart2;
>> + serial3 = &uart3;
>> + serial4 = &uart4;
>> + };
>
> The aliases are usually per-board, as it will vary depending on what
> the board enables.
Sure.
>
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <1>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <2>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <3>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-0.2", "arm,psci";
>> + method = "smc";
>> + cpu_suspend = <0xc4000001>;
>> + cpu_off = <0x84000002>;
>> + cpu_on = <0xc4000003>;
>> + };
>
> I thought that the function IDs were not needed anymore with PSCI 0.2?
The idea here was to provide compatibility with older OSes not
supporting PSCI 0.2, those would match on the "arm,psci" compatible
string and require the numbers (see bindings/arm/psci.txt).
Thinking again I realise that we require PSCI 0.2 for having reset and
shutdown, so I will drop this and just provide the 0.2 compatible string.
>> + memory {
>> + device_type = "memory";
>> + reg = <0x40000000 0>;
>> + };
>
> I'm guessing u-boot fixes that, can we just remove it entirely?
Don't know, can we? I found it nice to have it in here to give people at
the least the idea of where DRAM starts and also making it clear that a
bootloader is expected to patch this (and having a node already makes
patching easier).
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: osc32k_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6", "pll6x2";
>
> The output names have changed, and it doesn't take an argument
> anymore.
Would be happy to adapt to this, but we should sort this approach out
(see the other mail).
>> + };
>> +
>> + pll6d2: pll6d2_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-factor-clock";
>> + clock-div = <2>;
>> + clock-mult = <1>;
>> + clocks = <&pll6 0>;
>> + clock-output-names = "pll6d2";
>> + };
>> +
>> + /* dummy clock until pll6 can be reused */
>> + pll8: pll8_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <1>;
>> + clock-output-names = "pll8";
>> + };
>> +
>> + cpu: cpu_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + critical-clocks = <0>;
>> + };
>> +
>> + axi: axi_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1: ahb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + ahb2: ahb2_clk@01c2005c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-h3-ahb2-clk";
>> + reg = <0x01c2005c 0x4>;
>> + clocks = <&ahb1>, <&pll6d2>;
>> + clock-output-names = "ahb2";
>> + };
>> +
>> + apb1: apb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + apb2: apb2_clk@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + bus_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,a64-bus-gates-clk",
>> + "allwinner,sunxi-multi-bus-gates-clk";
>> + reg = <0x01c20060 0x14>;
>> + ahb1_parent {
>> + clocks = <&ahb1>;
>> + clock-indices = <1>, <5>,
>> + <6>, <8>,
>> + <9>, <10>,
>> + <13>, <14>,
>> + <18>, <19>,
>> + <20>, <21>,
>> + <23>, <24>,
>> + <25>, <28>,
>> + <32>, <35>,
>> + <36>, <37>,
>> + <40>, <43>,
>> + <44>, <52>,
>> + <53>, <54>,
>> + <135>;
>> + clock-output-names = "bus_mipidsi", "bus_ce",
>> + "bus_dma", "bus_mmc0",
>> + "bus_mmc1", "bus_mmc2",
>> + "bus_nand", "bus_sdram",
>> + "bus_ts", "bus_hstimer",
>> + "bus_spi0", "bus_spi1",
>> + "bus_otg", "bus_otg_ehci0",
>> + "bus_ehci0", "bus_otg_ohci0",
>> + "bus_ve", "bus_lcd0",
>> + "bus_lcd1", "bus_deint",
>> + "bus_csi", "bus_hdmi",
>> + "bus_de", "bus_gpu",
>> + "bus_msgbox", "bus_spinlock",
>> + "bus_dbg";
>> + };
>> + ahb2_parent {
>> + clocks = <&ahb2>;
>> + clock-indices = <17>, <29>;
>> + clock-output-names = "bus_gmac", "bus_ohci0";
>> + };
>> + apb1_parent {
>> + clocks = <&apb1>;
>> + clock-indices = <64>, <65>,
>> + <69>, <72>,
>> + <76>, <77>,
>> + <78>;
>> + clock-output-names = "bus_codec", "bus_spdif",
>> + "bus_pio", "bus_ths",
>> + "bus_i2s0", "bus_i2s1",
>> + "bus_i2s2";
>> + };
>> + abp2_parent {
>> + clocks = <&apb2>;
>> + clock-indices = <96>, <97>,
>> + <98>, <101>,
>> + <112>, <113>,
>> + <114>, <115>,
>> + <116>;
>> + clock-output-names = "bus_i2c0", "bus_i2c1",
>> + "bus_i2c2", "bus_scr",
>> + "bus_uart0", "bus_uart1",
>> + "bus_uart2", "bus_uart3",
>> + "bus_uart4";
>> + };
>> + };
>
> As I've already told you I'm not really fond of this one, for two main
> topics.
>
> The first one is about the DT bindings itself which is quite exotic,
> especially the fact that you define clocks using clocks, clock-indices
> and clock-output-names in nodes that are not the one referred to by
> consumer, which goes against both the clock bindings documentation and
> the usage.
You are right in one point: it is not documented. I just see that I
forgot to update the bindings doc and describe this behaviour there.
But I don't see an issue with abstracting the clock provider's internal
details by referring to the parent node and use the DT's natural tree
structure to properly represent these clock gates. I cannot read
anything in clock-bindings.txt that would prevent this.
Happy to hear from DT maintainers about it.
> The second one is pretty much the same one than for the discussion we
> had about pinctrl. There is SoCs where we simply don't have that
> information, or at least are not really sure about what to put where
> (namely, the A83t). In such a case, we would knowingly put invalid
> information in the DT, which is already quite bad in itself.
And in your case we would put knowingly invalid information into the kernel?
So what is wrong with just _not_ putting this information until we know
it? With my patch you would just enumerate the gates we know the parents
of so far. Once we learn about the other gates, we add them. If we don't
know the parent, we probably can't use it anyway, I guess.
So we do as we do with other new features: updated DTs provide new
functionality.
And also: this is about A64, not A83t.
> The worst
> part is, when we will identify issues and fix them (hopefully), there
> will be no way to fix the current DT users.
But if we have a broken DT out there where a feature never worked or had
bugs, we _can_ fix it. Interested users will upgrade their DT and are
able to use the new feature or run without bugs now. This mimics the
approach when we add features: users update. However if users are happy
with the current feature set or are not affected by the bug, they can
use the older DT.
Also from my point of view it is much harder to provide an updated
kernel to people, since every distribution would need to pick up the
changes and provide updates to their users.
> And it just became a pain to maintain in the long run.
How so?
> On the opposite side, having something like the H3 bus gates driver
> address all these concerns and is easily extensible, which is why we
> ended up merging it.
Speaking of this driver: I really dislike that it hardcodes Soc specific
information into the kernel. I consider this bad style. The clock gates
are a rather generic functionality (one bit per gate), and we provide
the SoC specific part (mapping names and bit numbers) already in the DT.
So with the parent relation in the code we hide some information from
the DT which clearly belongs there, also ending up with having something
in the kernel and something in the DT.
Also this requires to add support for each and every SoC explicitly in
the kernel.
Also please keep in mind that the DT is not just for Linux: why should
other OS developers hard code the same information over and over again
when we could have it once for everybody in the DT?
I think we should stop with supporting each and every SoC explicitly in
the kernel and go for more generic drivers, that use DTs to describe
each SoC.
That way we can eventually reach the point where we have (at least)
basic functionality for a new SoC in existing(!) kernels - like from a
LTS style distribution kernel.
New SoCs would just come with their DTs as part of their firmware, as
it's the case with many arm64 boards out there at the moment. As long as
they don't have fundamentally new IP blocks (for the basic
functionality), that could just work out of the box.
> So please use it.
I really rather would avoid doing this.
I would appreciate if other people could comment on this.
>
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc0",
>> + "mmc0_output",
>> + "mmc0_sample";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc1",
>> + "mmc1_output",
>> + "mmc1_sample";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> + clock-output-names = "mmc2",
>> + "mmc2_output",
>> + "mmc2_sample";
>> + };
>> + };
>> +
>> + regulators {
>> + reg_vcc3v3: vcc3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + };
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&bus_gates 8>,
>> + <&mmc0_clk 0>,
>> + <&mmc0_clk 1>,
>> + <&mmc0_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&bus_gates 9>,
>> + <&mmc1_clk 0>,
>> + <&mmc1_clk 1>,
>> + <&mmc1_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&bus_gates 10>,
>> + <&mmc2_clk 0>,
>> + <&mmc2_clk 1>,
>> + <&mmc2_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,a64-pinctrl";
>> + reg = <0x01c20800 0x400>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bus_gates 69>;
>> + gpio-controller;
>> + #gpio-cells = <3>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PB8", "PB9";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart0_pins_b: uart0@1 {
>> + allwinner,pins = "PF2", "PF3";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart1_pins: uart1@0 {
>> + allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> + allwinner,function = "uart1";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart2_pins: uart2@0 {
>> + allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> + allwinner,function = "uart2";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_a: uart3@0 {
>> + allwinner,pins = "PD0", "PD1";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + uart3_pins_b: uart3@1 {
>> + allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> + allwinner,function = "uart3";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>
> You have several options for all these controllers, which is why we
> have the _a or _b suffices.
>
> Usually, the uart pins we had were only using RX and TX, I guess you
> could add a separate node for the RTS / CTS pins if some board want to
> use them.
Makes sense. Do you want the RTS/CTS pins in a separate child node or
another variant (like uart3_pins_b_hwhs) with all four pins in addition
to the two-pin version?
Cheers,
Andre
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-01 18:50 +0100 |
| Subject | [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm |
| Message-ID | <qXqLU-6lT-13@gated-at.bofh.it> |
| In reply to | #1323352 |
The Allwinner sunxi specific interrupt controller cannot be compiled for any architecture except arm: drivers/irqchip/irq-sun4i.c:25:26: fatal error: asm/mach/irq.h: No such file or directory compilation terminated. It turns out that this header is actually not needed for the driver, so remove it and allow compilation for other architectures like arm64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> --- drivers/irqchip/irq-sun4i.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 0704362..376b280 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -22,7 +22,6 @@ #include <linux/of_irq.h> #include <asm/exception.h> -#include <asm/mach/irq.h> #define SUN4I_IRQ_VECTOR_REG 0x00 #define SUN4I_IRQ_PROTECTION_REG 0x08 -- 2.6.4
[toc] | [prev] | [next] | [standalone]
| From | tip-bot for Andre Przywara <tipbot@zytor.com> |
|---|---|
| Date | 2016-02-02 16:00 +0100 |
| Subject | [tip:irq/urgent] irqchip/sun4i: Fix compilation outside of arch/ arm |
| Message-ID | <qXKAW-4oM-11@gated-at.bofh.it> |
| In reply to | #1323360 |
Commit-ID: 6235f0ecc4ed799169b80f7317c7f974f7415320 Gitweb: http://git.kernel.org/tip/6235f0ecc4ed799169b80f7317c7f974f7415320 Author: Andre Przywara <andre.przywara@arm.com> AuthorDate: Mon, 1 Feb 2016 17:39:20 +0000 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Tue, 2 Feb 2016 15:46:40 +0100 irqchip/sun4i: Fix compilation outside of arch/arm The Allwinner sunxi specific interrupt controller cannot be compiled for any architecture except arm: drivers/irqchip/irq-sun4i.c:25:26: fatal error: asm/mach/irq.h: No such file or directory compilation terminated. It turns out that this header is actually not needed for the driver, so remove it and allow compilation for other architectures like arm64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-sunxi@googlegroups.com Link: http://lkml.kernel.org/r/1454348370-3816-2-git-send-email-andre.przywara@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- drivers/irqchip/irq-sun4i.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 0704362..376b280 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -22,7 +22,6 @@ #include <linux/of_irq.h> #include <asm/exception.h> -#include <asm/mach/irq.h> #define SUN4I_IRQ_VECTOR_REG 0x00 #define SUN4I_IRQ_PROTECTION_REG 0x08
[toc] | [prev] | [next] | [standalone]
| From | Matthias Brugger <matthias.bgg@gmail.com> |
|---|---|
| Date | 2016-02-02 16:20 +0100 |
| Subject | Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm |
| Message-ID | <qXKUh-4Qa-7@gated-at.bofh.it> |
| In reply to | #1323360 |
On 01/02/16 18:39, Andre Przywara wrote: > The Allwinner sunxi specific interrupt controller cannot be compiled > for any architecture except arm: s/arm/arm64
[toc] | [prev] | [next] | [standalone]
| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-02 16:40 +0100 |
| Subject | Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm |
| Message-ID | <qXLdE-51l-13@gated-at.bofh.it> |
| In reply to | #1324188 |
Hi, On 02/02/16 15:12, Matthias Brugger wrote: > On 01/02/16 18:39, Andre Przywara wrote: >> The Allwinner sunxi specific interrupt controller cannot be compiled >> for any architecture except arm: > > s/arm/arm64 ??? As it stands it only compiles for arm, and not arm64, so "cannot be compile for any architecture except arm" is the right thing to say, no? Or did I get confused by my own double negation? Cheers, Andre.
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| From | Matthias Brugger <matthias.bgg@gmail.com> |
|---|---|
| Date | 2016-02-02 18:00 +0100 |
| Subject | Re: [PATCH 01/11] irqchip: sun4i: fix compilation outside of arch/arm |
| Message-ID | <qXMt5-5Rl-21@gated-at.bofh.it> |
| In reply to | #1324206 |
On 02/02/16 16:32, Andre Przywara wrote: > Hi, > > On 02/02/16 15:12, Matthias Brugger wrote: >> On 01/02/16 18:39, Andre Przywara wrote: >>> The Allwinner sunxi specific interrupt controller cannot be compiled >>> for any architecture except arm: >> >> s/arm/arm64 > > ??? > > As it stands it only compiles for arm, and not arm64, so "cannot be > compile for any architecture except arm" is the right thing to say, no? > > Or did I get confused by my own double negation? > No, it's just me who get confused. ;) Sorry for the noise.
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-01 18:50 +0100 |
| Subject | [PATCH 08/11] clk: sunxi: improve error reporting for the mux clock |
| Message-ID | <qXqLU-6lT-19@gated-at.bofh.it> |
| In reply to | #1323352 |
clk_register_mux returns a pointer wrapped error value in case of
failure, so a simple NULL check is not sufficient to catch errors.
Fix that and elaborate on the failure reason on the way. The whole
function does not return any error value, so silently failing may
leave users scratching their heads because the kernel does not
provide any clues on what's wrong.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/clk/sunxi/clk-sunxi.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index efcce85..9416e0f3 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -627,17 +627,29 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
reg = of_iomap(node, 0);
i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
- of_property_read_string(node, "clock-output-names", &clk_name);
+ if (of_property_read_string(node, "clock-output-names", &clk_name)) {
+ pr_warn("%s: could not read clock-output-names for \"%s\"\n",
+ __func__, clk_name);
+ goto out_unmap;
+ }
clk = clk_register_mux(NULL, clk_name, parents, i,
CLK_SET_RATE_PARENT, reg,
data->shift, SUNXI_MUX_GATE_WIDTH,
0, &clk_lock);
- if (clk) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, clk_name, NULL);
+ if (IS_ERR(clk)) {
+ pr_warn("%s: failed to register mux clock %s: %ld\n", __func__,
+ clk_name, PTR_ERR(clk));
+ goto out_unmap;
}
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ clk_register_clkdev(clk, clk_name, NULL);
+ return;
+
+out_unmap:
+ iounmap(reg);
}
--
2.6.4
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| From | Andre Przywara <andre.przywara@arm.com> |
|---|---|
| Date | 2016-02-02 19:10 +0100 |
| Subject | Re: [PATCH 08/11] clk: sunxi: improve error reporting for the mux clock |
| Message-ID | <qXNyO-6U3-13@gated-at.bofh.it> |
| In reply to | #1323362 |
Salut, On 02/02/16 18:02, Maxime Ripard wrote: > On Mon, Feb 01, 2016 at 05:39:27PM +0000, Andre Przywara wrote: >> clk_register_mux returns a pointer wrapped error value in case of >> failure, so a simple NULL check is not sufficient to catch errors. >> Fix that and elaborate on the failure reason on the way. The whole >> function does not return any error value, so silently failing may >> leave users scratching their heads because the kernel does not >> provide any clues on what's wrong. >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> > > Applied, thanks. > > Any chance you do that for the other functions? :) Sure, that was actually a test balloon ;-) Cheers, Andre
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