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[PATCH] recordmcount: arm: Implement make_nop

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  [PATCH] recordmcount: arm: Implement make_nop Stephen Boyd <sboyd@codeaurora.org> - 2016-01-30 02:20 +0100
    Re: [PATCH] recordmcount: arm: Implement make_nop Rabin Vincent <rabin@rab.in> - 2016-01-30 19:50 +0100
      Re: [PATCH] recordmcount: arm: Implement make_nop Stephen Boyd <sboyd@codeaurora.org> - 2016-02-01 20:50 +0100
        Re: [PATCH] recordmcount: arm: Implement make_nop Rabin Vincent <rabin@rab.in> - 2016-02-02 18:40 +0100
          Re: [PATCH] recordmcount: arm: Implement make_nop Steven Rostedt <rostedt@goodmis.org> - 2016-02-02 19:00 +0100

#1322220 — [PATCH] recordmcount: arm: Implement make_nop

In similar spirit to x86 and arm64 support, add a make_nop_arm()
to replace calls to mcount with a "nop" in sections that aren't
traced.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Rabin Vincent <rabin@rab.in>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 scripts/recordmcount.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 scripts/recordmcount.h |  3 ++-
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c
index e167592793a7..0b16d14c54fb 100644
--- a/scripts/recordmcount.c
+++ b/scripts/recordmcount.c
@@ -206,6 +206,52 @@ static int make_nop_x86(void *map, size_t const offset)
 	return 0;
 }
 
+/*
+ * Indicates if ARM is using __gnu_mcount_nc or mcount style and if
+ * we should replace it with a pop or a nop respectively.
+ */
+static int uses_altmcount;
+
+static unsigned char ideal_nop4_arm_arm[4] = { 0x00, 0x40, 0xbd, 0xe8 };
+static unsigned char ideal_nop4_arm_thumb[4] = { 0x5d, 0xf8, 0x04, 0xeb };
+static unsigned char ideal_nop4_arm_arm_be[4] = { 0xe8, 0xbd, 0x40, 0x00 };
+static unsigned char ideal_nop4_arm_thumb_be[4] = { 0xf8, 0x5d, 0xeb, 0x04 };
+static unsigned char ideal_nop4_arm_old[4] = { 0x00, 0x00, 0xa0, 0xe1 };
+static unsigned char ideal_nop4_arm_old_be[4] = { 0xe1, 0xa0, 0x00, 0x00 };
+
+static unsigned char bl_gnu_mcount_nc_arm[4] = { 0xfe, 0xff, 0xff, 0xeb };
+static unsigned char bl_gnu_mcount_nc_thumb[4] = { 0xff, 0xf7, 0xfe, 0xff };
+static unsigned char bl_gnu_mcount_nc_arm_be[4] = { 0xeb, 0xff, 0xff, 0xfe };
+static unsigned char bl_gnu_mcount_nc_thumb_be[4] = { 0xf7, 0xff, 0xff, 0xfe };
+
+static int make_nop_arm(void *map, size_t const offset)
+{
+	uint32_t *ptr;
+
+	ptr = map + offset;
+	if (memcmp(ptr, bl_gnu_mcount_nc_arm, 4) == 0) {
+		if (uses_altmcount)
+			ideal_nop = ideal_nop4_arm_arm;
+		else
+			ideal_nop = ideal_nop4_arm_old;
+	} else if (memcmp(ptr, bl_gnu_mcount_nc_arm_be, 4) == 0) {
+		if (uses_altmcount)
+			ideal_nop = ideal_nop4_arm_arm_be;
+		else
+			ideal_nop = ideal_nop4_arm_old_be;
+	} else if (memcmp(ptr, bl_gnu_mcount_nc_thumb, 4) == 0)
+		ideal_nop = ideal_nop4_arm_thumb;
+	else if (memcmp(ptr, bl_gnu_mcount_nc_thumb_be, 4) == 0)
+		ideal_nop = ideal_nop4_arm_thumb_be;
+	else
+		return -1;
+
+	/* Convert to nop */
+	ulseek(fd_map, offset, SEEK_SET);
+	uwrite(fd_map, ideal_nop, 4);
+	return 0;
+}
+
 static unsigned char ideal_nop4_arm64[4] = {0x1f, 0x20, 0x03, 0xd5};
 static int make_nop_arm64(void *map, size_t const offset)
 {
@@ -454,6 +500,9 @@ do_file(char const *const fname)
 		break;
 	case EM_ARM:	 reltype = R_ARM_ABS32;
 			 altmcount = "__gnu_mcount_nc";
+			 make_nop = make_nop_arm;
+			 rel_type_nop = R_ARM_NONE;
+			 ideal_nop = ideal_nop4_arm_arm;
 			 break;
 	case EM_AARCH64:
 			reltype = R_AARCH64_ABS64;
diff --git a/scripts/recordmcount.h b/scripts/recordmcount.h
index b9897e2be404..890f5211745f 100644
--- a/scripts/recordmcount.h
+++ b/scripts/recordmcount.h
@@ -266,7 +266,8 @@ static unsigned get_mcountsym(Elf_Sym const *const sym0,
 	if (symname[0] == '.')
 		++symname;  /* ppc64 hack */
 	if (strcmp(mcount, symname) == 0 ||
-	    (altmcount && strcmp(altmcount, symname) == 0) ||
+	    (altmcount && strcmp(altmcount, symname) == 0 &&
+	     (uses_altmcount = 1)) ||
 	    (strcmp(fentry, symname) == 0))
 		mcountsym = Elf_r_sym(relp);
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1322489

On Fri, Jan 29, 2016 at 05:18:06PM -0800, Stephen Boyd wrote:
> diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c
> index e167592793a7..0b16d14c54fb 100644
> --- a/scripts/recordmcount.c
> +++ b/scripts/recordmcount.c
> @@ -206,6 +206,52 @@ static int make_nop_x86(void *map, size_t const offset)
>  	return 0;
>  }
>  
> +/*
> + * Indicates if ARM is using __gnu_mcount_nc or mcount style and if
> + * we should replace it with a pop or a nop respectively.
> + */

For __gnu_mcount_nc, wouldn't it be better to replace both the push {lr}
and the bl with nop instructions, instead of keeping a (useless) push +
pop sequence?

> +static int uses_altmcount;
> +
> +static unsigned char ideal_nop4_arm_arm[4] = { 0x00, 0x40, 0xbd, 0xe8 };
> +static unsigned char ideal_nop4_arm_thumb[4] = { 0x5d, 0xf8, 0x04, 0xeb };
> +static unsigned char ideal_nop4_arm_arm_be[4] = { 0xe8, 0xbd, 0x40, 0x00 };
> +static unsigned char ideal_nop4_arm_thumb_be[4] = { 0xf8, 0x5d, 0xeb, 0x04 };
> +static unsigned char ideal_nop4_arm_old[4] = { 0x00, 0x00, 0xa0, 0xe1 };
> +static unsigned char ideal_nop4_arm_old_be[4] = { 0xe1, 0xa0, 0x00, 0x00 };
> +
> +static unsigned char bl_gnu_mcount_nc_arm[4] = { 0xfe, 0xff, 0xff, 0xeb };
> +static unsigned char bl_gnu_mcount_nc_thumb[4] = { 0xff, 0xf7, 0xfe, 0xff };
> +static unsigned char bl_gnu_mcount_nc_arm_be[4] = { 0xeb, 0xff, 0xff, 0xfe };
> +static unsigned char bl_gnu_mcount_nc_thumb_be[4] = { 0xf7, 0xff, 0xff, 0xfe };

Comments showing what assembly instructions all these correspond to
would be helpful.

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#1323438

On 01/30, Rabin Vincent wrote:
> On Fri, Jan 29, 2016 at 05:18:06PM -0800, Stephen Boyd wrote:
> > diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c
> > index e167592793a7..0b16d14c54fb 100644
> > --- a/scripts/recordmcount.c
> > +++ b/scripts/recordmcount.c
> > @@ -206,6 +206,52 @@ static int make_nop_x86(void *map, size_t const offset)
> >  	return 0;
> >  }
> >  
> > +/*
> > + * Indicates if ARM is using __gnu_mcount_nc or mcount style and if
> > + * we should replace it with a pop or a nop respectively.
> > + */
> 
> For __gnu_mcount_nc, wouldn't it be better to replace both the push {lr}
> and the bl with nop instructions, instead of keeping a (useless) push +
> pop sequence?

Agreed. I was trying to do a 1-to-1 copy of the ftrace code on
ARM.  I was wondering the same thing in that code path while
doing this though. Can't we replace both instructions instead of
one instruction when we're patching in nops at runtime?

> 
> > +static int uses_altmcount;
> > +
> > +static unsigned char ideal_nop4_arm_arm[4] = { 0x00, 0x40, 0xbd, 0xe8 };
> > +static unsigned char ideal_nop4_arm_thumb[4] = { 0x5d, 0xf8, 0x04, 0xeb };
> > +static unsigned char ideal_nop4_arm_arm_be[4] = { 0xe8, 0xbd, 0x40, 0x00 };
> > +static unsigned char ideal_nop4_arm_thumb_be[4] = { 0xf8, 0x5d, 0xeb, 0x04 };
> > +static unsigned char ideal_nop4_arm_old[4] = { 0x00, 0x00, 0xa0, 0xe1 };
> > +static unsigned char ideal_nop4_arm_old_be[4] = { 0xe1, 0xa0, 0x00, 0x00 };
> > +
> > +static unsigned char bl_gnu_mcount_nc_arm[4] = { 0xfe, 0xff, 0xff, 0xeb };
> > +static unsigned char bl_gnu_mcount_nc_thumb[4] = { 0xff, 0xf7, 0xfe, 0xff };
> > +static unsigned char bl_gnu_mcount_nc_arm_be[4] = { 0xeb, 0xff, 0xff, 0xfe };
> > +static unsigned char bl_gnu_mcount_nc_thumb_be[4] = { 0xf7, 0xff, 0xff, 0xfe };
> 
> Comments showing what assembly instructions all these correspond to
> would be helpful.

Sure.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1324316

On Mon, Feb 01, 2016 at 11:44:32AM -0800, Stephen Boyd wrote:
> On 01/30, Rabin Vincent wrote:
> > For __gnu_mcount_nc, wouldn't it be better to replace both the push {lr}
> > and the bl with nop instructions, instead of keeping a (useless) push +
> > pop sequence?
> 
> Agreed. I was trying to do a 1-to-1 copy of the ftrace code on
> ARM.  I was wondering the same thing in that code path while
> doing this though. Can't we replace both instructions instead of
> one instruction when we're patching in nops at runtime?

As Steven pointed out the last time this came up, we can't do it safely
at runtime:

https://marc.info/?l=linux-arm-kernel&m=132517584531389&w=2

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#1324342

On Tue, 2 Feb 2016 18:31:41 +0100
Rabin Vincent <rabin@rab.in> wrote:

> On Mon, Feb 01, 2016 at 11:44:32AM -0800, Stephen Boyd wrote:
> > On 01/30, Rabin Vincent wrote:  
> > > For __gnu_mcount_nc, wouldn't it be better to replace both the push {lr}
> > > and the bl with nop instructions, instead of keeping a (useless) push +
> > > pop sequence?  
> > 
> > Agreed. I was trying to do a 1-to-1 copy of the ftrace code on
> > ARM.  I was wondering the same thing in that code path while
> > doing this though. Can't we replace both instructions instead of
> > one instruction when we're patching in nops at runtime?  
> 
> As Steven pointed out the last time this came up, we can't do it safely
> at runtime:
> 
> https://marc.info/?l=linux-arm-kernel&m=132517584531389&w=2

There is actually a way to do it, but it requires break points.

	push lr
	call mcount

Now add a break point:

	brk
	call mcount

Anything that hits the breakpoint, have it return after the call to
mcount.

Sync all CPUs where tasks have either hit the breakpoint and is
skipping the mcount regardless, or has already done the push lr and
is calling mcount. To be even more paranoid, you could add a step to:

	brk
	brk

and if the second brkpoint is hit, then call mcount to make sure it
does the necessary step with lr. Again sync the CPUS (which is simply
just sending an IPI to all of them).

Once the breakpoints are in place, you can convert them over to nops.

	brk
	nop

and then to

	nop
	nop

-- Steve

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