Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1322541 > unrolled thread

[PATCH 00/14] Add A83T clk, r_pio, mmc rsb support

Back to article view | Back to linux.kernel

Contents

  [PATCH 00/14] Add A83T clk, r_pio, mmc rsb support Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
    [PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board. Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board. Chen-Yu Tsai <wens@csie.org> - 2016-02-02 08:40 +0100
    [PATCH 03/14] clk: sunxi: add bus gates for A83T Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T Rob Herring <robh@kernel.org> - 2016-02-01 16:10 +0100
        Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T Chen-Yu Tsai <wens@csie.org> - 2016-02-01 16:20 +0100
      Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 14:20 +0100
    [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator  clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 14:20 +0100
      Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator  clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 14:20 +0100
        Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-02-04 10:00 +0100
          Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator  clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-04 13:20 +0100
    [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T Chen-Yu Tsai <wens@csie.org> - 2016-01-31 04:40 +0100
      Re: [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T Rob Herring <robh@kernel.org> - 2016-02-01 16:00 +0100
    [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Rob Herring <robh@kernel.org> - 2016-02-01 15:50 +0100
        Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Chen-Yu Tsai <wens@csie.org> - 2016-02-01 16:00 +0100
      Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 14:20 +0100
        Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-02-04 07:10 +0100
          Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-04 09:10 +0100
    [PATCH 08/14] ARM: dts: sun8i-a83t: add mmc clock nodes Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 08/14] ARM: dts: sun8i-a83t: add mmc clock nodes Chen-Yu Tsai <wens@csie.org> - 2016-01-31 07:20 +0100
    [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets Chen-Yu Tsai <wens@csie.org> - 2016-02-02 07:50 +0100
    [PATCH 12/14] ARM: dts: sun8i-a83t: Add RSB nodes to dtsi Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 12/14] ARM: dts: sun8i-a83t: Add RSB nodes to dtsi Chen-Yu Tsai <wens@csie.org> - 2016-01-31 05:00 +0100
    [PATCH 09/14] ARM: dts: sun8i-a83t: Add mmc controller nodes Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 09/14] ARM: dts: sun8i-a83t: Add mmc controller nodes Chen-Yu Tsai <wens@csie.org> - 2016-02-02 07:40 +0100
    [PATCH 02/14] clk: sunxi: Add apb0 gates for A83T Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 02/14] clk: sunxi: Add apb0 gates for A83T Rob Herring <robh@kernel.org> - 2016-02-01 16:10 +0100
        Re: [PATCH 02/14] clk: sunxi: Add apb0 gates for A83T Chen-Yu Tsai <wens@csie.org> - 2016-02-01 16:20 +0100
      Re: [PATCH 02/14] clk: sunxi: Add apb0 gates for A83T Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-02-02 14:20 +0100
    [PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-01-31 02:30 +0100
      Re: [PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board Chen-Yu Tsai <wens@csie.org> - 2016-02-02 08:40 +0100
        Re: [PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board Vishnu Patekar <vishnupatekar0510@gmail.com> - 2016-02-04 05:30 +0100

Page 1 of 2  [1] 2  Next page →

#1322541 — [PATCH 00/14] Add A83T clk, r_pio, mmc rsb support

Hello,
This series adds further support for A83T, mainly adds clock support.
Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

Patch 1: adds support for r_pio pin controller.

patch 2: adds PRCM apb0 clock gates, it controls prcm related clocks.

patch 3: adds bus gates which are similar to h3, it's not clearly known which
clocks belongs to which parent.

patch 4: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 5: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 6: this patch is form wens, a83t has 16M internal oscillator, to get 
aproximately 32k clock, it's divided by 512.

patch 7: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 8-9: adds mmc and it's clock nodes.

patch 10: adds A83T PRCM related clocks, clock resets.

patch 11: adds r_pio pin controller nodes to dtsi

patch 12: adds RSB nodes to dtsi

patch 13: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 14: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.


Regards,
Vishnu

Chen-Yu Tsai (1):
  ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller support
  clk: sunxi: Add apb0 gates for A83T
  clk: sunxi: add bus gates for A83T
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB nodes to dtsi
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

 Documentation/devicetree/bindings/clock/sunxi.txt  |   4 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  20 ++
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  28 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi                  | 314 ++++++++++++++++++++-
 drivers/clk/sunxi/clk-simple-gates.c               |   2 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c            |   2 +
 drivers/clk/sunxi/clk-sunxi.c                      |  92 ++++++
 drivers/pinctrl/sunxi/Kconfig                      |   5 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       | 119 ++++++++
 12 files changed, 582 insertions(+), 7 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} (79%)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

[toc] | [next] | [standalone]

#1322542 — [PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board.

This enables mmc0.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Tested-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts    | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..6c1f598 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
 	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,25 @@
 	};
 };
 
+&pio {
+	mmc0_cd_pin_h8homlet: mmc0_cd_pin@0 {
+		allwinner,pins = "PF6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h8homlet>;
+	vmmc-supply = <&reg_vcc3v0>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	bus-width = <4>;
+	cd-inverted;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1323853 — Re: [PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board.

Hi,

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This enables mmc0.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> Tested-by: LABBE Corentin <clabbe.montjoie@gmail.com>
> ---
>  .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts    | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> index 342e1d3..6c1f598 100644
> --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> @@ -43,6 +43,7 @@
>
>  /dts-v1/;
>  #include "sun8i-a83t.dtsi"
> +#include "sunxi-common-regulators.dtsi"
>
>  / {
>         model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
> @@ -57,6 +58,25 @@
>         };
>  };
>
> +&pio {
> +       mmc0_cd_pin_h8homlet: mmc0_cd_pin@0 {
> +               allwinner,pins = "PF6";
> +               allwinner,function = "gpio_in";
> +               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +       };
> +};
> +

Please keep them alphabetically sorted.

> +&mmc0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h8homlet>;
> +       vmmc-supply = <&reg_vcc3v0>;

The board design says 3.3V, but stock firmware uses 3.0V. I guess both work.

> +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> +       bus-width = <4>;
> +       cd-inverted;
> +       status = "okay";
> +};
> +

There's also eMMC onboard. Have you tried that?


Thanks!
ChenYu


>  &uart0 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&uart0_pins_b>;
> --
> 1.9.1
>

[toc] | [prev] | [next] | [standalone]

#1322544 — [PATCH 03/14] clk: sunxi: add bus gates for A83T

A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 7f19ef5..4514d77 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -59,6 +59,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+	"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
 	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
 	"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 1113eb9..63fdb79 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
 	       sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+	       sun8i_h3_bus_gates_init);
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1323217 — Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>  2 files changed, 3 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

[toc] | [prev] | [next] | [standalone]

#1323228 — Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

On Mon, Feb 1, 2016 at 11:03 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
>> A83T has similar bus gates that of H3, including single gating register has
>> different clock parent.
>>
>> As per H3 and A83T datasheet, usbhost is under AHB2.
>>
>> However,below shows allwinner source code assignment:
>> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
>> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
>> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
>>
>> until, this confusion is cleared keep it H3 way.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>>  2 files changed, 3 insertions(+)
>
> Acked-by: Rob Herring <robh@kernel.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

We should really get the clk parents sorted out though.

[toc] | [prev] | [next] | [standalone]

#1324068 — Re: [PATCH 03/14] clk: sunxi: add bus gates for A83T

[Multipart message — attachments visible in raw view] — view raw

On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 7f19ef5..4514d77 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -59,6 +59,7 @@ Required properties:
>  	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>  	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
> +	"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T

Please order them alphabetically next time.

Applied with the fix, and the Acked-bys

thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1322545 — [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

From: Chen-Yu Tsai <wens@csie.org>

The A83T does not have a 32.768 kHz low speed oscillator, either as
an external crystal or input. It has a 16 MHz RC-based (inaccurate)
internal oscillator, which is then divided by 512 for a clock close
to 32 kHz.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 8d27b63..45b725c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -118,6 +118,7 @@
 		#size-cells = <1>;
 		ranges;
 
+		/* TODO: PRCM block has a mux for this. */
 		osc24M: osc24M_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -125,11 +126,25 @@
 			clock-output-names = "osc24M";
 		};
 
-		osc32k: osc32k_clk {
+		/*
+		 * This is called "internal OSC" in some places.
+		 * It is an internal RC-based oscillator.
+		 * TODO: Its controls are in the PRCM block.
+		 */
+		osc16M: osc16M_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-output-names = "osc32k";
+			clock-frequency = <16000000>;
+			clock-output-names = "osc16M";
+		};
+
+		osc16Md512: osc16Md512_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <512>;
+			clock-mult = <1>;
+			clocks = <&osc16M>;
+			clock-output-names = "osc16Md512";
 		};
 	};
 
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1324060 — Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Multipart message — attachments visible in raw view] — view raw

1;4002;0c
On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A83T does not have a 32.768 kHz low speed oscillator, either as
> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> internal oscillator, which is then divided by 512 for a clock close
> to 32 kHz.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 8d27b63..45b725c 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -118,6 +118,7 @@
>  		#size-cells = <1>;
>  		ranges;
>  
> +		/* TODO: PRCM block has a mux for this. */
>  		osc24M: osc24M_clk {
>  			#clock-cells = <0>;
>  			compatible = "fixed-clock";
> @@ -125,11 +126,25 @@
>  			clock-output-names = "osc24M";
>  		};
>  
> -		osc32k: osc32k_clk {
> +		/*
> +		 * This is called "internal OSC" in some places.
> +		 * It is an internal RC-based oscillator.
> +		 * TODO: Its controls are in the PRCM block.
> +		 */
> +		osc16M: osc16M_clk {
>  			#clock-cells = <0>;
>  			compatible = "fixed-clock";
> -			clock-frequency = <32768>;
> -			clock-output-names = "osc32k";
> +			clock-frequency = <16000000>;
> +			clock-output-names = "osc16M";
> +		};
> +
> +		osc16Md512: osc16Md512_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <512>;
> +			clock-mult = <1>;
> +			clocks = <&osc16M>;
> +			clock-output-names = "osc16Md512";

We've been using a dash to separate between the clock and its divider
on other SoCs.

I changed that and applied the patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1324065 — Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Multipart message — attachments visible in raw view] — view raw

On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A83T does not have a 32.768 kHz low speed oscillator, either as
> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> internal oscillator, which is then divided by 512 for a clock close
> to 32 kHz.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

You should have your SoB here.

Is it ok to add it?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1326493 — Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

Hello Maxime,


On Tue, Feb 2, 2016 at 9:19 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>>
>> The A83T does not have a 32.768 kHz low speed oscillator, either as
>> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
>> internal oscillator, which is then divided by 512 for a clock close
>> to 32 kHz.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> You should have your SoB here.
>
> Is it ok to add it?
Yes, please add.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1326720 — Re: [PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Multipart message — attachments visible in raw view] — view raw

On Thu, Feb 04, 2016 at 04:51:06PM +0800, Vishnu Patekar wrote:
> Hello Maxime,
> 
> 
> On Tue, Feb 2, 2016 at 9:19 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> >> From: Chen-Yu Tsai <wens@csie.org>
> >>
> >> The A83T does not have a 32.768 kHz low speed oscillator, either as
> >> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> >> internal oscillator, which is then divided by 512 for a clock close
> >> to 32 kHz.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >
> > You should have your SoB here.
> >
> > Is it ok to add it?
> Yes, please add.

Done, thanks.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1322546 — [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index bfd82f1..10637e7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -49,6 +49,7 @@ Required properties:
 	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
 	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+	"allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
 	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
 	"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
 	"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 02bbdf6..6510b0e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -772,6 +772,22 @@ static const struct div_data sun4i_apb0_data __initconst = {
 	.table	= sun4i_apb0_table,
 };
 
+
+static const struct clk_div_table sun8i_a83t_apb1_table[] __initconst = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 3 },
+	{ .val = 3, .div = 4 },
+	{ } /* sentinel */
+};
+
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+	.shift	= 8,
+	.pow	= 0,
+	.width	= 2,
+	.table	= sun8i_a83t_apb1_table,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
 					   struct div_data *data)
 {
@@ -1027,6 +1043,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 	{.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
 	{.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
 	{.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
+	{.compatible = "allwinner,sun8i-a83t-apb1-clk", .data = &sun8i_a83t_apb1_data,},
 	{}
 };
 
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1322566 — Re: [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
>
> This adds support for apb1 on A83T.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>  drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index bfd82f1..10637e7 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -49,6 +49,7 @@ Required properties:
>         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
>         "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
>         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> +       "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
>         "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
>         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
>         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 02bbdf6..6510b0e 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -772,6 +772,22 @@ static const struct div_data sun4i_apb0_data __initconst = {
>         .table  = sun4i_apb0_table,
>  };
>
> +
> +static const struct clk_div_table sun8i_a83t_apb1_table[] __initconst = {
> +       { .val = 0, .div = 1 },
> +       { .val = 1, .div = 2 },
> +       { .val = 2, .div = 3 },
> +       { .val = 3, .div = 4 },
> +       { } /* sentinel */
> +};

The table is only needed if it cannot be handled by default or with
the div flags,
such as dividers not increasing or not power-of-2.

ChenYu

> +static const struct div_data sun8i_a83t_apb1_data __initconst = {
> +       .shift  = 8,
> +       .pow    = 0,
> +       .width  = 2,
> +       .table  = sun8i_a83t_apb1_table,
> +};
> +
>  static void __init sunxi_divider_clk_setup(struct device_node *node,
>                                            struct div_data *data)
>  {
> @@ -1027,6 +1043,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
>         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
>         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
>         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
> +       {.compatible = "allwinner,sun8i-a83t-apb1-clk", .data = &sun8i_a83t_apb1_data,},
>         {}
>  };
>
> --
> 1.9.1
>

[toc] | [prev] | [next] | [standalone]

#1323199 — Re: [PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

On Sun, Jan 31, 2016 at 09:20:57AM +0800, Vishnu Patekar wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
> 
> This adds support for apb1 on A83T.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)

[toc] | [prev] | [next] | [standalone]

#1322548 — [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
 2 files changed, 76 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 4514d77..bfd82f1 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
 	"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
 	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+	"allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
 	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index e460a6b..02bbdf6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
 	req->rate >>= req->p;
 }
 
+
+#define SUN8I_A83T_AHB1_PARENT_PLL6	2
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+	u8 div, calcp, calcm = 1;
+
+	/*
+	 * clock can only divide, so we will never be able to achieve
+	 * frequencies higher than the parent frequency
+	 */
+	if (req->parent_rate && req->rate > req->parent_rate)
+		req->rate = req->parent_rate;
+
+	div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+	/* calculate pre-divider if parent is pll6 */
+	if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+		if (div < 4)
+			calcp = 0;
+		else if (div / 2 < 4)
+			calcp = 1;
+		else if (div / 4 < 4)
+			calcp = 2;
+		else
+			calcp = 3;
+
+		calcm = DIV_ROUND_UP(div, 1 << calcp);
+	} else {
+		calcp = __roundup_pow_of_two(div);
+		calcp = calcp > 3 ? 3 : calcp;
+	}
+
+	req->rate = (req->parent_rate / calcm) >> calcp;
+	req->p = calcp;
+	req->m = calcm - 1;
+}
+
+/**
+ * sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+ *			 parent index
+ */
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+	req->rate = req->parent_rate;
+
+	/* apply pre-divider first if parent is pll6 */
+	if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+		req->rate /= req->m + 1;
+
+	/* clk divider */
+	req->rate >>= req->p;
+}
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = {
 	.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+	.mux = 12,
+	.muxmask = BIT(1) | BIT(0),
+	.table = &sun6i_ahb1_config,
+	.getter = sun8i_a83t_get_ahb1_factors,
+	.recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
 	.mux = 24,
 	.muxmask = BIT(1) | BIT(0),
@@ -592,6 +661,12 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
 	       sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+	sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+	       sun8i_a83t_ahb1_clk_setup);
 
 /**
  * sunxi_mux_clk_setup() - Setup function for muxes
-- 
1.9.1

[toc] | [prev] | [next] | [standalone]

#1323187 — Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
>  2 files changed, 76 insertions(+)

[toc] | [prev] | [next] | [standalone]

#1323207 — Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

On Mon, Feb 1, 2016 at 10:49 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>
> Acked-by: Rob Herring <robh@kernel.org>
>
>>  drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
>>  2 files changed, 76 insertions(+)

Acked-by: Chen-Yu Tsai <wens@csie.org>

[toc] | [prev] | [next] | [standalone]

#1324064 — Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

If the clock is the same but the parents are different, then we don't
need to duplicate all the logic. Simply add the number of parents to
mux_data, and you're all set.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

#1326425 — Re: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

Hello Maxime,


On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>
> If the clock is the same but the parents are different, then we don't
> need to duplicate all the logic. Simply add the number of parents to
> mux_data, and you're all set.

Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
0b10 and 0b11 is pll6/pre_div.
So, just adding number of parents to mux_data will not solve problem.

Regards,
Vishnu
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[toc] | [prev] | [next] | [standalone]

Page 1 of 2  [1] 2  Next page →

Back to top | Article view | linux.kernel

csiph-web