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[PATCH 0/3] Imagination Technologies MIPS P6600 CPU Support

Started byPaul Burton <paul.burton@imgtec.com>
First post2016-02-03 04:30 +0100
Last post2016-02-03 20:50 +0100
Articles 5 — 2 participants

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  [PATCH 0/3] Imagination Technologies MIPS P6600 CPU Support Paul Burton <paul.burton@imgtec.com> - 2016-02-03 04:30 +0100
    [PATCH 1/3] MIPS: Add P6600 PRID & cpu_type_enum values Paul Burton <paul.burton@imgtec.com> - 2016-02-03 04:30 +0100
    [PATCH 3/3] MIPS: Probe the P6600 core Paul Burton <paul.burton@imgtec.com> - 2016-02-03 04:30 +0100
    [PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements Paul Burton <paul.burton@imgtec.com> - 2016-02-03 04:30 +0100
      Re: [PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements "Maciej W. Rozycki" <macro@imgtec.com> - 2016-02-03 20:50 +0100

#1324873 — [PATCH 0/3] Imagination Technologies MIPS P6600 CPU Support

FromPaul Burton <paul.burton@imgtec.com>
Date2016-02-03 04:30 +0100
Subject[PATCH 0/3] Imagination Technologies MIPS P6600 CPU Support
Message-ID<qXWiK-4Pu-3@gated-at.bofh.it>
This series introduces support for probing the Imagination Technologies
P6600 CPU, a high end multi-core out-of-order MIPS64r6 CPU with features
such as SIMD & hardware supported virtualization.

We already have support in place for the required CM/CPS features so
this simply adds the PRID, probes for it & adds various switch cases.

Paul Burton (3):
  MIPS: Add P6600 PRID & cpu_type_enum values
  MIPS: Add P6600 cases to CPU switch statements
  MIPS: Probe the P6600 core

 arch/mips/include/asm/cpu-type.h     | 1 +
 arch/mips/include/asm/cpu.h          | 3 ++-
 arch/mips/kernel/cpu-probe.c         | 5 +++++
 arch/mips/kernel/perf_event_mipsxx.c | 6 ++++++
 arch/mips/kernel/spram.c             | 1 +
 arch/mips/kernel/traps.c             | 1 +
 arch/mips/mm/c-r4k.c                 | 1 +
 arch/mips/mm/sc-mips.c               | 1 +
 8 files changed, 18 insertions(+), 1 deletion(-)

-- 
2.7.0

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#1324875 — [PATCH 1/3] MIPS: Add P6600 PRID & cpu_type_enum values

FromPaul Burton <paul.burton@imgtec.com>
Date2016-02-03 04:30 +0100
Subject[PATCH 1/3] MIPS: Add P6600 PRID & cpu_type_enum values
Message-ID<qXWiK-4Pu-9@gated-at.bofh.it>
In reply to#1324873
Define the processor ID for the P6600 core and add a value to the enum
cpu_type_enum for the core.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index a97ca97..7908dc2 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -118,6 +118,7 @@
 #define PRID_IMP_INTERAPTIV_MP	0xa100
 #define PRID_IMP_PROAPTIV_UP	0xa200
 #define PRID_IMP_PROAPTIV_MP	0xa300
+#define PRID_IMP_P6600		0xa400
 #define PRID_IMP_M5150		0xa700
 #define PRID_IMP_P5600		0xa800
 #define PRID_IMP_I6400		0xa900
@@ -308,7 +309,7 @@ enum cpu_type_enum {
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
-	CPU_I6400,
+	CPU_I6400, CPU_P6600,
 
 	/*
 	 * MIPS64 class processors
-- 
2.7.0

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#1324876 — [PATCH 3/3] MIPS: Probe the P6600 core

FromPaul Burton <paul.burton@imgtec.com>
Date2016-02-03 04:30 +0100
Subject[PATCH 3/3] MIPS: Probe the P6600 core
Message-ID<qXWiK-4Pu-11@gated-at.bofh.it>
In reply to#1324873
Support probing the P6600 core now that cases for handling it have been
added throughout the core MIPS kernel code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/kernel/cpu-probe.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bc54458..92cc4d8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1315,6 +1315,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_P5600;
 		__cpu_name[cpu] = "MIPS P5600";
 		break;
+	case PRID_IMP_P6600:
+		c->cputype = CPU_P6600;
+		__cpu_name[cpu] = "MIPS P6600";
+		break;
 	case PRID_IMP_I6400:
 		c->cputype = CPU_I6400;
 		__cpu_name[cpu] = "MIPS I6400";
-- 
2.7.0

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#1324877 — [PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements

FromPaul Burton <paul.burton@imgtec.com>
Date2016-02-03 04:30 +0100
Subject[PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements
Message-ID<qXWiK-4Pu-13@gated-at.bofh.it>
In reply to#1324873
Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/cpu-type.h     | 1 +
 arch/mips/kernel/cpu-probe.c         | 1 +
 arch/mips/kernel/perf_event_mipsxx.c | 6 ++++++
 arch/mips/kernel/spram.c             | 1 +
 arch/mips/kernel/traps.c             | 1 +
 arch/mips/mm/c-r4k.c                 | 1 +
 arch/mips/mm/sc-mips.c               | 1 +
 7 files changed, 12 insertions(+)

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index abee2bf..2cb0979 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -79,6 +79,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
 	case CPU_I6400:
+	case CPU_P6600:
 #endif
 
 #ifdef CONFIG_SYS_HAS_CPU_R3000
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b725b71..bc54458 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -539,6 +539,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 	switch (c->cputype) {
 	case CPU_PROAPTIV:
 	case CPU_P5600:
+	case CPU_P6600:
 		/* proAptiv & related cores use Config6 to enable the FTLB */
 		config = read_c0_config6();
 		/* Clear the old probability value */
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index d7b8dd4..ae378d9 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
 		break;
 	case CPU_P5600:
+	case CPU_P6600:
 	case CPU_I6400:
 		/* 8-bit event numbers */
 		raw_id = config & 0x1ff;
@@ -1718,6 +1719,11 @@ init_hw_perf_events(void)
 		mipspmu.general_event_map = &mipsxxcore_event_map2;
 		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
 		break;
+	case CPU_P6600:
+		mipspmu.name = "mips/P6600";
+		mipspmu.general_event_map = &mipsxxcore_event_map2;
+		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+		break;
 	case CPU_I6400:
 		mipspmu.name = "mips/I6400";
 		mipspmu.general_event_map = &mipsxxcore_event_map2;
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 8489c88..d6e6cf7 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -210,6 +210,7 @@ void spram_config(void)
 	case CPU_P5600:
 	case CPU_QEMU_GENERIC:
 	case CPU_I6400:
+	case CPU_P6600:
 		config0 = read_c0_config();
 		/* FIXME: addresses are Malta specific */
 		if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index bafcb7a..f7dfe60 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1653,6 +1653,7 @@ static inline void parity_protection_init(void)
 	case CPU_P5600:
 	case CPU_QEMU_GENERIC:
 	case CPU_I6400:
+	case CPU_P6600:
 		{
 #define ERRCTL_PE	0x80000000
 #define ERRCTL_L2P	0x00800000
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index caac3d7..2f47999 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1278,6 +1278,7 @@ static void probe_pcache(void)
 	case CPU_M5150:
 	case CPU_QEMU_GENERIC:
 	case CPU_I6400:
+	case CPU_P6600:
 		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
 		    (c->icache.waysize > PAGE_SIZE))
 			c->icache.flags |= MIPS_CACHE_ALIASES;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 3bd0597..91006c2 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -141,6 +141,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
 	case CPU_P5600:
 	case CPU_BMIPS5000:
 	case CPU_QEMU_GENERIC:
+	case CPU_P6600:
 		if (config2 & (1 << 12))
 			return 0;
 	}
-- 
2.7.0

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#1325894 — Re: [PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements

From"Maciej W. Rozycki" <macro@imgtec.com>
Date2016-02-03 20:50 +0100
SubjectRe: [PATCH 2/3] MIPS: Add P6600 cases to CPU switch statements
Message-ID<qYbB7-6f1-1@gated-at.bofh.it>
In reply to#1324877
On Wed, 3 Feb 2016, Paul Burton wrote:

> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index d7b8dd4..ae378d9 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
>  #endif
>  		break;
>  	case CPU_P5600:
> +	case CPU_P6600:
>  	case CPU_I6400:
>  		/* 8-bit event numbers */
>  		raw_id = config & 0x1ff;
> @@ -1718,6 +1719,11 @@ init_hw_perf_events(void)
>  		mipspmu.general_event_map = &mipsxxcore_event_map2;
>  		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
>  		break;
> +	case CPU_P6600:
> +		mipspmu.name = "mips/P6600";
> +		mipspmu.general_event_map = &mipsxxcore_event_map2;
> +		mipspmu.cache_event_map = &mipsxxcore_cache_map2;
> +		break;
>  	case CPU_I6400:
>  		mipspmu.name = "mips/I6400";
>  		mipspmu.general_event_map = &mipsxxcore_event_map2;
> diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
> index 8489c88..d6e6cf7 100644
> --- a/arch/mips/kernel/spram.c
> +++ b/arch/mips/kernel/spram.c
> @@ -210,6 +210,7 @@ void spram_config(void)
>  	case CPU_P5600:
>  	case CPU_QEMU_GENERIC:
>  	case CPU_I6400:
> +	case CPU_P6600:
>  		config0 = read_c0_config();
>  		/* FIXME: addresses are Malta specific */
>  		if (config0 & (1<<24)) {

 Minor nit: you sometimes place the I6400 before and sometimes after the 
P6600 -- would it make sense to keep the ordering consistent?

  Maciej

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