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[PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

Started byKrzysztof Adamski <k@japko.eu>
First post2016-02-02 22:30 +0100
Last post2016-02-03 08:10 +0100
Articles 5 — 2 participants

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  [PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support Krzysztof Adamski <k@japko.eu> - 2016-02-02 22:30 +0100
    [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Krzysztof Adamski <k@japko.eu> - 2016-02-02 22:30 +0100
      Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set Chen-Yu Tsai <wens@csie.org> - 2016-02-03 08:10 +0100
    [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3 Krzysztof Adamski <k@japko.eu> - 2016-02-02 22:30 +0100
      Re: [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3 Chen-Yu Tsai <wens@csie.org> - 2016-02-03 08:10 +0100

#1324646 — [PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

FromKrzysztof Adamski <k@japko.eu>
Date2016-02-02 22:30 +0100
Subject[PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support
Message-ID<qXQGm-FZ-3@gated-at.bofh.it>
This patch series is extension of my original single patch with the
same subject. It adds support for R_PIO so that GPIO port L can be
used in H3 based devices. It was tested on OrangePi PC where PL is
connected amount others to an onboard led, a switch and IR receiver and
some VCC controllers.

Patchset was based on next-20160129.

--- 

Changes since v1:
- splited patch to two separate - dtsi and c files
- added APB0 clocks a parent for R_PIO
- added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq
  mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt


Krzysztof Adamski (5):
  clk: sunxi: Add apb0 gates for H3
  dts: sun8i-h3: Add APB0 related clocks and resets
  pinctrl: sunxi: Add H3 R_PIO controller support
  ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
  pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

 Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  44 +++++++++
 drivers/clk/sunxi/clk-simple-gates.c               |   2 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c         | 106 +++++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c              |   9 +-
 8 files changed, 165 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c

-- 
2.1.4

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#1324648 — [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

FromKrzysztof Adamski <k@japko.eu>
Date2016-02-02 22:30 +0100
Subject[PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set
Message-ID<qXQGn-FZ-19@gated-at.bofh.it>
In reply to#1324646
sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.

This was only used on A10 so far, where there is only one GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 7a2465f..9e5bac9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 	u32 set_mux = pctl->desc->irq_read_needs_mux &&
 			test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
 	u32 val;
+	u32 pin;
 
-	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
+	if (set_mux) {
+		pin = offset + pctl->desc->pin_base;
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
+	}
 
 	val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 
 	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 
 	return !!val;
 }
-- 
2.1.4

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#1324976 — Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

FromChen-Yu Tsai <wens@csie.org>
Date2016-02-03 08:10 +0100
SubjectRe: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set
Message-ID<qXZJD-78a-1@gated-at.bofh.it>
In reply to#1324648
Hi,

On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski <k@japko.eu> wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 7a2465f..9e5bac9 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
>         u32 set_mux = pctl->desc->irq_read_needs_mux &&
>                         test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
>         u32 val;
> +       u32 pin;
>
> -       if (set_mux)
> -               sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
> +       if (set_mux) {
> +               pin = offset + pctl->desc->pin_base;

You can use chip->base directly. It's value is set to pin_base in the
init function.
You could also move this out of the if block, and not add the braces.

Otherwise this looks good.

ChenYu

> +               sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
> +       }
>
>         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
>
>         if (set_mux)
> -               sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
> +               sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
>
>         return !!val;
>  }
> --
> 2.1.4
>

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#1324652 — [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3

FromKrzysztof Adamski <k@japko.eu>
Date2016-02-02 22:30 +0100
Subject[PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3
Message-ID<qXQGn-FZ-37@gated-at.bofh.it>
In reply to#1324646
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..6ee6875 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -32,6 +32,7 @@ Required properties:
 	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+	"allwinner,sun8i-h3-abp0-gates-clk" - for the APB0 gates on H3
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
 	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
 	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index f4da52b..8a1fa3e 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
 	       sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_h3_abp0, "allwinner,sun8i-h3-abp0-gates-clk",
+	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
-- 
2.1.4

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#1324977 — Re: [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3

FromChen-Yu Tsai <wens@csie.org>
Date2016-02-03 08:10 +0100
SubjectRe: [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3
Message-ID<qXZJE-78a-7@gated-at.bofh.it>
In reply to#1324652
On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski <k@japko.eu> wrote:
> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> etc).
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..6ee6875 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -32,6 +32,7 @@ Required properties:
>         "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> +       "allwinner,sun8i-h3-abp0-gates-clk" - for the APB0 gates on H3

The list is grouped by clock type (AHB/APB/...) then family then SoC.
Please put this in the apb0 section below.

ChenYu

>         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>         "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>         "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> index f4da52b..8a1fa3e 100644
> --- a/drivers/clk/sunxi/clk-simple-gates.c
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
>                sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
>                sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_h3_abp0, "allwinner,sun8i-h3-abp0-gates-clk",
> +              sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
>                sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> --
> 2.1.4
>

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