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RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

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  RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge  driver to  work on both  Zynq and Microblaze Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-01-27 15:40 +0100
    Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to  work on both  Zynq and Microblaze Arnd Bergmann <arnd@arndb.de> - 2016-01-27 16:20 +0100

#1319031 — RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

> Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver
> to work on both Zynq and Microblaze
> 
> On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote:
> > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
> > Zynq and Microblaze Architectures.
> > With these modifications drivers/pci/host/pcie-xilinx.c, will work on
> > both Zynq and Microblaze Architectures.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> 
> I think this patch should be split into three, as you are doing three unrelated
> things here.
> 
Agreed, will send as different patches in next series.
> > ---
> > --- a/drivers/pci/host/pcie-xilinx.c
> > +++ b/drivers/pci/host/pcie-xilinx.c
> > @@ -92,7 +92,12 @@
> >  #define ECAM_DEV_NUM_SHIFT		12
> >
> >  /* Number of MSI IRQs */
> > -#define XILINX_NUM_MSI_IRQS		128
> > +#define XILINX_NUM_MSI_IRQS	128
> > +#ifdef CONFIG_ARM
> > +#define TOT_NR_IRQS		XILINX_NUM_MSI_IRQS
> > +#else
> > +#define TOT_NR_IRQS		(NR_IRQS + XILINX_NUM_MSI_IRQS)
> > +#endif
> 
> Something looks wrong here in the microblaze variant. What does NR_IRQS
> have to do with it?
> 
> > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int
> irq)
> >   */
> >  static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)  {
> > +	int irq;
> >  	int pos;
> >
> >  	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> > -	if (pos < XILINX_NUM_MSI_IRQS)
> > +	irq = pos;
> > +#ifdef CONFIG_MICROBLAZE
> > +	irq = XILINX_NUM_MSI_IRQS + pos;
> > +#endif
> 
> 
> 	if (IS_ENABLED(CONFIG_MICROBLAZE))
> 		irq = XILINX_NUM_MSI_IRQS + pos;
> 
Agreed.
> > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > platform_device *pdev)  #endif
> >  	pci_scan_child_bus(bus);
> >  	pci_assign_unassigned_bus_resources(bus);
> > +#ifdef CONFIG_ARM
> >  	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > +#endif
> >  	pci_bus_add_devices(bus);
> >  	platform_set_drvdata(pdev, port);
> 
> Here it looks like microblaze gets it right. I'm not sure why we still need the
> pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in
> common code.
In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately.

Bharat

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#1319063 — Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

On Wednesday 27 January 2016 14:33:45 Bharat Kumar Gogada wrote:
> > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct
> > > platform_device *pdev)  #endif
> > >     pci_scan_child_bus(bus);
> > >     pci_assign_unassigned_bus_resources(bus);
> > > +#ifdef CONFIG_ARM
> > >     pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> > > +#endif
> > >     pci_bus_add_devices(bus);
> > >     platform_set_drvdata(pdev, port);
> > 
> > Here it looks like microblaze gets it right. I'm not sure why we still need the
> > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in
> > common code.
> In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately.

But who calls it in microblaze? If it works without the extra call there,
can we make it work the same way for ARM?

	Arnd

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