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Re: [RFC PATCH v2] Add IPI entry for CPU UP

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  Re: [RFC PATCH v2] Add IPI entry for CPU UP Zhaoyang Huang <zhaoyang.huang@linaro.org> - 2016-01-21 09:50 +0100
    Re: [RFC PATCH v2] Add IPI entry for CPU UP Mark Rutland <mark.rutland@arm.com> - 2016-01-21 12:00 +0100
      Re: [RFC PATCH v2] Add IPI entry for CPU UP Zhaoyang Huang <zhaoyang.huang@linaro.org> - 2016-01-22 03:10 +0100
        Re: [RFC PATCH v2] Add IPI entry for CPU UP Marc Zyngier <marc.zyngier@arm.com> - 2016-01-22 09:10 +0100

#1314004 — Re: [RFC PATCH v2] Add IPI entry for CPU UP

Hi Mark,
Do you have any suggestion on how to sync the GIC operation from
kernel and psci parallelly? Thanks!

On 12 January 2016 at 19:51, Mark Rutland <mark.rutland@arm.com> wrote:
> On Tue, Jan 12, 2016 at 09:38:20AM +0000, Lorenzo Pieralisi wrote:
>> On Tue, Jan 12, 2016 at 10:17:42AM +0800, Zhaoyang Huang wrote:
>> > On 12 January 2016 at 10:05, Zhaoyang Huang <zhaoyang.huang@linaro.org> wrote:
>> > > In some ARM SOCs, IPI interrupt is used for hotplug in one cpu, that is,
>> > > sending a IPI to the core in WFI and powerdown status. So Add a IPI
>> > > entry for handle this kind of cpu up interrupt
>> > > Launching the IPI can be done within PSCI, while there will be one unknown
>> > > type of IPI as the dest core come up to the kernel world which will bring a
>> > > warning so far.So add such type of IPI to handle the interrupt.
>>
>> You missed CC'ing ALKML for the second time and you were warned.
>>
>> You are adding a call to *send* an IPI in the kernel so the commit
>> above is misleading.
>>
>> Acknowledge and clear the IRQ in FW so that the mechanism is completely
>> implemented in FW (ie PSCI), that the CPU coming out of reset will run
>> before getting to the kernel, this patch is not needed and we already
>> explained to you why.
>>
>> Lorenzo
>
> I would also suggest that FW used the set of SGIs reserved for secure
> usage (i.e. ID8 - ID15), as these will not conflict with those the
> kernel uses.
>
> Thanks,
> Mark.

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#1314104

On Thu, Jan 21, 2016 at 04:48:57PM +0800, Zhaoyang Huang wrote:
> Hi Mark,

Hi,

> Do you have any suggestion on how to sync the GIC operation from
> kernel and psci parallelly? Thanks!

I'm not sure what you mean. 

What problem are you having with synchronising GIC accesses?

As far as I can see, the CPU sending the IPI can simply poke the
relevant register in the distributor without requiring any
synchronisation. The CPU receiving the IPI is the only CPU with access
to its CPU interface.

Could you describe your problem in more detail?

Thanks,
Mark.

> On 12 January 2016 at 19:51, Mark Rutland <mark.rutland@arm.com> wrote:
> > On Tue, Jan 12, 2016 at 09:38:20AM +0000, Lorenzo Pieralisi wrote:
> >> On Tue, Jan 12, 2016 at 10:17:42AM +0800, Zhaoyang Huang wrote:
> >> > On 12 January 2016 at 10:05, Zhaoyang Huang <zhaoyang.huang@linaro.org> wrote:
> >> > > In some ARM SOCs, IPI interrupt is used for hotplug in one cpu, that is,
> >> > > sending a IPI to the core in WFI and powerdown status. So Add a IPI
> >> > > entry for handle this kind of cpu up interrupt
> >> > > Launching the IPI can be done within PSCI, while there will be one unknown
> >> > > type of IPI as the dest core come up to the kernel world which will bring a
> >> > > warning so far.So add such type of IPI to handle the interrupt.
> >>
> >> You missed CC'ing ALKML for the second time and you were warned.
> >>
> >> You are adding a call to *send* an IPI in the kernel so the commit
> >> above is misleading.
> >>
> >> Acknowledge and clear the IRQ in FW so that the mechanism is completely
> >> implemented in FW (ie PSCI), that the CPU coming out of reset will run
> >> before getting to the kernel, this patch is not needed and we already
> >> explained to you why.
> >>
> >> Lorenzo
> >
> > I would also suggest that FW used the set of SGIs reserved for secure
> > usage (i.e. ID8 - ID15), as these will not conflict with those the
> > kernel uses.
> >
> > Thanks,
> > Mark.
> 

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#1314711

On 21 January 2016 at 18:51, Mark Rutland <mark.rutland@arm.com> wrote:
> On Thu, Jan 21, 2016 at 04:48:57PM +0800, Zhaoyang Huang wrote:
>> Hi Mark,
>
> Hi,
>
>> Do you have any suggestion on how to sync the GIC operation from
>> kernel and psci parallelly? Thanks!
>
> I'm not sure what you mean.
>
> What problem are you having with synchronising GIC accesses?
>
> As far as I can see, the CPU sending the IPI can simply poke the
> relevant register in the distributor without requiring any
> synchronisation. The CPU receiving the IPI is the only CPU with access
> to its CPU interface.
>
> Could you describe your problem in more detail?
>
> Thanks,
> Mark.
>
Hi Mark,
Sorry for making confusions. I mean mutex between kernel and trustzone
when accessing
GIC registers. It is possible for they two issuing an accessing to the
same register at the
same time. How should I handle such kind of race conditions?

>> On 12 January 2016 at 19:51, Mark Rutland <mark.rutland@arm.com> wrote:
>> > On Tue, Jan 12, 2016 at 09:38:20AM +0000, Lorenzo Pieralisi wrote:
>> >> On Tue, Jan 12, 2016 at 10:17:42AM +0800, Zhaoyang Huang wrote:
>> >> > On 12 January 2016 at 10:05, Zhaoyang Huang <zhaoyang.huang@linaro.org> wrote:
>> >> > > In some ARM SOCs, IPI interrupt is used for hotplug in one cpu, that is,
>> >> > > sending a IPI to the core in WFI and powerdown status. So Add a IPI
>> >> > > entry for handle this kind of cpu up interrupt
>> >> > > Launching the IPI can be done within PSCI, while there will be one unknown
>> >> > > type of IPI as the dest core come up to the kernel world which will bring a
>> >> > > warning so far.So add such type of IPI to handle the interrupt.
>> >>
>> >> You missed CC'ing ALKML for the second time and you were warned.
>> >>
>> >> You are adding a call to *send* an IPI in the kernel so the commit
>> >> above is misleading.
>> >>
>> >> Acknowledge and clear the IRQ in FW so that the mechanism is completely
>> >> implemented in FW (ie PSCI), that the CPU coming out of reset will run
>> >> before getting to the kernel, this patch is not needed and we already
>> >> explained to you why.
>> >>
>> >> Lorenzo
>> >
>> > I would also suggest that FW used the set of SGIs reserved for secure
>> > usage (i.e. ID8 - ID15), as these will not conflict with those the
>> > kernel uses.
>> >
>> > Thanks,
>> > Mark.
>>

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#1314821

On Fri, 22 Jan 2016 10:01:24 +0800
Zhaoyang Huang <zhaoyang.huang@linaro.org> wrote:

> On 21 January 2016 at 18:51, Mark Rutland <mark.rutland@arm.com>
> wrote:
> > On Thu, Jan 21, 2016 at 04:48:57PM +0800, Zhaoyang Huang wrote:
> >> Hi Mark,
> >
> > Hi,
> >
> >> Do you have any suggestion on how to sync the GIC operation from
> >> kernel and psci parallelly? Thanks!
> >
> > I'm not sure what you mean.
> >
> > What problem are you having with synchronising GIC accesses?
> >
> > As far as I can see, the CPU sending the IPI can simply poke the
> > relevant register in the distributor without requiring any
> > synchronisation. The CPU receiving the IPI is the only CPU with
> > access to its CPU interface.
> >
> > Could you describe your problem in more detail?
> >
> > Thanks,
> > Mark.
> >
> Hi Mark,
> Sorry for making confusions. I mean mutex between kernel and trustzone
> when accessing
> GIC registers. It is possible for they two issuing an accessing to the
> same register at the
> same time. How should I handle such kind of race conditions?

The GIC programming interface is designed to allow this kind of access
without locking:

- CPU interface: the CPU cannot be in secure and non-secure at the same
  time, so there is no race for the access. Furthermore, the fact that
  secure interrupts have a higher priority than non-secure ones ensure
  that a secure interrupt will preempt a non-secure one, making the
  whole thing race free.

- Distributor: Writing to the GICD_SGIR register is atomic, and the GIC
  will ensure simultaneous access.

In a nutshell, there is no need to worry about these things, because
the GIC architecture has been designed from the ground up to support
this.

See for example this:
http://git.denx.de/?p=u-boot.git;a=blob_plain;f=arch/arm/cpu/armv7/sunxi/psci_sun7i.S;hb=HEAD

which uses IPIs to implement PSCI on an existing ARMv7 system.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.

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