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Re: [PATCH v15 0/6] altera fpga area and fpga bus

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  Re: [PATCH v15 0/6] altera fpga area and fpga bus Moritz Fischer <moritz.fischer@ettus.com> - 2016-01-21 10:50 +0100
    Re: [PATCH v15 0/6] altera fpga area and fpga bus Moritz Fischer <moritz.fischer@ettus.com> - 2016-01-21 21:40 +0100

#1314040 — Re: [PATCH v15 0/6] altera fpga area and fpga bus

Hi Alan,

On Wed, Jan 20, 2016 at 8:24 PM,  <atull@opensource.altera.com> wrote:
> From: Alan Tull <atull@opensource.altera.com>
>
> For v15, I'm not using the FPGA Manager as the bus.  I'm adding a FPGA Bus;
> the FPGA Manager and bridges go below it.
>
> I've gotten enough feedback that my proposals are Altera specific that I am
> going with that and changing the bindings to include an 'altr,' prefix.

I hope this wasn't a misunderstanding of one of my earlier remarks. I
think the fpga-area & fpga bus
parts do apply to to Xilinx FPGAs, too. I think for fpga-area and
fpga-bus we could drop the 'altr' prefix.

>
> I've combined the bindings document and the other Documentation/fpga/ document
> and done a rewrite there.

Looks great!

I'll test it on hardware and look at the patches individually,

Cheers,

Moritz

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#1314517

Hi Alan,

On Thu, Jan 21, 2016 at 5:42 PM, atull <atull@opensource.altera.com> wrote:

> If you want to send me a Xilinx example of usage for me to include in that
> document, that would be useful also.  I think you might have sent me
> something a while ago, but I can't find it now.

Will do. I'll clean up some of my examples with an in-tree driver and
get back to you.
Having more examples never hurts.

Cheers,

Moritz

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