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Groups > linux.kernel > #1311918 > unrolled thread
| Started by | Jiancheng Xue <xuejiancheng@huawei.com> |
|---|---|
| First post | 2016-01-19 04:00 +0100 |
| Last post | 2016-01-19 19:20 +0100 |
| Articles | 5 — 2 participants |
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[PATCH v6 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc. Jiancheng Xue <xuejiancheng@huawei.com> - 2016-01-19 04:00 +0100
[PATCH v6 6/6] ARM: dts: add dts files for Hi3519 Jiancheng Xue <xuejiancheng@huawei.com> - 2016-01-19 04:00 +0100
[PATCH v6 4/6] ARM: debug: add hi3519 debug uart Jiancheng Xue <xuejiancheng@huawei.com> - 2016-01-19 04:00 +0100
[PATCH v6 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue <xuejiancheng@huawei.com> - 2016-01-19 04:10 +0100
Re: [PATCH v6 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Rob Herring <robh@kernel.org> - 2016-01-19 19:20 +0100
| From | Jiancheng Xue <xuejiancheng@huawei.com> |
|---|---|
| Date | 2016-01-19 04:00 +0100 |
| Subject | [PATCH v6 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc. |
| Message-ID | <qSuGu-1nT-5@gated-at.bofh.it> |
Hello, Hi3519 soc is mainly used for ip camera and sport DV solutions. This patchset adds initial support for Hi3519 soc. It includes clock driver, arch configuration, debug uart configuration and device tree. It has been tested on hi3519 reference board. Any comments will be appreciated! Thanks! Change Log ---------- v6: -Change clock driver to a real platform driver v5: -Adjust clock and reset controller driver code v4: -Rebase to v4.4-rc7 -Divide patches according to Rob's comments -Add spi nodes in hi3519-demb.dts v3: -Rebase to v4.4-rc4 -Adjust according to Arnd's comments -Remove ARCH_HI3519, using ARCH_HISI directly v2: -Rebase to v4.4-rc3 -Put dt-binding doc and header file in a separate patch. -Delete unused clocks definitions. -Adjust the ARCH_xxx order in Kconfig file -Rename ARCH_HI3xxx to ARCH_36xx Jiancheng Xue (6): clk: hisilicon: add CRG driver for hi3519 soc ARM: hisi: add compatible string for Hi3519 soc ARM: config: hisi: enable CONFIG_RESET_CONTROLLER ARM: debug: add hi3519 debug uart ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl ARM: dts: add dts files for Hi3519 .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++ .../devicetree/bindings/clock/hi3519-crg.txt | 46 +++++ arch/arm/Kconfig.debug | 10 ++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3519-demb.dts | 42 +++++ arch/arm/boot/dts/hi3519.dtsi | 187 +++++++++++++++++++++ arch/arm/configs/hisi_defconfig | 1 + arch/arm/mach-hisi/hisilicon.c | 23 +-- drivers/clk/hisilicon/Kconfig | 7 + drivers/clk/hisilicon/Makefile | 2 + drivers/clk/hisilicon/clk-hi3519.c | 132 +++++++++++++++ drivers/clk/hisilicon/clk.c | 23 ++- drivers/clk/hisilicon/clk.h | 14 +- drivers/clk/hisilicon/reset.c | 130 ++++++++++++++ drivers/clk/hisilicon/reset.h | 32 ++++ include/dt-bindings/clock/hi3519-clock.h | 40 +++++ 16 files changed, 671 insertions(+), 34 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt create mode 100644 arch/arm/boot/dts/hi3519-demb.dts create mode 100644 arch/arm/boot/dts/hi3519.dtsi create mode 100644 drivers/clk/hisilicon/clk-hi3519.c create mode 100644 drivers/clk/hisilicon/reset.c create mode 100644 drivers/clk/hisilicon/reset.h create mode 100644 include/dt-bindings/clock/hi3519-clock.h -- 1.9.1
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| From | Jiancheng Xue <xuejiancheng@huawei.com> |
|---|---|
| Date | 2016-01-19 04:00 +0100 |
| Subject | [PATCH v6 6/6] ARM: dts: add dts files for Hi3519 |
| Message-ID | <qSuGu-1nT-19@gated-at.bofh.it> |
| In reply to | #1311918 |
add dts files for Hi3519
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/hi3519-demb.dts | 42 +++++++++
arch/arm/boot/dts/hi3519.dtsi | 187 ++++++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 arch/arm/boot/dts/hi3519-demb.dts
create mode 100644 arch/arm/boot/dts/hi3519.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..1ff3ed9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+ hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 0000000..6991ab6
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+ model = "HiSilicon HI3519 DEMO Board";
+ compatible = "hisilicon,hi3519";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&dual_timer0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 0000000..5729ecf
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+ };
+
+ clk_3m: clk_3m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+
+ crg: clock-reset-controller@12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ reg = <0x12010000 0x10000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ uart0: serial@12100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12100000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART0_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart1: serial@12101000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12101000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART1_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart2: serial@12102000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12102000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART2_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart3: serial@12103000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12103000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART3_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ uart4: serial@12104000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12104000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_UART4_CLK>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer0: timer@12000000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12000000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer1: timer@12001000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12001000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ dual_timer2: timer@12002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12002000 0x1000>;
+ clocks = <&clk_3m>;
+ clock-names = "apb_pclk";
+ status = "disable";
+ };
+
+ spi_bus0: spi@12120000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12120000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI0_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ spi_bus1: spi@12121000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12121000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI1_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ spi_bus2: spi@12122000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x12122000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HI3519_SPI2_CLK>;
+ clock-names = "apb_pclk";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
+ sysctrl: system-controller@12020000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12020000 0x1000>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysctrl>;
+ offset = <0x4>;
+ mask = <0xdeadbeef>;
+ };
+ };
+};
--
1.9.1
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| From | Jiancheng Xue <xuejiancheng@huawei.com> |
|---|---|
| Date | 2016-01-19 04:00 +0100 |
| Subject | [PATCH v6 4/6] ARM: debug: add hi3519 debug uart |
| Message-ID | <qSuGu-1nT-23@gated-at.bofh.it> |
| In reply to | #1311918 |
add hi3519 debug uart. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> --- arch/arm/Kconfig.debug | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 259c0ca..6d23073 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -270,6 +270,14 @@ choice Say Y here if you want the debug print routines to direct their output to the 8250 at PCI COM1. + config DEBUG_HI3519_UART + bool "Hisilicon Hi3519 Debug UART" + depends on ARCH_HISI + select DEBUG_UART_PL01X + help + Say Y here if you want kernel low-level debugging support + on HI3519 UART. + config DEBUG_HI3620_UART bool "Hisilicon HI3620 Debug UART" depends on ARCH_HI3xxx @@ -1392,6 +1400,7 @@ config DEBUG_UART_PHYS default 0x11002000 if DEBUG_MT8127_UART0 default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 + default 0x12100000 if DEBUG_HI3519_UART default 0x16000000 if ARCH_INTEGRATOR default 0x18000300 if DEBUG_BCM_5301X default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1553,6 +1562,7 @@ config DEBUG_UART_VIRT default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART default 0xfee82340 if ARCH_IOP13XX default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN + default 0xfef00000 if DEBUG_HI3519_UART default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 -- 1.9.1
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| From | Jiancheng Xue <xuejiancheng@huawei.com> |
|---|---|
| Date | 2016-01-19 04:10 +0100 |
| Subject | [PATCH v6 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl |
| Message-ID | <qSuQ9-1Gz-13@gated-at.bofh.it> |
| In reply to | #1311918 |
Add device tree bindings for Hi3519 system controller.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
new file mode 100644
index 0000000..115c5be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Required properties:
+- compatible: "hisilicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12010000 0x1000>;
+};
--
1.9.1
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-01-19 19:20 +0100 |
| Subject | Re: [PATCH v6 5/6] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl |
| Message-ID | <qSJ2O-36W-27@gated-at.bofh.it> |
| In reply to | #1311922 |
On Tue, Jan 19, 2016 at 10:38:30AM +0800, Jiancheng Xue wrote: > Add device tree bindings for Hi3519 system controller. > > Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> > --- > .../devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt Sorry to keep telling you different places, but I'd rather try to collect these in a common location (perhaps bindings/sysctrl). Leaving it here is fine for now. If you respin the series then please move it. Either way: Acked-by: Rob Herring <robh@kernel.org>
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