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[RFC 0/3] MT8173 CMDQ support

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  [RFC 0/3] MT8173 CMDQ support <hs.liao@mediatek.com> - 2016-01-20 06:20 +0100
    [RFC 2/3] arm64: dts: mt8173: Add GCE node <hs.liao@mediatek.com> - 2016-01-20 06:20 +0100

#1312882 — [RFC 0/3] MT8173 CMDQ support

Hi,

This is the first version to add Mediatek MT8173 Command Queue(CMDQ)
support. The CMDQ is used to help read/write registers with critical
time limitation, such as updating display configuration during the
vblank. It controls Global Command Engine (GCE) hardware to achieve
this requirement.

These patches have a build dependency on top of v4.4-rc1.

Best regards,
HS Liao

HS Liao (3):
  dt-bindings: soc: Add documentation for the MediaTek GCE unit
  arm64: dts: mt8173: Add GCE node
  CMDQ: Mediatek CMDQ driver

 .../devicetree/bindings/soc/mediatek/gce.txt       |   33 +
 arch/arm64/boot/dts/mediatek/mt8173.dtsi           |    8 +
 drivers/soc/mediatek/Kconfig                       |   10 +
 drivers/soc/mediatek/Makefile                      |    1 +
 drivers/soc/mediatek/mtk-cmdq.c                    | 3532 ++++++++++++++++++++
 include/soc/mediatek/cmdq.h                        |  225 ++
 6 files changed, 3809 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/gce.txt
 create mode 100644 drivers/soc/mediatek/mtk-cmdq.c
 create mode 100644 include/soc/mediatek/cmdq.h

-- 
1.7.9.5

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#1312883 — [RFC 2/3] arm64: dts: mt8173: Add GCE node

From: HS Liao <hs.liao@mediatek.com>

This patch adds the device node of the GCE hardware for CMDQ module.

Signed-off-by: HS Liao <hs.liao@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4dd5f93..4474e2f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -273,6 +273,14 @@
 			#clock-cells = <1>;
 		};
 
+		gce: gce@10212000 {
+			compatible = "mediatek,mt8173-gce";
+			reg = <0 0x10212000 0 0x1000>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		gic: interrupt-controller@10220000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
1.7.9.5

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