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Groups > linux.kernel > #1309387 > unrolled thread
| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2016-01-14 16:30 +0100 |
| Last post | 2016-01-19 16:40 +0100 |
| Articles | 12 on this page of 52 — 8 participants |
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[PATCH v2 00/26] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 03/26] clk: Add regmap support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 22/26] ARM: sun5i: r8: Add display blocks to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 20/26] drm: sun4i: tv: Add PAL output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 21/26] drm: sun4i: tv: Add NTSC output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
Re: [PATCH v2 10/26] ARM: sun5i: a13: Add display and TCON clocks Chen-Yu Tsai <wens@csie.org> - 2016-01-16 18:10 +0100
[PATCH v2 18/26] drm: sun4i: Add RGB output Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 23/26] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 11/26] ARM: sun5i: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
Re: [PATCH v2 11/26] ARM: sun5i: Add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2016-01-16 18:20 +0100
[PATCH v2 19/26] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 08/26] clk: sun5i: add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
Re: [PATCH v2 08/26] clk: sun5i: add DRAM gates Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
[PATCH v2 06/26] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
Re: [PATCH v2 06/26] clk: sunxi: Add PLL3 clock Chen-Yu Tsai <wens@csie.org> - 2016-01-16 17:10 +0100
[PATCH v2 04/26] clk: composite: Add unregister function Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:30 +0100
[PATCH v2 02/26] reset: Make reset_control_ops const Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 02/26] reset: Make reset_control_ops const Philipp Zabel <p.zabel@pengutronix.de> - 2016-01-15 17:00 +0100
[PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
Re: [PATCH v2 07/26] clk: sunxi: Add TCON channel1 clock Chen-Yu Tsai <wens@csie.org> - 2016-01-16 17:40 +0100
[PATCH v2 26/26] DO NOT MERGE: ARM: sun5i: chip: Enable the LCD panel Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
[PATCH v2 15/26] drm/modes: Support modes names on the command line Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
[PATCH v2 14/26] drm/modes: Rewrite the command line parser Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
[PATCH v2 17/26] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 17/26] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
[PATCH v2 12/26] ARM: sun5i: Add TV encoder gate to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 12/26] ARM: sun5i: Add TV encoder gate to the DTSI Chen-Yu Tsai <wens@csie.org> - 2016-01-16 18:20 +0100
[PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 25/26] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
[PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2016-01-15 00:20 +0100
Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Daniel Vetter <daniel@ffwll.ch> - 2016-01-15 11:20 +0100
Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2016-01-25 07:30 +0100
Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Daniel Vetter <daniel@ffwll.ch> - 2016-01-25 08:30 +0100
Re: [PATCH v2 13/26] drm/fb_cma_helper: Remove implicit call to disable_unused_functions Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2016-01-25 20:10 +0100
[PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Rob Herring <robh@kernel.org> - 2016-01-15 04:10 +0100
Re: [linux-sunxi] [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Priit Laes <plaes@plaes.org> - 2016-01-16 15:10 +0100
Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver Chen-Yu Tsai <wens@csie.org> - 2016-01-16 16:40 +0100
[PATCH v2 24/26] devicetree: Add olimex vendor prefix Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Rob Herring <robh@kernel.org> - 2016-01-15 04:20 +0100
Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Stefan Wahren <stefan.wahren@i2se.com> - 2016-01-15 07:50 +0100
Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-15 09:10 +0100
[PATCH v2 09/26] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:40 +0100
[PATCH v2 01/26] reset: Move DT cell size check to the core Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-14 16:50 +0100
Re: [PATCH v2 01/26] reset: Move DT cell size check to the core Philipp Zabel <p.zabel@pengutronix.de> - 2016-01-15 17:00 +0100
Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support Priit Laes <plaes@plaes.org> - 2016-01-16 16:20 +0100
Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support Priit Laes <plaes@plaes.org> - 2016-01-17 14:00 +0100
Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-19 16:40 +0100
Page 3 of 3 — ← Prev page 1 2 [3]
| From | Priit Laes <plaes@plaes.org> |
|---|---|
| Date | 2016-01-16 15:10 +0100 |
| Subject | Re: [linux-sunxi] [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver |
| Message-ID | <qRzIe-5mB-3@gated-at.bofh.it> |
| In reply to | #1309430 |
On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
> Add a driver to support both.
...
> +static void __init sun4i_a10_display_init(struct device_node *node,
> + struct sun4i_a10_display_clk_data *data)
> +{
> + const char *parents[data->parents];
> + const char *clk_name = node->name;
> + struct reset_data *reset_data;
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate;
> + struct clk_mux *mux;
> + void __iomem *reg;
> + struct clk *clk;
> + int i;
warning: unused variable 'i'
> +
> + of_property_read_string(node, "clock-output-names", &clk_name);
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n", clk_name);
> + return;
> + }
...
Thanks for working on this feature ;)
Päikest,
Priit Laes
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2016-01-16 16:40 +0100 |
| Subject | Re: [PATCH v2 05/26] clk: sunxi: Add display and TCON0 clocks driver |
| Message-ID | <qRB7k-67J-11@gated-at.bofh.it> |
| In reply to | #1309430 |
Hi,
On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A10 SoCs and its relatives has a special clock controller to drive the
> display engines (both frontend and backend), that have a lot in common with
> the clock to drive the first TCON channel.
>
> Add a driver to support both.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-sun4i-display.c | 241 ++++++++++++++++++++++
> 3 files changed, 244 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 8a47b77abfca..5360554a7d3f 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -55,6 +55,7 @@ Required properties:
> "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
> "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
> "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
> + "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
> "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
> "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
> "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
> @@ -64,6 +65,7 @@ Required properties:
> "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
> "allwinner,sun7i-a20-out-clk" - for the external output clocks
> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
> + "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
> "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
> "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index cb4c299214ce..a991cd8ca509 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
> obj-y += clk-a20-gmac.o
> obj-y += clk-mod0.o
> obj-y += clk-simple-gates.o
> +obj-y += clk-sun4i-display.o
> obj-y += clk-sun8i-mbus.o
> obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c
> new file mode 100644
> index 000000000000..9dc6894f0934
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -0,0 +1,241 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/kernel.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +struct sun4i_a10_display_clk_data {
> + bool has_div;
> + bool has_rst;
> + u8 parents;
> +
> + u8 offset_en;
> + u8 offset_div;
> + u8 offset_mux;
> + u8 offset_rst;
> +
> + u8 width_div;
> + u8 width_mux;
> +};
> +
> +struct reset_data {
> + void __iomem *reg;
> + spinlock_t *lock;
> + struct reset_controller_dev rcdev;
> + u8 offset;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_display_lock);
> +
> +static inline struct reset_data *rcdev_to_reset_data(struct reset_controller_dev *rcdev)
> +{
> + return container_of(rcdev, struct reset_data, rcdev);
> +};
> +
> +static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct reset_data *data = rcdev_to_reset_data(rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg & ~BIT(data->offset), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct reset_data *data = rcdev_to_reset_data(rcdev);
> + unsigned long flags;
> + u32 reg;
> +
> + spin_lock_irqsave(data->lock, flags);
> +
> + reg = readl(data->reg);
> + writel(reg | BIT(data->offset), data->reg);
> +
> + spin_unlock_irqrestore(data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct reset_data *data = rcdev_to_reset_data(rcdev);
> +
> + return !(readl(data->reg) & BIT(data->offset));
> +}
> +
> +static const struct reset_control_ops sun4i_a10_display_reset_ops = {
> + .assert = sun4i_a10_display_assert,
> + .deassert = sun4i_a10_display_deassert,
> + .status = sun4i_a10_display_status,
> +};
> +
> +static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *spec)
> +{
> + /* We only have a single reset signal */
> + return 0;
> +}
> +
> +static void __init sun4i_a10_display_init(struct device_node *node,
> + struct sun4i_a10_display_clk_data *data)
> +{
> + const char *parents[data->parents];
> + const char *clk_name = node->name;
> + struct reset_data *reset_data;
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate;
> + struct clk_mux *mux;
> + void __iomem *reg;
> + struct clk *clk;
> + int i;
> +
> + of_property_read_string(node, "clock-output-names", &clk_name);
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n", clk_name);
> + return;
> + }
> +
> + of_clk_parent_fill(node, parents, data->parents);
What if someone uses an incorrect DT that has less parents described?
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
> + return;
> +
> + mux->reg = reg;
> + mux->shift = data->offset_mux;
> + mux->mask = (1 << data->width_mux) - 1;
> + mux->lock = &sun4i_a10_display_lock;
> +
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto free_mux;
> +
> + gate->reg = reg;
> + gate->bit_idx = data->offset_en;
> + gate->lock = &sun4i_a10_display_lock;
> +
> + if (data->has_div) {
> + div = kzalloc(sizeof(*div), GFP_KERNEL);
> + if (!div)
> + goto free_gate;
> +
> + div->reg = reg;
> + div->shift = data->offset_div;
> + div->width = data->width_div;
> + div->lock = &sun4i_a10_display_lock;
> + }
> +
> + clk = clk_register_composite(NULL, clk_name,
> + parents, data->parents,
> + &mux->hw, &clk_mux_ops,
> + data->has_div ? &div->hw : NULL,
> + data->has_div ? &clk_divider_ops : NULL,
> + &gate->hw, &clk_gate_ops,
> + 0);
> + if (IS_ERR(clk)) {
> + pr_err("%s: Couldn't register the clock\n", clk_name);
> + goto free_div;
> + }
> +
> + of_clk_add_provider(node, of_clk_src_simple_get, clk);
Check for errors?
> +
> + if (!data->has_rst)
> + return;
> +
> + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
> + if (!reset_data)
> + goto free_clk;
> +
> + reset_data->reg = reg;
> + reset_data->offset = data->offset_rst;
> + reset_data->lock = &sun4i_a10_display_lock;
> + reset_data->rcdev.nr_resets = 1;
> + reset_data->rcdev.ops = &sun4i_a10_display_reset_ops;
> + reset_data->rcdev.of_node = node;
> + reset_data->rcdev.of_reset_n_cells = 0;
> + reset_data->rcdev.of_xlate = &sun4i_a10_display_reset_xlate;
> +
> + if (reset_controller_register(&reset_data->rcdev)) {
> + pr_err("%s: Couldn't register the reset controller\n",
> + clk_name);
> + goto free_reset;
> + }
> +
> + return;
> +
> +free_reset:
> + kfree(reset_data);
> +free_clk:
> + clk_unregister(clk);
> +free_div:
> + if (data->has_div)
> + kfree(div);
> +free_gate:
> + kfree(gate);
> +free_mux:
> + kfree(mux);
Cleanup after of_io_request_and_map()?
> +}
> +
> +static struct sun4i_a10_display_clk_data sun4i_a10_tcon_ch0_data = {
> + .has_rst = true,
> + .parents = 4,
> + .offset_en = 31,
> + .offset_rst = 29,
My datasheets (A10 v1.5, A20 v1.4), say bit 30 for LCD0 ch0 reset.
A13 and R8 manuals do not list this clock, but A10s does, which has
bit 30 for LCD reset and bit 29 for TV encoder reset.
I suggest changing has_rst to int, and for sun5i variant, have
has_rst = 2, reset_cells = 1, for 2 separate reset controls.
The tcon and tv encoder bits of the DTSI should be updated as
well.
I assume your tests work because U-boot already de-asserted the
resets (both if you're using composite output).
> + .offset_mux = 24,
> + .width_mux = 2,
> +};
> +
> +static void __init sun4i_a10_tcon_ch0_setup(struct device_node *node)
> +{
> + sun4i_a10_display_init(node, &sun4i_a10_tcon_ch0_data);
> +}
> +CLK_OF_DECLARE(sun4i_a10_tcon_ch0, "allwinner,sun4i-a10-tcon-ch0-clk",
> + sun4i_a10_tcon_ch0_setup);
> +
> +static struct sun4i_a10_display_clk_data sun4i_a10_display_data = {
> + .has_div = true,
Missing .has_rst = true.
> + .parents = 3,
> + .offset_en = 31,
> + .offset_rst = 30,
> + .offset_mux = 24,
> + .offset_div = 0,
This is already implied.
> + .width_mux = 2,
> + .width_div = 4,
> +};
> +
> +static void __init sun4i_a10_display_setup(struct device_node *node)
> +{
> + sun4i_a10_display_init(node, &sun4i_a10_display_data);
> +}
> +CLK_OF_DECLARE(sun4i_a10_display, "allwinner,sun4i-a10-display-clk",
> + sun4i_a10_display_setup);
> --
> 2.6.4
Thanks for working on this!
Regards
ChenYu
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-01-14 16:40 +0100 |
| Subject | [PATCH v2 24/26] devicetree: Add olimex vendor prefix |
| Message-ID | <qQSag-yO-69@gated-at.bofh.it> |
| In reply to | #1309387 |
Olimex is an open source hardware boards vendors based in Bulgaria. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 55df1d444e9f..de4eb72b3adc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -161,6 +161,7 @@ nuvoton Nuvoton Technology Corporation nvidia NVIDIA nxp NXP Semiconductors okaya Okaya Electric America, Inc. +olimex Olimex onnn ON Semiconductor Corp. opencores OpenCores.org option Option NV -- 2.6.4
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-01-15 04:20 +0100 |
| Subject | Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix |
| Message-ID | <qR35E-6Q-9@gated-at.bofh.it> |
| In reply to | #1309431 |
On Thu, Jan 14, 2016 at 04:25:07PM +0100, Maxime Ripard wrote: > Olimex is an open source hardware boards vendors based in Bulgaria. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org>
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| From | Stefan Wahren <stefan.wahren@i2se.com> |
|---|---|
| Date | 2016-01-15 07:50 +0100 |
| Subject | Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix |
| Message-ID | <qR6mR-2gY-1@gated-at.bofh.it> |
| In reply to | #1309847 |
> Rob Herring <robh@kernel.org> hat am 15. Januar 2016 um 04:15 geschrieben:
>
>
> On Thu, Jan 14, 2016 at 04:25:07PM +0100, Maxime Ripard wrote:
> > Olimex is an open source hardware boards vendors based in Bulgaria.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > 1 file changed, 1 insertion(+)
>
> Acked-by: Rob Herring <robh@kernel.org>
>
I don't think we need this twice.
It's already committed:
2193377bdade ("DT: add Olimex to vendor prefixes")
Regards
Stefan
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-01-15 09:10 +0100 |
| Subject | Re: [PATCH v2 24/26] devicetree: Add olimex vendor prefix |
| Message-ID | <qR7Ci-3ht-17@gated-at.bofh.it> |
| In reply to | #1309894 |
[Multipart message — attachments visible in raw view] — view raw
Hi,
On Fri, Jan 15, 2016 at 07:41:35AM +0100, Stefan Wahren wrote:
>
> > Rob Herring <robh@kernel.org> hat am 15. Januar 2016 um 04:15 geschrieben:
> >
> >
> > On Thu, Jan 14, 2016 at 04:25:07PM +0100, Maxime Ripard wrote:
> > > Olimex is an open source hardware boards vendors based in Bulgaria.
> > >
> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > > ---
> > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > > 1 file changed, 1 insertion(+)
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> >
>
> I don't think we need this twice.
>
> It's already committed:
>
> 2193377bdade ("DT: add Olimex to vendor prefixes")
Hmm, indeed.
Sorry for the noise, I'll drop the commit.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-01-14 16:40 +0100 |
| Subject | [PATCH v2 09/26] ARM: sun5i: dt: Add pll3 and pll7 clocks |
| Message-ID | <qQSag-yO-77@gated-at.bofh.it> |
| In reply to | #1309387 |
Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun5i.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 59a9426e3bd4..0840612b5ed6 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -88,6 +88,15 @@
clock-output-names = "osc24M";
};
+ osc3M: osc3M_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc3M";
+ };
+
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -112,6 +121,23 @@
"pll2-4x", "pll2-8x";
};
+ pll3: clk@01c20010 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20010 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll3";
+ };
+
+ pll3x2: pll3x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll3>;
+ clock-output-names = "pll3-2x";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +162,23 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
+ pll7: clk@01c20030 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20030 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll7";
+ };
+
+ pll7x2: pll7x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll7>;
+ clock-output-names = "pll7-2x";
+ };
+
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
--
2.6.4
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-01-14 16:50 +0100 |
| Subject | [PATCH v2 01/26] reset: Move DT cell size check to the core |
| Message-ID | <qQSjU-Dz-21@gated-at.bofh.it> |
| In reply to | #1309387 |
The core currently doesn't check that the DT cell size matches what the
driver declares, which means that every xlate function needs to duplicate
that check.
Make sure that of_reset_control_get checks for this to avoid duplication
and errors.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/reset/core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index 7955e00d04d4..d53b2b980bdd 100644
--- a/drivers/reset/core.c
+++ b/drivers/reset/core.c
@@ -46,9 +46,6 @@ struct reset_control {
static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
- if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
- return -EINVAL;
-
if (reset_spec->args[0] >= rcdev->nr_resets)
return -EINVAL;
@@ -182,6 +179,9 @@ struct reset_control *of_reset_control_get(struct device_node *node,
return ERR_PTR(-EPROBE_DEFER);
}
+ if (WARN_ON(args.args_count != rcdev->of_reset_n_cells))
+ return ERR_PTR(-EINVAL);
+
rstc_id = rcdev->of_xlate(rcdev, &args);
if (rstc_id < 0) {
mutex_unlock(&reset_controller_list_mutex);
--
2.6.4
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| From | Philipp Zabel <p.zabel@pengutronix.de> |
|---|---|
| Date | 2016-01-15 17:00 +0100 |
| Subject | Re: [PATCH v2 01/26] reset: Move DT cell size check to the core |
| Message-ID | <qReXa-8dT-35@gated-at.bofh.it> |
| In reply to | #1309440 |
Hi Maxime,
Am Donnerstag, den 14.01.2016, 16:24 +0100 schrieb Maxime Ripard:
> The core currently doesn't check that the DT cell size matches what the
> driver declares, which means that every xlate function needs to duplicate
> that check.
>
> Make sure that of_reset_control_get checks for this to avoid duplication
> and errors.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/reset/core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/reset/core.c b/drivers/reset/core.c
> index 7955e00d04d4..d53b2b980bdd 100644
> --- a/drivers/reset/core.c
> +++ b/drivers/reset/core.c
> @@ -46,9 +46,6 @@ struct reset_control {
> static int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
> const struct of_phandle_args *reset_spec)
> {
> - if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
> - return -EINVAL;
> -
> if (reset_spec->args[0] >= rcdev->nr_resets)
> return -EINVAL;
>
> @@ -182,6 +179,9 @@ struct reset_control *of_reset_control_get(struct device_node *node,
> return ERR_PTR(-EPROBE_DEFER);
> }
>
> + if (WARN_ON(args.args_count != rcdev->of_reset_n_cells))
> + return ERR_PTR(-EINVAL);
> +
Applied with this fix:
- if (WARN_ON(args.args_count != rcdev->of_reset_n_cells))
+ if (WARN_ON(args.args_count != rcdev->of_reset_n_cells)) {
+ mutex_unlock(&reset_controller_list_mutex);
return ERR_PTR(-EINVAL);
+ }
No further action needed if you agree, otherwise let me know and I'll
back it out.
best regards
Philipp
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| From | Priit Laes <plaes@plaes.org> |
|---|---|
| Date | 2016-01-16 16:20 +0100 |
| Subject | Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support |
| Message-ID | <qRANX-60x-1@gated-at.bofh.it> |
| In reply to | #1309387 |
On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The Allwinner A10 and subsequent SoCs share the same display pipeline, with
> variations in the number of controllers (1 or 2), or the presence or not of
> some output (HDMI, TV, VGA) or not.
>
> Add a driver with a limited set of features for now, and we will hopefully
> support all of them eventually
>
[..]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h
> b/drivers/gpu/drm/sun4i/sun4i_backend.h
> new file mode 100644
> index 000000000000..60f6a200fa73
> --- /dev/null
> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
> @@ -0,0 +1,160 @@
> +/*
> + * Copyright (C) 2015 Free Electrons
> + * Copyright (C) 2015 NextThing Co
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#ifndef _SUN4I_BACKEND_H_
> +#define _SUN4I_BACKEND_H_
> +
> +#include <linux/clk.h>
> +#include <linux/regmap.h>
> +
> +#define SUN4I_BACKEND_MODCTL_REG 0x800
> +#define SUN4I_BACKEND_MODCTL_LINE_SEL BIT(29)
> +#define SUN4I_BACKEND_MODCTL_ITLMOD_EN BIT(28
> )
> +#define SUN4I_BACKEND_MODCTL_OUT_SEL GENMASK(
> 22, 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_LCD
> (0 << 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_FE0
> (6 << 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_FE1
> (7 << 20)
> +#define SUN4I_BACKEND_MODCTL_HWC_EN BIT(16)
> +#define SUN4I_BACKEND_MODCTL_LAY_EN(l) BIT(8
> + l)
> +#define SUN4I_BACKEND_MODCTL_OCSC_EN BIT(5)
> +#define SUN4I_BACKEND_MODCTL_DFLK_EN BIT(4)
> +#define SUN4I_BACKEND_MODCTL_DLP_START_CTL BIT(2)
> +#define SUN4I_BACKEND_MODCTL_START_CTL BIT(1)
> +#define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
> +
> +#define SUN4I_BACKEND_BACKCOLOR_REG 0x804
> +#define SUN4I_BACKEND_BACKCOLOR(r, g, b) (((r) << 16)
> | ((g) << 8) | (b))
> +
> +#define SUN4I_BACKEND_DISSIZE_REG 0x808
> +#define SUN4I_BACKEND_DISSIZE(w, h) (((((h) -
> 1) & 0xffff) << 16) | \
> + (((w) - 1)
> & 0xffff))
> +
> +#define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) -
> 1) & 0x1fff) << 16) | \
> + (((w) - 1)
> & 0x1fff))
> +
> +#define SUN4I_BACKEND_LAYCOOR_REG(l) (0x820 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_LAYCOOR(x, y) ((((u32)(
> y) & 0xffff) << 16) | \
> + ((u32)(x) &
> 0xffff))
> +
> +#define SUN4I_BACKEND_LAYLINEWIDTH_REG(l) (0x840 + (0x4 *
> (l)))
> +
> +#define SUN4I_BACKEND_LAYFB_L32ADD_REG(l) (0x850 + (0x4 *
> (l)))
> +
> +#define SUN4I_BACKEND_LAYFB_H4ADD_REG 0x860
> +#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l) GENMASK(3 +
> ((l) * 8), 0)
> +#define SUN4I_BACKEND_LAYFB_H4ADD(l, val) ((v
> al) << ((l) * 8))
> +
> +#define SUN4I_BACKEND_REGBUFFCTL_REG 0x870
> +#define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS BIT(1)
> +#define SUN4I_BACKEND_REGBUFFCTL_LOADCTL BIT(0)
> +
> +#define SUN4I_BACKEND_CKMAX_REG 0x880
> +#define SUN4I_BACKEND_CKMIN_REG 0x884
> +#define SUN4I_BACKEND_CKCFG_REG 0x888
> +#define SUN4I_BACKEND_ATTCTL_REG0(l) (0x890 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK BIT(15)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x) ((x)
> << 15)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK GENMASK(11,
> 10)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)
> ((x) << 10)
> +
> +#define SUN4I_BACKEND_ATTCTL_REG1(l) (0x8a0 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT GENMASK
> (15, 14)
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT GENMASK
> (13, 12)
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT GENMASK(1
> 1, 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_1BPP
> (0 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_2BPP
> (1 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_4BPP
> (2 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_8BPP
> (3 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB655
> (4 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB565
> (5 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB556
> (6 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_ARGB1555 (7
> << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGBA5551 (8
> << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_XRGB8888 (9
> << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_ARGB8888 (10
> << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB888
> (11 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_ARGB4444 (12
> << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGBA4444 (13
> << 8)
> +
> +#define SUN4I_BACKEND_DLCDPCTL_REG 0x8b0
> +#define SUN4I_BACKEND_DLCDPFRMBUF_ADDRCTL_REG 0x8b4
> +#define SUN4I_BACKEND_DLCDPCOOR_REG0 0x8b8
> +#define SUN4I_BACKEND_DLCDPCOOR_REG1 0x8bc
> +
> +#define SUN4I_BACKEND_INT_EN_REG 0x8c0
> +#define SUN4I_BACKEND_INT_FLAG_REG 0x8c4
> +#define SUN4I_BACKEND_REG_LOAD_FINISHED BIT(1
> )
> +
> +#define SUN4I_BACKEND_HWCCTL_REG 0x8d8
> +#define SUN4I_BACKEND_HWCFBCTL_REG 0x8e0
> +#define SUN4I_BACKEND_WBCTL_REG 0x8f0
> +#define SUN4I_BACKEND_WBADD_REG 0x8f4
> +#define SUN4I_BACKEND_WBLINEWIDTH_REG 0x8f8
> +#define SUN4I_BACKEND_SPREN_REG 0x900
> +#define SUN4I_BACKEND_SPRFMTCTL_REG 0x908
> +#define SUN4I_BACKEND_SPRALPHACTL_REG 0x90c
> +#define SUN4I_BACKEND_IYUVCTL_REG 0x920
> +#define SUN4I_BACKEND_IYUVADD_REG(c) (0x930 + (0x4 *
> (c)))
> +#define SUN4I_BACKEND_IYUVLINEWITDTH_REG(c) (0x940 + (0x4 *
> (c)))
WITDTH ?
This isn't used anyway...
> +#define SUN4I_BACKEND_YGCOEF_REG(c) (0x950 + (0x4 *
> (c)))
> +#define SUN4I_BACKEND_YGCONS_REG 0x95c
> +#define SUN4I_BACKEND_URCOEF_REG(c) (0x960 + (0x4 *
> (c)))
> +#define SUN4I_BACKEND_URCONS_REG 0x96c
> +#define SUN4I_BACKEND_VBCOEF_REG(c) (0x970 + (0x4 *
> (c)))
> +#define SUN4I_BACKEND_VBCONS_REG 0x97c
> +#define SUN4I_BACKEND_KSCTL_REG 0x980
> +#define SUN4I_BACKEND_KSBKCOLOR_REG 0x984
> +#define SUN4I_BACKEND_KSFSTLINEWIDTH_REG 0x988
> +#define SUN4I_BACKEND_KSVSCAFCT_REG 0x98c
> +#define SUN4I_BACKEND_KSHSCACOEF_REG(x) (0x9a0 + (0x4
> * (x)))
> +#define SUN4I_BACKEND_OCCTL_REG 0x9c0
> +#define SUN4I_BACKEND_OCCTL_ENABLE BIT(0)
> +
> +#define SUN4I_BACKEND_OCRCOEF_REG(x) (0x9d0 + (0x4 *
> (x)))
> +#define SUN4I_BACKEND_OCRCONS_REG 0x9dc
> +#define SUN4I_BACKEND_OCGCOEF_REG(x) (0x9e0 + (0x4 *
> (x)))
> +#define SUN4I_BACKEND_OCGCONS_REG 0x9ec
> +#define SUN4I_BACKEND_OCBCOEF_REG(x) (0x9f0 + (0x4 *
> (x)))
> +#define SUN4I_BACKEND_OCBCONS_REG 0x9fc
> +#define SUN4I_BACKEND_SPRCOORCTL_REG(s) (0xa00 + (0x4
> * (s)))
> +#define SUN4I_BACKEND_SPRATTCTL_REG(s) (0xb00 + (0x4
> * (s)))
> +#define SUN4I_BACKEND_SPRADD_REG(s) (0xc00 + (0x4 *
> (s)))
> +#define SUN4I_BACKEND_SPRLINEWIDTH_REG(s) (0xd00 + (0x4 *
> (s)))
> +
> +#define SUN4I_BACKEND_SPRPALTAB_OFF 0x4000
> +#define SUN4I_BACKEND_GAMMATAB_OFF 0x4400
> +#define SUN4I_BACKEND_HWCPATTERN_OFF 0x4800
> +#define SUN4I_BACKEND_HWCCOLORTAB_OFF 0x4c00
> +#define SUN4I_BACKEND_PIPE_OFF(p) (0x5000 + (0x400 *
> (p)))
> +
> +struct sun4i_backend {
> + struct regmap *regs;
> +
> + struct clk *bus_clk;
> + struct clk *mod_clk;
> + struct clk *ram_clk;
> +};
> +
> +void sun4i_backend_apply_color_correction(struct sun4i_backend
> *backend);
> +void sun4i_backend_commit(struct sun4i_backend *backend);
> +
> +void sun4i_backend_layer_enable(struct sun4i_backend *backend,
> + int layer, bool enable);
> +int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
> + int layer, struct drm_plane
> *plane);
> +int sun4i_backend_update_layer_formats(struct sun4i_backend
> *backend,
> + int layer, struct drm_plane
> *plane);
> +int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
> + int layer, struct drm_plane
> *plane);
> +
> +#endif /* _SUN4I_BACKEND_H_ */
>
[...]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
> b/drivers/gpu/drm/sun4i/sun4i_drv.c
> new file mode 100644
> index 000000000000..cc7dedc5d256
> --- /dev/null
> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
> @@ -0,0 +1,325 @@
> +/*
> + * Copyright (C) 2015 Free Electrons
> + * Copyright (C) 2015 NextThing Co
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/component.h>
> +#include <linux/of_graph.h>
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "sun4i_crtc.h"
> +#include "sun4i_drv.h"
> +#include "sun4i_framebuffer.h"
> +#include "sun4i_layer.h"
> +#include "sun4i_tcon.h"
[...]
> +static struct drm_driver sun4i_drv_driver = {
> + .driver_features = DRIVER_GEM | DRIVER_MODESET |
> DRIVER_PRIME | DRIVER_ATOMIC,
> +
> + /* Generic Operations */
> + .fops = &sun4i_drv_fops,
> + .name = "sun4i-drm",
> + .desc = "Allwinner sun4i Display
> Engine",
> + .date = "20150629",
2016something ?
> + .major = 1,
> + .minor = 0,
> +
> + /* GEM Operations */
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .gem_free_object = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> +
> + /* PRIME Operations */
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_get_sg_table =
> drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table =
> drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> +
> + /* Frame Buffer Operations */
> +
> + /* VBlank Operations */
> + .get_vblank_counter = drm_vblank_count,
> + .enable_vblank = sun4i_drv_enable_vblank,
> + .disable_vblank = sun4i_drv_disable_vblank,
> +};
> +
[...]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> new file mode 100644
> index 000000000000..68072b8cddab
> --- /dev/null
> +++ b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> @@ -0,0 +1,54 @@
> +/*
> + * Copyright (C) 2015 Free Electrons
> + * Copyright (C) 2015 NextThing Co
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drmP.h>
> +
> +#include "sun4i_drv.h"
> +
> +static void sun4i_de_output_poll_changed(struct drm_device *drm)
> +{
> + struct sun4i_drv *drv = drm->dev_private;
> +
> + if (drv->fbdev)
> + drm_fbdev_cma_hotplug_event(drv->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs sun4i_de_mode_config_funcs
> = {
> + .output_poll_changed = sun4i_de_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> + .fb_create = drm_fb_cma_create,
> +};
> +
> +struct drm_fbdev_cma *sun4i_framebuffer_init(struct drm_device *drm)
> +{
> + drm_mode_config_reset(drm);
> +
> + drm->mode_config.max_width = 8192;
> + drm->mode_config.max_height = 8192;
Shouldn't these be 1920 x 1080 as per A10 User manual?
> +
> + drm->mode_config.funcs = &sun4i_de_mode_config_funcs;
> +
> + return drm_fbdev_cma_init(drm, 32,
> + drm->mode_config.num_crtc,
> + drm->mode_config.num_connector);
> +}
> +
> +void sun4i_framebuffer_free(struct drm_device *drm)
> +{
> + struct sun4i_drv *drv = drm->dev_private;
> +
> + drm_fbdev_cma_fini(drv->fbdev);
> + drm_mode_config_cleanup(drm);
> +}
[...]
Päikest,
Priit Laes :)
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| From | Priit Laes <plaes@plaes.org> |
|---|---|
| Date | 2016-01-17 14:00 +0100 |
| Subject | Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support |
| Message-ID | <qRV62-2zR-1@gated-at.bofh.it> |
| In reply to | #1310965 |
On Sat, 2016-01-16 at 17:11 +0200, Priit Laes wrote:
> On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> > The Allwinner A10 and subsequent SoCs share the same display
> > pipeline, with
> > variations in the number of controllers (1 or 2), or the presence
> > or not of
> > some output (HDMI, TV, VGA) or not.
[...]
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> > b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> > new file mode 100644
> > index 000000000000..68072b8cddab
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
> > @@ -0,0 +1,54 @@
> > +/*
> > + * Copyright (C) 2015 Free Electrons
> > + * Copyright (C) 2015 NextThing Co
> > + *
> > + * Maxime Ripard <maxime.ripard@free-electrons.com>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + */
> > +
> > +#include <drm/drm_fb_cma_helper.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drmP.h>
> > +
> > +#include "sun4i_drv.h"
> > +
> > +static void sun4i_de_output_poll_changed(struct drm_device *drm)
> > +{
> > + struct sun4i_drv *drv = drm->dev_private;
> > +
> > + if (drv->fbdev)
> > + drm_fbdev_cma_hotplug_event(drv->fbdev);
> > +}
> > +
> > +static const struct drm_mode_config_funcs
> > sun4i_de_mode_config_funcs
> > = {
> > + .output_poll_changed =
> > sun4i_de_output_poll_changed,
> > + .atomic_check = drm_atomic_helper_check,
> > + .atomic_commit = drm_atomic_helper_commit,
> > + .fb_create = drm_fb_cma_create,
> > +};
> > +
> > +struct drm_fbdev_cma *sun4i_framebuffer_init(struct drm_device
> > *drm)
> > +{
> > + drm_mode_config_reset(drm);
> > +
> > + drm->mode_config.max_width = 8192;
> > + drm->mode_config.max_height = 8192;
>
> Shouldn't these be 1920 x 1080 as per A10 User manual?
I was wrong here. 8192x8192 it is.
>
Päikest,
Priit Laes :)
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-01-19 16:40 +0100 |
| Subject | Re: [linux-sunxi] [PATCH v2 16/26] drm: Add Allwinner A10 Display Engine support |
| Message-ID | <qSGxY-1lu-21@gated-at.bofh.it> |
| In reply to | #1310965 |
[Multipart message — attachments visible in raw view] — view raw
Hi,
On Sat, Jan 16, 2016 at 05:11:44PM +0200, Priit Laes wrote:
> > +struct drm_fbdev_cma *sun4i_framebuffer_init(struct drm_device *drm)
> > +{
> > + drm_mode_config_reset(drm);
> > +
> > + drm->mode_config.max_width = 8192;
> > + drm->mode_config.max_height = 8192;
>
> Shouldn't these be 1920 x 1080 as per A10 User manual?
1080p is what the SoC can output. However, to create its output, it
uses a combination of planes of 8192x8192, that you'll obviously have
to crop. This is the size of the plane that we are exposing here, not
what we can output (which is listed in the various connectors).
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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