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[PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec

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  [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-01-16 00:50 +0100
    [PATCH V2 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2016-01-16 00:50 +0100
    Re: [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec Borislav Petkov <bp@alien8.de> - 2016-01-16 17:10 +0100

#1310534 — [PATCH V2 0/5] Updates to AMD MCE driver per Scalable MCA spec

The patchset contains updates to the MCE driver based
on the Scalable MCA specification.

Patches 1-3 include some minor changes to existing code
and have been tested for regressions on older families.

Patches 4-5 is new code and only runs on processors
with ScalableMCA feature enabled (for future)

Patch 1: Order of mce_amd_feature_init() was incorrect as
	 it should be called after we gather features from
	 cpuid bits. Fixing that in this patch
Patch 2: We do not require shared bank verification on ZP.
	 Modifying code here to return early if we are on a processor
	 that supports SMCA feature.
Patch 3: The number of blocks per bank is reduced from Fam17h onwards.
	 Fixing code to reflect this architectural change
Patch 4: LVT offset for thresholding is now programmed in different MSR
	 as opposed to per-bank MISC register in earlier processors.
	 Fixing code here to obtain LVT offset from correct MSR.
Patch 5: OS is required to set MCAXEn bit in the per-bank CONFIG MSR
	 to acknowledge the use of new MSR range for MCA.
	 Doing that here and also creating definitions for the new
	 MSR range in msr-index.

Changes in V2 (per Boris)
  - Include only definitions on header file that we are using here
  - Add comments around macros that belong to SMCA

Aravind Gopalakrishnan (5):
  x86, mce: Fix order of AMD MCE init function call
  x86/mcheck/AMD: Do not perform shared bank check for future processors
  x86/mcheck/AMD: Reduce number of blocks scanned per bank
  x86/mcheck/AMD: Fix LVT offset configuration for thresholding
  x86/mcheck/AMD: Set MCAX Enable bit

 arch/x86/include/asm/msr-index.h     |  5 +++
 arch/x86/kernel/cpu/mcheck/mce.c     |  2 +-
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 63 ++++++++++++++++++++++++++++++++++--
 3 files changed, 67 insertions(+), 3 deletions(-)

-- 
2.7.0

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#1310535 — [PATCH V2 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank

From Fam17h onwards, the number of extended MISC register
blocks is reduced to 4. It is an architectural change
from what we had on earlier processors.

Changing the value of NRBLOCKS here to reflect that change.

Although theoritically the total number of extended MCx_MISC
registers was 8 in earlier processor families, in practice
we only had to use the extra registers for MC4. And only 2 of
those were used. So this change does not affect older processors.
Tested it on Fam10h, Fam15h systems and works fine.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index da570a8..e650fdc 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,7 +28,7 @@
 #include <asm/msr.h>
 #include <asm/trace/irq_vectors.h>
 
-#define NR_BLOCKS         9
+#define NR_BLOCKS         5
 #define THRESHOLD_MAX     0xFFF
 #define INT_TYPE_APIC     0x00020000
 #define MASK_VALID_HI     0x80000000
-- 
2.7.0

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#1310986

On Fri, Jan 15, 2016 at 05:50:31PM -0600, Aravind Gopalakrishnan wrote:
> The patchset contains updates to the MCE driver based
> on the Scalable MCA specification.

Applied and pushed here:

http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=tip-ras

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

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