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Re: [PATCH V4 09/16] soc: tegra: pmc: Ensure partitions can be toggled on/off by PMC

Started byThierry Reding <thierry.reding@gmail.com>
First post2016-01-14 15:20 +0100
Last post2016-01-15 10:40 +0100
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  Re: [PATCH V4 09/16] soc: tegra: pmc: Ensure partitions can be  toggled on/off by PMC Thierry Reding <thierry.reding@gmail.com> - 2016-01-14 15:20 +0100
    Re: [PATCH V4 09/16] soc: tegra: pmc: Ensure partitions can be  toggled on/off by PMC Jon Hunter <jonathanh@nvidia.com> - 2016-01-15 10:40 +0100

#1309307 — Re: [PATCH V4 09/16] soc: tegra: pmc: Ensure partitions can be toggled on/off by PMC

FromThierry Reding <thierry.reding@gmail.com>
Date2016-01-14 15:20 +0100
SubjectRe: [PATCH V4 09/16] soc: tegra: pmc: Ensure partitions can be toggled on/off by PMC
Message-ID<qQQUO-8fS-17@gated-at.bofh.it>

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On Fri, Dec 04, 2015 at 02:57:10PM +0000, Jon Hunter wrote:
> For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off
> via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the
> partition is simply powered up and down via an external regulator.
> Describe in the PMC SoC data in which devices the GPU partition can be
> controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that
> no one can incorrectly try to toggle the GPU partition via the
> APBDEV_PMC_PWRGATE_TOGGLE_0 register.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

The TRM doesn't mention anything like this. Will this be updated in the
TRM as well?

Thierry

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#1309995

FromJon Hunter <jonathanh@nvidia.com>
Date2016-01-15 10:40 +0100
Message-ID<qR91o-49P-21@gated-at.bofh.it>
In reply to#1309307
On 14/01/16 14:14, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Fri, Dec 04, 2015 at 02:57:10PM +0000, Jon Hunter wrote:
>> For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off
>> via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the
>> partition is simply powered up and down via an external regulator.
>> Describe in the PMC SoC data in which devices the GPU partition can be
>> controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that
>> no one can incorrectly try to toggle the GPU partition via the
>> APBDEV_PMC_PWRGATE_TOGGLE_0 register.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  drivers/soc/tegra/pmc.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
> 
> The TRM doesn't mention anything like this. Will this be updated in the
> TRM as well?

For T210, I have requested that the partitions are updated. Looks like
the powergate sequencing information for T210 is still missing from the
TRM. I can request that this is added. I will make a note for T124 as
well as it is missing.

Cheers
Jon

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