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Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit

Started byThierry Reding <thierry.reding@gmail.com>
First post2016-01-13 17:10 +0100
Last post2016-01-13 17:30 +0100
Articles 5 — 3 participants

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  Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 17:10 +0100
    Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Rhyland Klein <rklein@nvidia.com> - 2016-01-13 17:20 +0100
      Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 17:20 +0100
        Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Rhyland Klein <rklein@nvidia.com> - 2016-01-13 17:30 +0100
    Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit Jon Hunter <jonathanh@nvidia.com> - 2016-01-13 17:30 +0100

#1308542 — Re: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit

FromThierry Reding <thierry.reding@gmail.com>
Date2016-01-13 17:10 +0100
SubjectRe: [PATCH 2/2] clk: tegra: Use definition for pll_u override bit
Message-ID<qQw9I-2at-25@gated-at.bofh.it>

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On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> the code directly uses the bit number. Therefore, use the definition,
> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 791215747863..6f043c5e2394 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>  
>  	/* PLLU_VCO */
>  	val = readl(clk_base + pll_u_vco_params.base_reg);
> -	val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> +	val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>  	writel(val, clk_base + pll_u_vco_params.base_reg);
>  
>  	clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,

I think the comment is now redundant, given that the code says pretty
much the same thing. No need to respin for that, I can remove the
comment when I apply the patch. That is, unless anyone feels strongly
about keeping the comment.

Thierry

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#1308549

FromRhyland Klein <rklein@nvidia.com>
Date2016-01-13 17:20 +0100
Message-ID<qQwjn-2ek-3@gated-at.bofh.it>
In reply to#1308542
On 1/13/2016 11:08 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  drivers/clk/tegra/clk-tegra210.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>  
>>  	/* PLLU_VCO */
>>  	val = readl(clk_base + pll_u_vco_params.base_reg);
>> -	val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> +	val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>>  	writel(val, clk_base + pll_u_vco_params.base_reg);
>>  
>>  	clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
> 
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.

I agree its redundant. If I am going to post a new version to address
other concerns, I can just roll this in while doing so.

-rhyland


-- 
nvpublic

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#1308559

FromThierry Reding <thierry.reding@gmail.com>
Date2016-01-13 17:20 +0100
Message-ID<qQwjo-2ek-29@gated-at.bofh.it>
In reply to#1308549

[Multipart message — attachments visible in raw view] — view raw

On Wed, Jan 13, 2016 at 11:10:53AM -0500, Rhyland Klein wrote:
> On 1/13/2016 11:08 AM, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
> >> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
> >> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
> >> the code directly uses the bit number. Therefore, use the definition,
> >> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
> >>
> >> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> >> ---
> >>  drivers/clk/tegra/clk-tegra210.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> >> index 791215747863..6f043c5e2394 100644
> >> --- a/drivers/clk/tegra/clk-tegra210.c
> >> +++ b/drivers/clk/tegra/clk-tegra210.c
> >> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
> >>  
> >>  	/* PLLU_VCO */
> >>  	val = readl(clk_base + pll_u_vco_params.base_reg);
> >> -	val &= ~BIT(24); /* disable PLLU_OVERRIDE */
> >> +	val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
> >>  	writel(val, clk_base + pll_u_vco_params.base_reg);
> >>  
> >>  	clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
> > 
> > I think the comment is now redundant, given that the code says pretty
> > much the same thing. No need to respin for that, I can remove the
> > comment when I apply the patch. That is, unless anyone feels strongly
> > about keeping the comment.
> 
> I agree its redundant. If I am going to post a new version to address
> other concerns, I can just roll this in while doing so.

This looks like a good fix, or cleanup, on its own. So no need for
anyone to carry this forward, I can pick it up into a fixes branch
for v4.5.

Thierry

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#1308574

FromRhyland Klein <rklein@nvidia.com>
Date2016-01-13 17:30 +0100
Message-ID<qQwt6-2jv-43@gated-at.bofh.it>
In reply to#1308559
On 1/13/2016 11:19 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Wed, Jan 13, 2016 at 11:10:53AM -0500, Rhyland Klein wrote:
>> On 1/13/2016 11:08 AM, Thierry Reding wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>>>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>>>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>>>> the code directly uses the bit number. Therefore, use the definition,
>>>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>>>
>>>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>>>> ---
>>>>  drivers/clk/tegra/clk-tegra210.c | 2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>> index 791215747863..6f043c5e2394 100644
>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>>>  
>>>>  	/* PLLU_VCO */
>>>>  	val = readl(clk_base + pll_u_vco_params.base_reg);
>>>> -	val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>>>> +	val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>>>>  	writel(val, clk_base + pll_u_vco_params.base_reg);
>>>>  
>>>>  	clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
>>>
>>> I think the comment is now redundant, given that the code says pretty
>>> much the same thing. No need to respin for that, I can remove the
>>> comment when I apply the patch. That is, unless anyone feels strongly
>>> about keeping the comment.
>>
>> I agree its redundant. If I am going to post a new version to address
>> other concerns, I can just roll this in while doing so.
> 
> This looks like a good fix, or cleanup, on its own. So no need for
> anyone to carry this forward, I can pick it up into a fixes branch
> for v4.5.
> 

Sure thing.

Thanks,
Rhyland


-- 
nvpublic

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#1308573

FromJon Hunter <jonathanh@nvidia.com>
Date2016-01-13 17:30 +0100
Message-ID<qQwt6-2jv-51@gated-at.bofh.it>
In reply to#1308542
On 13/01/16 16:08, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Dec 21, 2015 at 12:56:32PM +0000, Jon Hunter wrote:
>> The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
>> but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
>> the code directly uses the bit number. Therefore, use the definition,
>> PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  drivers/clk/tegra/clk-tegra210.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>> index 791215747863..6f043c5e2394 100644
>> --- a/drivers/clk/tegra/clk-tegra210.c
>> +++ b/drivers/clk/tegra/clk-tegra210.c
>> @@ -2520,7 +2520,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>>  
>>  	/* PLLU_VCO */
>>  	val = readl(clk_base + pll_u_vco_params.base_reg);
>> -	val &= ~BIT(24); /* disable PLLU_OVERRIDE */
>> +	val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
>>  	writel(val, clk_base + pll_u_vco_params.base_reg);
>>  
>>  	clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
> 
> I think the comment is now redundant, given that the code says pretty
> much the same thing. No need to respin for that, I can remove the
> comment when I apply the patch. That is, unless anyone feels strongly
> about keeping the comment.

Fine with me. Thanks.

Jon

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