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[PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

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  [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY. Subbaraya Sundeep Bhatta <subbaraya.sundeep.bhatta@xilinx.com> - 2016-01-13 15:30 +0100
    Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY. Sören Brinkmann <soren.brinkmann@xilinx.com> - 2016-01-13 16:40 +0100
    Re: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY. Rob Herring <robh@kernel.org> - 2016-01-15 03:20 +0100

#1308455 — [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY.

This patch adds the document describing dt bindings for ZynqMP
PHY. ZynqMP SOC has a High Speed Processing System Gigabit
Transceiver which provides PHY capabilties to USB, SATA,
PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
---
 v2:
	modified to use phy cells as 2.

 .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
new file mode 100644
index 0000000..975cf21
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
@@ -0,0 +1,103 @@
+Xilinx ZynqMP PHY binding
+
+This binding describes a ZynqMP PHY device that is used to control ZynqMP
+High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
+and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.
+
+Required properties (controller (parent) node):
+- compatible    : Should be "xlnx,zynqmp-psgtr"
+
+- reg		: Address and length of register sets for each device in
+		  "reg-names"
+- reg-names     : The names of the register addresses corresponding to the
+		  registers filled in "reg":
+			- serdes: SERDES block register set
+			- siou: SIOU block register set
+			- lpd: Low power domain peripherals reset control
+			- fpd: Full power domain peripherals reset control
+
+-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
+			  termination resistance can be out of spec due to a
+			  bug in the calibration logic. This issue will be fixed
+			  in silicon in future versions.
+
+Required nodes	:  A sub-node is required for each lane the controller
+		   provides.
+
+Required properties (port (child) nodes):
+lane0:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 0>
+			- <PHY_TYPE_SATA 0>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 1>
+			- <PHY_TYPE_SGMII 0>
+lane1:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 1>
+			- <PHY_TYPE_SATA 1>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 0>
+			- <PHY_TYPE_SGMII 1>
+lane2:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 2>
+			- <PHY_TYPE_SATA 0>
+			- <PHY_TYPE_USB3 0>
+			- <PHY_TYPE_DP 1>
+			- <PHY_TYPE_SGMII 2>
+lane3:
+- #phy-cells	: Should be 2
+		  Cell after port phandle is device type from:
+			- <PHY_TYPE_PCIE 3>
+			- <PHY_TYPE_SATA 1>
+			- <PHY_TYPE_USB3 1>
+			- <PHY_TYPE_DP 0>
+			- <PHY_TYPE_SGMII 3>
+
+Example:
+	zynqmp_phy@fd400000 {
+		compatible = "xlnx,zynqmp-psgtr";
+		status = "okay";
+		reg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>,
+			<0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>;
+		reg-names = "serdes", "siou", "fpd", "lpd";
+
+		lane0: lane@0 {
+			#phy-cells = <2>;
+		};
+		lane1: lane@1 {
+			#phy-cells = <2>;
+		};
+		lane2: lane@2 {
+			#phy-cells = <2>;
+		};
+		lane3: lane@3 {
+			#phy-cells = <2>;
+		};
+	};
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+	usb@fe200000 {
+		...
+		phys	  = <&lane2 PHY_TYPE_USB3 0>;
+		...
+	};
+
+	ahci@fd0c0000 {
+		...
+		phys	  = <&lane3 PHY_TYPE_SATA 1>;
+		...
+	};
-- 
2.1.2

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#1308517

On Wed, 2016-01-13 at 07:43PM +0530, Subbaraya Sundeep Bhatta wrote:
> This patch adds the document describing dt bindings for ZynqMP
> PHY. ZynqMP SOC has a High Speed Processing System Gigabit
> Transceiver which provides PHY capabilties to USB, SATA,
> PCIE, Display Port and Ehernet SGMII controllers.
> 
> Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>

I missed the v2 hence again.

> ---
>  v2:
> 	modified to use phy cells as 2.
> 
>  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> new file mode 100644
> index 0000000..975cf21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> @@ -0,0 +1,103 @@
> +Xilinx ZynqMP PHY binding
> +
> +This binding describes a ZynqMP PHY device that is used to control ZynqMP
> +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
> +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.
> +
> +Required properties (controller (parent) node):
> +- compatible    : Should be "xlnx,zynqmp-psgtr"
> +
> +- reg		: Address and length of register sets for each device in
> +		  "reg-names"
> +- reg-names     : The names of the register addresses corresponding to the
> +		  registers filled in "reg":
> +			- serdes: SERDES block register set
> +			- siou: SIOU block register set
> +			- lpd: Low power domain peripherals reset control
> +			- fpd: Full power domain peripherals reset control

The reset registers should not be directly modified by Linux. Any access
to resets is likely requiring a reset controller that uses platform FW
to modify the resets.
> +
> +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> +			  termination resistance can be out of spec due to a
> +			  bug in the calibration logic. This issue will be fixed
> +			  in silicon in future versions.

The silicon version is run-time detectable. There should be a way to get
away without this property.

	Sören

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#1309816

On Wed, Jan 13, 2016 at 07:43:24PM +0530, Subbaraya Sundeep Bhatta wrote:
> This patch adds the document describing dt bindings for ZynqMP
> PHY. ZynqMP SOC has a High Speed Processing System Gigabit
> Transceiver which provides PHY capabilties to USB, SATA,
> PCIE, Display Port and Ehernet SGMII controllers.
> 
> Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com>
> ---
>  v2:
> 	modified to use phy cells as 2.
> 
>  .../devicetree/bindings/phy/phy-zynqmp.txt         | 103 +++++++++++++++++++++
>  1 file changed, 103 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> new file mode 100644
> index 0000000..975cf21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
> @@ -0,0 +1,103 @@
> +Xilinx ZynqMP PHY binding
> +
> +This binding describes a ZynqMP PHY device that is used to control ZynqMP
> +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes
> +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers.

s/SGMMI/SGMII/ 

> +
> +Required properties (controller (parent) node):
> +- compatible    : Should be "xlnx,zynqmp-psgtr"
> +
> +- reg		: Address and length of register sets for each device in
> +		  "reg-names"
> +- reg-names     : The names of the register addresses corresponding to the
> +		  registers filled in "reg":
> +			- serdes: SERDES block register set
> +			- siou: SIOU block register set
> +			- lpd: Low power domain peripherals reset control
> +			- fpd: Full power domain peripherals reset control
> +
> +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX
> +			  termination resistance can be out of spec due to a
> +			  bug in the calibration logic. This issue will be fixed
> +			  in silicon in future versions.
> +
> +Required nodes	:  A sub-node is required for each lane the controller
> +		   provides.
> +
> +Required properties (port (child) nodes):
> +lane0:
> +- #phy-cells	: Should be 2
> +		  Cell after port phandle is device type from:
> +			- <PHY_TYPE_PCIE 0>
> +			- <PHY_TYPE_SATA 0>
> +			- <PHY_TYPE_USB3 0>
> +			- <PHY_TYPE_DP 1>
> +			- <PHY_TYPE_SGMII 0>

What is the 2nd cell for? The phandle doesn't count for the size.

However, I would simplify this to get rid of the sub nodes and set lane 
in the 1st cell and the type in the 2nd cell.

Rob

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