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Groups > linux.kernel > #1307673 > unrolled thread
| Started by | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
|---|---|
| First post | 2016-01-12 18:40 +0100 |
| Last post | 2016-01-12 23:40 +0100 |
| Articles | 7 — 2 participants |
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[PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-01-12 18:40 +0100
[PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure. Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-01-12 18:40 +0100
Re: [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure. Arnd Bergmann <arnd@arndb.de> - 2016-01-12 23:30 +0100
[PATCH V2 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-01-12 18:40 +0100
[PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-01-12 18:40 +0100
Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Arnd Bergmann <arnd@arndb.de> - 2016-01-12 23:30 +0100
Re: [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and Arnd Bergmann <arnd@arndb.de> - 2016-01-12 23:40 +0100
| From | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
|---|---|
| Date | 2016-01-12 18:40 +0100 |
| Subject | [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and |
| Message-ID | <qQb5g-491-3@gated-at.bofh.it> |
This patch series does modifications to pcie-xilinx.c, to support common
driver on both Zynq and Microblaze architectures.
Microblaze pci-common.c has been modified to support generic driver.
I'm aware Paul Burton <paul.burton@imgtec.com> has also sent patches
related to pcie-xilinx.c, but I'm unable to comment on them.
I request Paul Burton to please add me in cc list so that I can comment on
those patches.
Bharat Kumar Gogada (5):
PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
PCI: xilinx: Removing struct hw_irq structure.
PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on
both Zynq and Microblaze
PCI: xilinx: Updating Zynq PCI binding documentation with
Microblaze node.
Microblaze: Modifying microblaze PCI subsytem to support generic
Xilinx AXI PCIe Host Bridge IP driver
.../devicetree/bindings/pci/xilinx-pcie.txt | 36 +++-
arch/microblaze/Kconfig | 3 +
arch/microblaze/pci/pci-common.c | 61 +++---
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pcie-xilinx.c | 210 ++++-----------------
5 files changed, 98 insertions(+), 214 deletions(-)
--
2.1.1
[toc] | [next] | [standalone]
| From | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
|---|---|
| Date | 2016-01-12 18:40 +0100 |
| Subject | [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure. |
| Message-ID | <qQb5h-491-21@gated-at.bofh.it> |
| In reply to | #1307673 |
Removing struct hw_irq and adding generic PCI core API's.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Removing architecure dependecy structure struct hw_irq which is ARM 32-bit
specific structure, and adding generic PCI core API's to register to
PCI subsytem.
Removing funtions which are not being used with generic API's.
---
drivers/pci/host/pcie-xilinx.c | 81 +++++++++---------------------------------
1 file changed, 16 insertions(+), 65 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f02cfe7..3e3757f 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -117,11 +117,6 @@ struct xilinx_pcie_port {
static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
- return sys->private_data;
-}
-
static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
{
return readl(port->reg_base + reg);
@@ -163,7 +158,7 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
*/
static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
{
- struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+ struct xilinx_pcie_port *port = bus->sysdata;
/* Check if link is up when trying to access downstream ports */
if (bus->number != port->root_busno)
@@ -196,7 +191,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
- struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+ struct xilinx_pcie_port *port = bus->sysdata;
int relbus;
if (!xilinx_pcie_valid_device(bus, devfn))
@@ -228,7 +223,7 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
if (!test_bit(irq, msi_irq_in_use)) {
msi = irq_get_msi_desc(irq);
- port = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
+ port = msi_desc_to_pci_sysdata(msi);
dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
} else {
clear_bit(irq, msi_irq_in_use);
@@ -277,7 +272,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
struct pci_dev *pdev,
struct msi_desc *desc)
{
- struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
+ struct xilinx_pcie_port *port = pdev->bus->sysdata;
unsigned int irq;
int hwirq;
struct msi_msg msg;
@@ -614,47 +609,6 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
}
/**
- * xilinx_pcie_setup - Setup memory resources
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: '1' on success and error value on failure
- */
-static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct xilinx_pcie_port *port = sys_to_pcie(sys);
-
- list_splice_init(&port->resources, &sys->resources);
-
- return 1;
-}
-
-/**
- * xilinx_pcie_scan_bus - Scan PCIe bus for devices
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: Valid Bus pointer on success and NULL on failure
- */
-static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
- struct xilinx_pcie_port *port = sys_to_pcie(sys);
- struct pci_bus *bus;
-
- port->root_busno = sys->busnr;
-
- if (IS_ENABLED(CONFIG_PCI_MSI))
- bus = pci_scan_root_bus_msi(port->dev, sys->busnr,
- &xilinx_pcie_ops, sys,
- &sys->resources,
- &xilinx_pcie_msi_chip);
- else
- bus = pci_scan_root_bus(port->dev, sys->busnr,
- &xilinx_pcie_ops, sys, &sys->resources);
- return bus;
-}
-
-/**
* xilinx_pcie_parse_dt - Parse Device tree
* @port: PCIe port information
*
@@ -704,8 +658,9 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
static int xilinx_pcie_probe(struct platform_device *pdev)
{
struct xilinx_pcie_port *port;
- struct hw_pci hw;
struct device *dev = &pdev->dev;
+ struct pci_bus *bus;
+
int err;
resource_size_t iobase = 0;
LIST_HEAD(res);
@@ -739,24 +694,20 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
dev_err(dev, "Getting bridge resources failed\n");
return err;
}
-
- platform_set_drvdata(pdev, port);
-
- /* Register the device */
- memset(&hw, 0, sizeof(hw));
- hw = (struct hw_pci) {
- .nr_controllers = 1,
- .private_data = (void **)&port,
- .setup = xilinx_pcie_setup,
- .map_irq = of_irq_parse_and_map_pci,
- .scan = xilinx_pcie_scan_bus,
- .ops = &xilinx_pcie_ops,
- };
+ bus = pci_create_root_bus(&pdev->dev, 0,
+ &xilinx_pcie_ops, port, &res);
+ if (!bus)
+ return -ENOMEM;
#ifdef CONFIG_PCI_MSI
xilinx_pcie_msi_chip.dev = port->dev;
+ bus->msi = &xilinx_pcie_msi_chip;
#endif
- pci_common_init_dev(dev, &hw);
+ pci_scan_child_bus(bus);
+ pci_assign_unassigned_bus_resources(bus);
+ pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+ pci_bus_add_devices(bus);
+ platform_set_drvdata(pdev, port);
return 0;
}
--
2.1.1
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| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2016-01-12 23:30 +0100 |
| Subject | Re: [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure. |
| Message-ID | <qQfBU-7kg-23@gated-at.bofh.it> |
| In reply to | #1307676 |
On Tuesday 12 January 2016 23:06:10 Bharat Kumar Gogada wrote: > Removing struct hw_irq and adding generic PCI core API's. > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> > --- > Removing architecure dependecy structure struct hw_irq which is ARM 32-bit > specific structure, and adding generic PCI core API's to register to > PCI subsytem. > Removing funtions which are not being used with generic API's. > typo: s/hw_irq/hw_pci/ Arnd
[toc] | [prev] | [next] | [standalone]
| From | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
|---|---|
| Date | 2016-01-12 18:40 +0100 |
| Subject | [PATCH V2 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function |
| Message-ID | <qQb5h-491-29@gated-at.bofh.it> |
| In reply to | #1307673 |
Removing xilinx_pcie_parse_and_add_res function replacing with
of_pci_get_host_bridge_resources API.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Solved issue with build failure.
Removing xilinx_pcie_parse_and_add_res function and replacing it
with of_pci_get_host_bridge_resources kernel API which does the same.
---
drivers/pci/host/pcie-xilinx.c | 107 ++---------------------------------------
1 file changed, 5 insertions(+), 102 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3c7a0d5..f02cfe7 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -94,8 +94,6 @@
/* Number of MSI IRQs */
#define XILINX_NUM_MSI_IRQS 128
-/* Number of Memory Resources */
-#define XILINX_MAX_NUM_RESOURCES 3
/**
* struct xilinx_pcie_port - PCIe port information
@@ -105,7 +103,6 @@
* @root_busno: Root Bus number
* @dev: Device pointer
* @irq_domain: IRQ domain pointer
- * @bus_range: Bus range
* @resources: Bus Resources
*/
struct xilinx_pcie_port {
@@ -115,7 +112,6 @@ struct xilinx_pcie_port {
u8 root_busno;
struct device *dev;
struct irq_domain *irq_domain;
- struct resource bus_range;
struct list_head resources;
};
@@ -659,97 +655,6 @@ static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
}
/**
- * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
- * @port: PCIe port information
- *
- * Return: '0' on success and error value on failure
- */
-static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
-{
- struct device *dev = port->dev;
- struct device_node *node = dev->of_node;
- struct resource *mem;
- resource_size_t offset;
- struct of_pci_range_parser parser;
- struct of_pci_range range;
- struct resource_entry *win;
- int err = 0, mem_resno = 0;
-
- /* Get the ranges */
- if (of_pci_range_parser_init(&parser, node)) {
- dev_err(dev, "missing \"ranges\" property\n");
- return -EINVAL;
- }
-
- /* Parse the ranges and add the resources found to the list */
- for_each_of_pci_range(&parser, &range) {
-
- if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
- dev_err(dev, "Maximum memory resources exceeded\n");
- return -EINVAL;
- }
-
- mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
- if (!mem) {
- err = -ENOMEM;
- goto free_resources;
- }
-
- of_pci_range_to_resource(&range, node, mem);
-
- switch (mem->flags & IORESOURCE_TYPE_BITS) {
- case IORESOURCE_MEM:
- offset = range.cpu_addr - range.pci_addr;
- mem_resno++;
- break;
- default:
- err = -EINVAL;
- break;
- }
-
- if (err < 0) {
- dev_warn(dev, "Invalid resource found %pR\n", mem);
- continue;
- }
-
- err = request_resource(&iomem_resource, mem);
- if (err)
- goto free_resources;
-
- pci_add_resource_offset(&port->resources, mem, offset);
- }
-
- /* Get the bus range */
- if (of_pci_parse_bus_range(node, &port->bus_range)) {
- u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
- u8 last;
-
- last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
- XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
-
- port->bus_range = (struct resource) {
- .name = node->name,
- .start = 0,
- .end = last,
- .flags = IORESOURCE_BUS,
- };
- }
-
- /* Register bus resource */
- pci_add_resource(&port->resources, &port->bus_range);
-
- return 0;
-
-free_resources:
- release_child_resources(&iomem_resource);
- resource_list_for_each_entry(win, &port->resources)
- devm_kfree(dev, win->res);
- pci_free_resource_list(&port->resources);
-
- return err;
-}
-
-/**
* xilinx_pcie_parse_dt - Parse Device tree
* @port: PCIe port information
*
@@ -802,6 +707,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
struct hw_pci hw;
struct device *dev = &pdev->dev;
int err;
+ resource_size_t iobase = 0;
+ LIST_HEAD(res);
if (!dev->of_node)
return -ENODEV;
@@ -826,14 +733,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
return err;
}
- /*
- * Parse PCI ranges, configuration bus range and
- * request their resources
- */
- INIT_LIST_HEAD(&port->resources);
- err = xilinx_pcie_parse_and_add_res(port);
+ err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
+ &iobase);
if (err) {
- dev_err(dev, "Failed adding resources\n");
+ dev_err(dev, "Getting bridge resources failed\n");
return err;
}
--
2.1.1
[toc] | [prev] | [next] | [standalone]
| From | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> |
|---|---|
| Date | 2016-01-12 18:40 +0100 |
| Subject | [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze |
| Message-ID | <qQb5i-491-45@gated-at.bofh.it> |
| In reply to | #1307673 |
Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
Zynq and Microblaze Architectures.
With these modifications drivers/pci/host/pcie-xilinx.c, will
work on both Zynq and Microblaze Architectures.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Changed Total number of MSI IRQ count logic according to both architectures.
Updated MSI assigning functions accordingly to new count.
Modified irq_domain_add_linear with new MSI IRQ count.
Added #ifdef to pci_fixup_irqs which is ARM specific API.
---
drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3e3757f..1981948 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -92,7 +92,12 @@
#define ECAM_DEV_NUM_SHIFT 12
/* Number of MSI IRQs */
-#define XILINX_NUM_MSI_IRQS 128
+#define XILINX_NUM_MSI_IRQS 128
+#ifdef CONFIG_ARM
+#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS
+#else
+#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS)
+#endif
/**
@@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
*/
static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
{
+ int irq;
int pos;
pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
- if (pos < XILINX_NUM_MSI_IRQS)
+ irq = pos;
+#ifdef CONFIG_MICROBLAZE
+ irq = XILINX_NUM_MSI_IRQS + pos;
+#endif
+ if (irq < TOT_NR_IRQS)
set_bit(pos, msi_irq_in_use);
else
return -ENOSPC;
- return pos;
+ return irq;
}
/**
@@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
free_pages(port->msi_pages, 0);
- num_irqs = XILINX_NUM_MSI_IRQS;
+ num_irqs = TOT_NR_IRQS;
} else {
/* INTx */
num_irqs = 4;
@@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
/* Setup MSI */
if (IS_ENABLED(CONFIG_PCI_MSI)) {
port->irq_domain = irq_domain_add_linear(node,
- XILINX_NUM_MSI_IRQS,
+ TOT_NR_IRQS,
&msi_domain_ops,
&xilinx_pcie_msi_chip);
if (!port->irq_domain) {
@@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
#endif
pci_scan_child_bus(bus);
pci_assign_unassigned_bus_resources(bus);
+#ifdef CONFIG_ARM
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
pci_bus_add_devices(bus);
platform_set_drvdata(pdev, port);
--
2.1.1
[toc] | [prev] | [next] | [standalone]
| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2016-01-12 23:30 +0100 |
| Subject | Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze |
| Message-ID | <qQfBT-7kg-7@gated-at.bofh.it> |
| In reply to | #1307679 |
On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote:
> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
> Zynq and Microblaze Architectures.
> With these modifications drivers/pci/host/pcie-xilinx.c, will
> work on both Zynq and Microblaze Architectures.
>
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
I think this patch should be split into three, as you are doing three
unrelated things here.
> ---
> Changes:
> Changed Total number of MSI IRQ count logic according to both architectures.
> Updated MSI assigning functions accordingly to new count.
> Modified irq_domain_add_linear with new MSI IRQ count.
> Added #ifdef to pci_fixup_irqs which is ARM specific API.
> ---
> drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++-----
> 1 file changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
> index 3e3757f..1981948 100644
> --- a/drivers/pci/host/pcie-xilinx.c
> +++ b/drivers/pci/host/pcie-xilinx.c
> @@ -92,7 +92,12 @@
> #define ECAM_DEV_NUM_SHIFT 12
>
> /* Number of MSI IRQs */
> -#define XILINX_NUM_MSI_IRQS 128
> +#define XILINX_NUM_MSI_IRQS 128
> +#ifdef CONFIG_ARM
> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS
> +#else
> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS)
> +#endif
Something looks wrong here in the microblaze variant. What does NR_IRQS
have to do with it?
> @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
> */
> static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
> {
> + int irq;
> int pos;
>
> pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> - if (pos < XILINX_NUM_MSI_IRQS)
> + irq = pos;
> +#ifdef CONFIG_MICROBLAZE
> + irq = XILINX_NUM_MSI_IRQS + pos;
> +#endif
if (IS_ENABLED(CONFIG_MICROBLAZE))
irq = XILINX_NUM_MSI_IRQS + pos;
> @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
> #endif
> pci_scan_child_bus(bus);
> pci_assign_unassigned_bus_resources(bus);
> +#ifdef CONFIG_ARM
> pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
> +#endif
> pci_bus_add_devices(bus);
> platform_set_drvdata(pdev, port);
Here it looks like microblaze gets it right. I'm not sure why we still
need the pci_fixup_irqs() on ARM, but my feeling is that this should be
fixed in common code.
Arnd
[toc] | [prev] | [next] | [standalone]
| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2016-01-12 23:40 +0100 |
| Message-ID | <qQfLz-7o9-1@gated-at.bofh.it> |
| In reply to | #1307673 |
On Tuesday 12 January 2016 23:06:08 Bharat Kumar Gogada wrote: > This patch series does modifications to pcie-xilinx.c, to support common > driver on both Zynq and Microblaze architectures. > Microblaze pci-common.c has been modified to support generic driver. > > I'm aware Paul Burton <paul.burton@imgtec.com> has also sent patches > related to pcie-xilinx.c, but I'm unable to comment on them. > I request Paul Burton to please add me in cc list so that I can comment on > those patches. Very nice work overall! I've commented on a few smaller things that I think could be improved. Arnd
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